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    24BVD0072 VL2024250106550 Ast02

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    SaήjaγKs

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    24BVD0072 VL2024250106550 Ast02

    Uploaded by

    SaήjaγKs
    12 views4 pages

    Original Title

    24BVD0072_VL2024250106550_AST02

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    Copyright:

    © All Rights Reserved
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    12 views4 pages

    24BVD0072 VL2024250106550 Ast02

    Uploaded by

    SaήjaγKs

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    DIGITAL ASSIGNMENT 2

    Basic Electrical & Electronics Engineering - BEEE102P


    Name: SIDDHANT PANDEY
    Reg. No: 24BVD0072
    Faculty: SOMASUNDARAM D

    --------------------------------------------------------------------------------------------

    Experiment - Design of half adder circuit using logic gates


    Aim: To design and verify a half adder using logic gates

    Apparatus/Tool required:

    S. No. Name of the apparatus Range/Type Quantity


    1 Breadboard Circuit - 1
    2 IC 7486 - 1
    3 IC 7408 - 1
    4 Regulated Power Source 0-15V 1
    5 Resistor 330Ω 1
    6 Connecting Wires - Few
    7 LED - 2

    Basic Theory:

    Half adder circuit is two-bit adder. It is also known as modulo – 2 adder. The expression for logic sum
    S of half adder is
    ̅ B = 𝐴⊕B
    ̅+𝐀
    S = 𝐴𝐁
    The logic expression for carry C is

    C = A.B
    Truth Table:

    INPUTS OUTPUTS
    X Y Sum Carry
    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1
    Circuit Diagram

    Pin Diagram of IC7408 Pin Diagram of IC7468

    Photograph of practical circuit done in the lab

    Green LED = SUM Yellow LED = CARRY


    Procedure:

    1. Connect the circuit as shown in figure


    2. Apply voltages to inputs A and B as represented in the truth table and verify the truth table

    Result:

    A B S=𝐴⊕B C = A.B Photo

    0 0 0 0

    0 1 1 0

    1 0 1 0

    1 1 0 1
    SOFTWARE LAB EXPERIMENT for HALF ADDER
    Aim: To design and verify a half adder using logic gates

    Apparatus/Tool required: NI Multisim

    Circuit -

    Results -

    A B S=𝐴⊕B C = A.B Photo

    0 0 0 0

    0 1 1 0

    1 0 1 0

    1 1 0 1

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