R5434D Series

2 to 5 Serial Cell Li-Ion / Li-Polymer Battery Protection IC for Secondary Protection

NO.EA-267-160407

OUTLINES
The R5434D is an overcharge protection IC for 2 to 5 serial Li-ion/Li-polymer secondary battery. When an
overcharge is detected, after the IC internally fixed delay time, the output of COUT becomes "H". After
detecting the overcharge, when the cell voltage becomes lower than the overcharge release voltage, the
overcharge state is released.
By forcing VDD+3.0V or more to the CTLC pin, the test time of protection circuit board can be shortened, and
overcharge delay time becomes about 1/30. The output type is CMOS.

FEATURES
• Manufactured with High Voltage Tolerant Process
Absolute Maximum Rating ····························· 30V
• Low Supply Current
Cell Voltage 3.9V, for 5-cell ······························ Typ. 3.0µA
• High-accuracy Detector Threshold
Overcharge Detector ······································ ±25mV (Ta=25°C)
• Variety of Detector Threshold
Overcharge Detector Threshold (VDET1n(1)) ·················· 3.6V - 4.6V (in 5mV step)
Overcharge Release Voltage (VREL1n(1)) ··············· VDET1n - 0.1V to VDET1n - 0.4V (in 50mV steps)
Overcharge Detector Output Delay ····················· Typ.1.5s
Overcharge Released Condition ························ Voltage Released Type
• 2 to 5 Cells Selectable Protection
• COUT Output (CMOS Output, Active-high) ········· Typ. 3.7V
(“Low” at normal times, “High” at detecting times)
• Overcharge Delay Time Shortening Function with CTLC pin
VDD+3.0V or more ······································· 1sec to about 1/30
2.0V to VDD-2.0V········································· about 4ms.
• Small Package ·············································· SON-8

APPLICATIONS
● Li-ion or Li-polymer Battery Protection

(1) VDET1n, VREL1n : n =1, 2, 3, 4, 5

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SELECTION GUIDE
The overcharge and the delay time are user-selectable options.

Selection Guide
Product Name Package Quantity per Reel Pb Free Halogen Free
R5434Dxxx$∗-TR -FE SON-8 5,000 pcs Yes Yes

xxx: Specify the combination of the overcharge detector threshold (VDET1n) and the overcharge release
voltage (VREL1n) (1).

VDET1n(2): 3.6 V to 4.6 V in 5 mV step

VREL1n(2): VDET1n – 0.1 V to VDET1n – 0.4 V in 50 mV step

$: Specify the delay time option.

A: Overcharge Detection Delay Time (tVDET1) : 1.5s

∗: Specify the overcharge release option.

A: Voltage Released Type

Product Code List

The product code is determined by the combination of the set output voltage (overcharge detection voltage:
VDET1n, overcharge release voltage: VREL1n), the delay time (overcharge detection delay time: tVDET1), and the
overcharge release options.
Overcharge Detection
Set Voltages (V)
Product Code Delay Time (s) Overcharge Released Type
VDET1n VREL1n tVDET1
R5434D401AA 4.300 4.000 1.5 Voltage Release
R5434D402AA 4.220 4.120 1.5 Voltage Release
R5434D403AA 4.250 4.000 1.5 Voltage Release
R5434D404AA 4.350 4.050 1.5 Voltage Release
R5434D405AA 3.825 3.575 1.5 Voltage Release

(1) Refer to Product Code Table for details.

(2) VDET1n, VREL1n: n = 1, 2, 3, 4, 5
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 R5434D
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BLOCK DIAGRAM

VDD
VD1-1

VC2 Regulator
VD1-2
Regulator

Logic Logic
Circuit Circuit CTLC

VC3 Oscillator DS
VD1-3 Circuit

Counter

Regulator
VC4
VD1-4

COUT

VC5
VD1-5

VSS

R5434DxxxAA Block Diagram

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R5434D
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PIN DESCRIPTION

SON-8
Top View Bottom View
8 7 6 5 5 6 7 8

∗ ∗ ∗

1 2 3 4 4 3 2 1

Pin No. Symbol Description

1 VC5 Positive terminal pin for Cell-5
2 VC4 Positive terminal pin for Cell-4
3 VC3 Positive terminal Pin for Cell-3
4 VC2 Positive terminal pin for Cell-2
5 VDD VDD pin, positive terminal pin for Cell-1
6 CTLC COUT control pin / Output delay time shortening pin
7 COUT Output pin of overcharge detection, CMOS output
8 VSS VSS pin. Ground pin for the IC

∗ The tab suspended leads are connected to the GND level. Do not short or wire those parts to other
voltage level parts.

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NO.EA-267-160407

ABSOLUTE MAXIMUM RATINGS

(Ta = 25°C, VSS = 0V)
Symbol Item Ratings Unit
Supply voltage -0.3 to 30
VDD V
(Positive terminal pin voltage of Cell-1) VC2-0.3 to VC2+6.5
VC2 Positive input pin voltage for Cell-2 VC3 -0.3 to VC3+6.5
VC3 Positive input pin voltage for Cell-3 VC4 –0.3 to VC4+6.5
VC4 Positive input pin voltage for Cell-4 VC5–0.3 to VC5+6.5 V
VC5 Positive input pin voltage for Cell-5 -0.3 to 6.5
VCTLC CTLC pin voltage -0.3 to 30
VCOUT COUT pin output voltage -0.3 to VOH1+0.3 V
PD Power Dissipation (1) 480 mW
Tj Junction Temperature Range -40 to 125 °C
Tstg Storage Temperature Range -55 to 125 °C

ABSOLUTE MAXIMUM RATINGS

Electronic and mechanical stress momentarily exceeded absolute maximum ratings may cause the permanent
damages and may degrade the life time and safety for both device and system using the device in the field. The
functional operation at or over these absolute maximum ratings is not assured.

RECOMMENDED OPERATING CONDITION

Symbol Item Rating Unit
VDD Operating Input Voltage 4.0 to 25 V
Ta Operating Temperature Range −40 to 85 °C

RECOMMENDED OPERATING CONDITIONS

All of electronic equipment should be designed that the mounted semiconductor devices operate within the
recommended operating conditions. The semiconductor devices cannot operate normally over the recommended
operating conditions, even if when they are used over such conditions by momentary electronic noise or surge. And
the semiconductor devices may receive serious damage when they continue to operate over the recommended
operating conditions.

(1) Refer to POWER DISSIPATION in SUPPLEMENTSRY ITEMS for detail information.

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ELECTRICAL CHARACTERISTICS
VCELLn = CELLn (Ex. VCELL1 is a voltage difference between VDD and VC2), n = 1, 2, 3, 4, 5, unless otherwise
noted. The specifications surrounded by are guaranteed by Design Engineering at 0°C ≤ Ta ≤ 60°C.

R5434DxxxAA Electrical Characteristics (Ta = 25°C)

Circuit
Symbol Item Conditions Min. Typ. Max. Unit (1)

Detect rising edge of supply VDET1n VDET1n

VDET1n
CELLn Overcharge voltage (25°C) -0.025V +0.025V
VDET1n V A
Detection Threshold Detect rising edge of supply VDET1n VDET1n
VDET1n
voltage (0 to 60°C) -0.030V +0.030V
CELLn Overcharge Detect falling edge of supply VREL1n VREL1n
VREL1n VREL1n V A
Release Voltage voltage -0.050V +0.050V
Overcharge Detection VCELLn=3.5V (n=2,3,4,5),
tVDET1 1.05 1.50 1.95 s B
Delay Time VCELL1=3.5V to 4.5V,
Overcharge Release VCELLn=3.5V (n=2,3,4,5),
tVREL1 11 16 21 ms B
Delay Time VCELL1=4.5V to 3.5V,
VCELLn=VDET1n+0.050V
Overcharge Detection
to VREL1n-0.100V
tVDTR1 Timer Reset Delay 8 16 24 ms B
to VDET1n+0.050V
Time
to VREL1n-0.100V
CTLC Pin "High1" VDD VDD
VIH-1 V C
Input Voltage -0.7V +0.3V
CILC Pin "High2" VDD
VIH-2 V C
Input Voltage +3.0V
CTLC Pin "Middle" VDD
VIM VDD ≥ 4 V 2.0 V C
Input Voltage -2.0V
CTLC Pin "Low" Input VSS
VIL VDD ≥ 4 V 0.5 V D
Voltage -0.3V
COUT Nch. ON IOL=50μA,
VOL 0.1 0.5 V E
Voltage VCELLn= 3.5V, CTLC= VDD
COUT Pch. ON IOH = 0μA,
VOH1 3.0 3.7 4.5 V F
Voltage1 (at no load) VCELLn = 3.5V, CTLC= VSS
COUT Pch. ON IOH= -50μA, VOH1 VOH1
VOH V G
Voltage VCELLn = 3.5V, CTLC= VSS -0.5V -0.1V
ISS Supply Current VCELLn=3.9V 3.0 7.0 µA H

(1) Refer to TEST CIRCUITS for detail information.

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TEST CIRCUITS

A E
VDD VDD
V
VC2 CTLC VC2 CTLC
V
VC3 VC3
V
VC4 OSCILLOSCOPE VC4
V
VC5 COUT VC5 COUT
V
V
VSS VSS

B F
VDD
VDD
V
CTLC VC2 CTLC
VC2

VC3
VC3

OSCILLOSCOPE VC4
VC4

COUT VC5 COUT

VC5
V
VSS VSS

C G
VDD VDD

VC2 CTLC VC2 CTLC

VC3 VC3

VC4 OSCILLOSCOPE VC4

VC5 COUT VC5 COUT

VSS V
VSS V

D H
VDD A VDD

VC2 CTLC VC2 CTLC

VC3 VC3

VC4 OSCILLOSCOPE VC4

VC5 COUT VC5 COUT

VSS V VSS

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R5434D
NO.EA-267-160407

THEORY OF OPERATION

Overcharge Detectors, VDET1n (n=1, 2, 3, 4, 5)

While the cells are charged, the voltage between VDD pin and VC2 pin (voltage of the Cell-1), the voltage
between VC2 pin and VC3 pin (voltage of the Cell-2), the voltage between VC3 pin and VC4 pin (voltage of
the Cell-3), the voltage between VC4 pin and VC5 pin (voltage of the Cell-4), and the voltage between VC5
and VSS pin (voltage of the Cell-5) are supervised. If at least one of the cells’ voltage becomes equal or more
than the overcharge detection voltage, the overcharge is detected, and an external charge control Nch. FET
turns ON with COUT pin being at "H" level and by cutting off a fuse on the charger path, and the charge
operation stops.
To reset the overcharge and make the COUT pin level to "Low" again after detecting overcharge, in such
conditions that a time when all the cells’ voltages are down to a level lower than overcharge release voltage.
Internal fixed output delay times for overcharge detection, overcharge detector timer reset, release from
overcharge exist. Even if one of voltage of the cells keeps its level more than the overcharge detection voltage,
and output delay time passes, overcharge voltage is detected. If all the cell voltages become lower than the
overcharge detection voltage within the overcharge detection delay time by noise or other reasons, the time
period is less than overcharge detector timer reset output delay time, the overcharge delay time is accumulated
and maintained, and the accumulated delay time reaches the overcharge delay time, the overcharge is
detected. After detecting overcharge, even if all the cell voltages become equal or less than the release voltage
from overcharge, if at least one of the cells voltage becomes higher than the release voltage from overcharge
within the overcharge release delay time from overcharge, then overcharge is not released.
The output type of the COUT pin is a CMOS output between VSS and the built-in regulator, and "High" level
of COUT pin is the output voltage of the built-in regulator.

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 R5434D
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Connect Charger Connect Load

V CE LL1
VDET11
VREL11

V CE LL2 t

VDET12
VREL12

V CE LL3 t

VDET13
VREL13

V CE LL4 t

VDET14
VREL14

V CE LL5 t

VDET15
VREL15

C OUT t
V+
tVDET1 tVDET1

tVREL1 tVREL1

VSS
Ch ar ge / Disc h ar ge t
Cu r r e n t
Charge
Current

0
Discharge t
Current
Overcharge Operation Timing Chart

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Delay Shortening (DS) Function

The COUT pin is forcibly set to "High" output with applying the VSS level voltage to the CTLC pin.
By applying VDD+3.0V or more voltage to the CTLC pin, the overcharge detect and release delay times can
be shorten into approximately 1/30. (DS mode 1)
By applying the voltage in the range from 2.0V to VDD-2.0V to CTLC pin, the overcharge detect delay time
can be shorten into approximately 4ms. (DS mode 2)
The CTLC pin has internally the input delay time (approximately 1ms).

Table. CTLC Pin Input Conditions and IC’s Operating Conditions (VDD ≥ 4.0 V)
Input Conditions to CTLC Pin IC Operating Conditions
VDD+3.0V or more DS mode 1
VDD-0.8V to VDD+0.3V Normal operation
2.0V to VDD-2.0V DS mode 2
VSS-0.3V to 0.5V COUT output "H"
Open Indefinite

Setting for 2 to 4 Cell Protection

By short-circuiting between cells, the R5434D can meet as a protection IC for 2, 3, or 4 cells placed in series.
The following table indicates pins to short-circuit to VSS depending on protected cells.
Protected Cells Pins to Short-circuit to VSS
2-cell protection VC3, VC4, and VC5 pins
3-cell protection VC4 and VC5 pins
4-cell protection VC5 pin

If providing other connections except above short-circuit for 2, 3, or 4 cells protection, perform thorough
evaluation using the actual devices.

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 R5434D
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TYPICAL APPLICATIONS
Typical Application Circuits
SC PROTECTOR

R1
VDD CTLC
CELL1 R2 C1
VC2

CELL2 R3 C2
VC3

CELL3 R4 C3 R5434D
VC4
Normal Output: ”L”
CELL4 C4 COUT
R5
“H” Active
VC5

CELL5 C5

VSS

5-cell Protection Circuit

SC PROTECTOR

R1
VDD
CTLC
CELL1 R2 C1

VC2

CELL2 C2
R3
VC3

CELL3 R4 C3 R5434D
VC4
Normal Output: ”L”
CELL4 C4 COUT
“H” Active
VC5

VSS

4-cell Protection Circuit

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R5434D
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SC PROTECTOR

R1
VDD
CTLC
CELL1 R2 C1

VC2

CELL2 C2
R3
VC3

CELL3 C3 R5434D
VC4
Normal Output: “L”
COUT
“H” Active
VC5

VSS

3-cell Protection Circuit

SC PROTECTOR

R1
VDD
CTLC
CELL1 R2 C1

VC2

CELL2 C2

VC3

R5434D
VC4
Normal Output: “L”
COUT “H” Active
VC5

VSS

2-cell Protection Circuit

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External Components
Symbol Min. Typ. Max. Unit
R1 / R2 / R3 / R4 / R5 330 330 1000 Ω
C1 / C2 / C3 / C4 / C5 0.01 0.1 1 µF

Technical Notes on Selection Components

● The voltage fluctuation is stabilized with R1 to R5 and C1 to C5. If a R1 to R5 is too large, by the
conduction current at detection, the detector threshold may shift higher. Therefore, the appropriate value
range of R1 to R5 is equal or less than 1kΩ. To make a stable operation of the IC, the appropriate value
range of C1 to C5 is 0.01µF or more.
● The typical application circuit diagrams are just examples. This circuit performance largely depends
on the PCB layout and external components. In the actual application, fully evaluation is necessary.
● Overvoltage and the over current beyond the absolute maximum rating should not be forced to the
protection IC and external components. During the time until the fuse is open after detecting
overcharge, a large current may flow through the FET. Select an FET with large enough current
capacity in order to endure the large current.
● To connect the SC protector, connect the SC protector to the cell must be the last.

Contact Information for Inquiries regarding SC PROTECTOR

Dexerials Corporation (Sony Chemical & Information Device Company Ltd.)
Gate-city Osaki East Tower 8F, 1-11-2 Osaki, Shinagawa, Tokyo, 141-0032
TEL: 03-5435-3946
URL: http://www.dexerials.jp

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TYPICAL CHARACTERISTICS
Vs. Temperature
1) CELLn Overcharge Detector Threshold 2) CELLn Overcharge Release Voltage
vs. Temperature vs. Temperature
R5434D401AA n=1, 2, 3, 4, 5 R5434D401AA n=1, 2, 3, 4, 5

VCELLn=3.2V VCELLn=3.2V
4.35 4.05
4.33 4.03

VREL1n(V)
VDET1n(V)

4.31 4.01
4.29 3.99
4.27 3.97
4.25 3.95
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

Ta (℃) Ta (℃)

3) Overcharge Detection Delay Time 4) Overcharge Release Delay Time

vs. Temperature vs. Temperature
R5434D401AA n=1, 2, 3, 4, 5 R5434D401AA n=1, 2, 3, 4, 5

VCELLn=3.5V、VCELL1=3.5V→4.5V VCELLn=3.5V、VCELL1=4.5V→3.5V
2.0
23.0
1.8
tVREL1(msec)
tVDET1(sec)

1.6 18.0

1.4
13.0
1.2
1.0 8.0
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

Ta (℃) Ta (℃)

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 R5434D
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5) Timer Reset Delay Time vs. Temperature 6) COUT Nch. ON Voltage vs. Temperature
R5434D401AA n=1, 2, 3, 4, 5 R5434D401AA n=1, 2, 3, 4, 5

VCELLn=3.5V、VCELL1=4.5V→3.5V→4.5V VCELLn=3.5V、VCELL1=4.5V→3.5V→4.5V
0.30
23.0
0.25
tVTR1(msec)

18.0 0.20

VOL(V)
0.15
13.0 0.10
0.05
8.0 0.00
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

Ta (℃) Ta (℃)
7) COUT Pch. ON Voltage vs. Temperature 8) COUT Pch. ON Voltage vs. Temperature
(at No Load)
R5434D401AA n=1, 2, 3, 4, 5 R5434D401AA n=1, 2, 3, 4, 5

VCELLn=3.5V、ILOAD=0µA VCELLn=3.5V、ILOAD=-50µA
0.00
4.50
-0.10
VOH-VOH1(V)

4.00
VOH1(V)

-0.20
3.50
-0.30

3.00 -0.40
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100

Ta (℃) Ta (℃)

9) Supply Current vs. Temperature

R5434D401AA n=1, 2, 3, 4, 5
VCELLn=3.9V
4.00

3.00
Iss(uA)

2.00

1.00

0.00
-60 -40 -20 0 20 40 60 80 100

Ta (℃)

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Output Delay Time vs. Supply Voltage (VDD) Dependence

1) Overcharge Detection Delay Time vs. VDD 2) Overcharge Release Delay Time vs. VDD

R5434D401AA R5 4 3 4 D4 0 1 AA
VCELL1=0.4V, 1.6V, 2.4V, 3.2V,4.0V→4.5V VCELL1 =0.4V、1.6V、2.4、3.2V、4.0V→4.5V
20.0
2.00
19.0
1.80 18.0
tVDET1 (sec)

tVREL1 (msec)
17.0
1.60
16.0
1.40 15.0
14.0
1.20
13.0
1.00 12.0
0.0 0.8 1.6 2.4 3.2 4.0 4.8 11.0
10.0
VCELLn (V) n=1, 2, 3, 4, 5
0.0 0.8 1.6 2.4 3.2 4.0 4.8
VCELLn (V) n=1、2、3、4、5

Supply Current vs. VDD (for 5 Cells Protection)

SC PROTECTOR

4 R1
VDD
A 1kΩ
CTLC
CELL1 C1
3
Supply Current[uA]

R2 0.1µF
VC2
1kΩ
C2
CELL2 R3
2 0.1µF
VC3
1kΩ
C3
CELL3 R4 0.1µF R5434D
1 VC4
1kΩ Normal Output: “L”
C4 COUT
CELL4 R5 0.1µF “H” Active
VC5
0 1kΩ
0 10 20 30 CELL5
C5
VDD[V] 0.1µF
VSS

Test Circuit

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 R5434D
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Vs. External Resister dependence

Overcharge Detection Voltage / Overcharge Release Voltage vs. R1

VDET11 VREL11
4.330 4.050

4.320 4.040

4.310 4.030
VDET11(V)

VREL11(V)
4.300 4.020

4.290 4.010

4.280 4.000

4.270 3.990
0 500 1000 1500 2000
R1(Ω)

SC PROTECTOR

R1
VDD
CTLC
C1
CELL1
R2 0.1uF
VC2
1kΩ C2
CELL2
R3 0.1uF
VC3
1kΩ C3
CELL3 R5434D
R4 0.1uF
VC4
1kΩ Normal Output: “L”
C4
CELL4 COUT
R5 0.1uF “H” Active
VC5
1kΩ C5
CELL5
0.1uF
VSS

Test Circuit

17
POWER DISSIPATION SON-8
Ver. A

The power dissipation of the package is dependent on PCB material, layout, and environmental conditions.
The following conditions are used in this measurement.

Measurement Conditions
Standard Test Land Pattern
Environment Mounting on Board (Wind Velocity = 0 m/s)
Board Material Glass Cloth Epoxy Plastic (Double-Sided Board)
Board Dimensions 40 mm × 40 mm × 1.6 mm
Top Side: Approx. 50%
Copper Ratio
Bottom Side: Approx. 50%
Through-holes φ 0.5 mm × 44 pcs

Measurement Result (Ta = 25°C, Tjmax = 125°C)

Standard Test Land Pattern Free Air
Power Dissipation 480 mW 300 mW
Thermal Resistance θja = (125 − 25°C) / 0.48 W = 208°C/W 333 /W

600

480 Standard Test Land Pattern

Power Dissipation PD (mW)

500

400
Free Air
300

200

100

0
0 25 50 75 85 100 125 150

Ambient Temperature (°C) IC Mount Area (mm)

Power Dissipation vs. Ambient Temperature Measurement Board Pattern

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PACKAGE DIMENSIONS SON-8
Ver. A

2.9±0.2 0.13±0.05 +0.10 +0.10

0.15-0.15 0.15-0.15
0.475TYP
8 5

0.23±0.1

0.2±0.1
3.0±0.2
2.8±0.2

0.2±0.1
1 4
0.13±0.05

0.9MAX

0.65 0.1
0.3±0.1
0.1 M

SON-8-18 Package Dimensions (Unit: mm)

*

∗ The tab suspension leads on the bottom of the package is substrate level (GND). It is recommended that the tab
suspension leads be connected to the ground plane on the board, or otherwise be left floating. Also, the tab suspension
leads should not connect to other wires or land patterns.
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with a view to contributing to the protection of human health and the environment.
Ricoh has been providing RoHS compliant products since April 1, 2006 and Halogen-free products since
Halogen Free April 1, 2012.

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