PAPER II

Study of Logic Gates and Verification of De Morgan's Theorems 71

Study of a Boolean Equation 81
Study of Ex-OR Gate-and its Use as Controlled Inverter 85
Determination of Noise Margin in T1L Gates 91
Study of R-S Flip-Flop Using NANO or NOR Gate 96
Study of Multiplexer IC 74153 101
Study of Demultiplex~ Using IC 74139 105
Study of Encoder Using IC 74147 108
Study of Decoder Using IC 7447 / 7448 112
Study of Decade Counter Using IC 7490 116
Construction of Half- adder 120
Full adder using Logic Gates 122
·Stud)' of 4 - bit Binary Adder Using IC 7483 124
14 Square Wave Generator Using Schmitt Trigger Inverter 129
15 Digital to Analog Converter Using R-2R Ladder 133
16 Study of Diode Matrix ROM 138
17 Familiarisation with Computer 141
• PROJECT REPORT • 145
• Model Project Report 146
• Some Practicable Projects : Circuits and Components 152

•••••••••
• • •

-.c ctr :rt

r-r;t,f.;.f
~,,- ~•.1:- "'~
/!J.yj;..~ ~---, ... ~-- -·--·---·- -·····'"'-· •·- -·- ---··•-

w'

STD. XII - SCIENt:E

PRACTICAL ELECTRONICS

Exper iment No. 1

Study of Logic Gates and Verification of De Morgan's Theore ms

expJ: (i) To identify given !Cs and to verify the truth-table for each type of logic
Aim
gate.
e.< p 2 _ (ii) To verify De Morgan's theorems.
<'.., p 3 (iii) To construct the basic gates using NANO/NOR gates.
. Component List

Type of Component Specifications

IC 7432 Quad - 2 - Input OR gate TIL IC, Supply V =5V
7408 Quad - 2- I~put AND gate TIL IC,
.
" 7404 Hex INVERTER TIL IC
c,C.({
"('
7400 Quad - 2- Input NAND gate TIL IC
7402 Quad 2-Input NOR gate TIL IC

Resistor R 330 .Q, + 5%, _!_ W. Carbon composition

4
LED ........... .......... Colour; V = .......... .
F
'

Equipments and miscellaneous : 5V de regulated power supply, switches (SPOT) -· , ,

ir-r rr- L ;-

Identification and pin configurations :

14 13 12 11 10 9 8
., +Vee
L -,r \ _;

IC 7432

GND
1 2 3 4 5 6 7

(a) Quad 2 - input OR gate IC

__ ____ ..., ____ _. ____

, ... - -
72
'V\.1ro,,
~ p,tEP-"
73
+Vex
14 J3 12 11 10 9 8

IC 7402

JC 7408

- .... uu GND
GND 1234 5 67
(e) Quadruple 2 - input NOR gate IC
2 3 4 5 6 7
~ l.1 : Pin confiruratu,,as
(bJ Quad 2 • input AND gate IC Pan I : Study of Logic gates
CifCuit diagrams :
~ I f j
I
14 13 12 11 JO 9 8
+Vr:x +5V

IC 7404
7 ~I\. I
I~-17 fR ~

GND
f s2 J 1~ ~
2 3 4 S 6 7 '::
-=
Fig.(a) Fag.(b) Fig. (c)
(c) flex INVERTER I I .+5V ,+5V
\. ·' { .,
.,
14
-. V •

R I I . 8 l3 17 $R
'--

s2 I
IC 7400
~
¥1
- -
Fig. (d) Fig. (e)

GND Fig. 1. 2 : Circuit diagrams

2 3 4 5 6 7
Procedure :
Talce IC 7432. Consider one of its gates. Connect the supply of regulated 5 V d~ to the
(d) Quadruplt: 2 • input NAND gace IC supply terminals of IC. Now give different combinations of inputs (either by connecting to+ 5V
or to ground ) and verify the truth table for the gate. Glowing LED indicates logic 1and LED in
off state indicates logic O.
 74
Std. XII Science ■ Practlca 1Electr

Replace the IC and ven'fYth e b"U th table. Repeat this procedure for !Cs 7408 740 ol'lics a·QS;~ II •
,,,.
. ' 4, 740() Part II : Vcrif v f .2. 75
7402 cation of D
Observations : a,d .,ii c)iagraDl5 : I. e Morgan', theo
CifC ()e Morgan's first theorem : Logic . rein.,
A and B are mputs
• and Y is output. A B y , equation : - -
+SV A+B:::A·B
1. IC 7432 (OR gate) 0 0 0
0 I 1
Logic equation
I 0 \
Y=A+B
I I I

Truth table
+5V
IC 7404
2, IC 7408 (AND gate)
A B y 1
r·--~ -::- +5V
Logic equation 14 IC 7408
0 0 ("'
3 - -
Y=A·B 0 1 (' A-B
I 0 0
1 1 \

Truth table

3. IC 7404 (Hex INVERTER) Fig. 1.3: De Morgan'sfirstth eorem.- Cvcuil

. d'
+5V iagram

ffi!J
Logic equation +5V
A I 14 IC7400
Y=A
B A-B
Truth table 2
- R
4. IC 7400 (NANO gate)
y-
,.,,,,
Logic equation A B _,;;,
-
0 0 j
+5V
Y=A·B 0 1 I 14 IC7432
3 -A+B
-
1 0 \
1 1 0 R
Truth table -
5. IC 7402 (NOR gate)
y-
-
A 'B
Logic equation ' Fig 1.4 : De Morgan's second theorem - C;cuil diagram
0 0 I Procedure :
0 1 •'
1 theFor . ven'fiication
cir the • of De Morgan's first theorem,• take !Cs 7402.7404 and 7408. Connect
0 I
differccwts as shown m • p·1g. J.3. Connect the supply of reguIated 5V dc to the IC~ Now give
I I '
~
table 01 combinations of inputs (either by eoonecting to +5 Vor to ground). Verify the truth
Truth table s.
I I I (\I ~I I ' - th For the ven'fi1cation of De Morgan's second theorem, take ICs 7400, 7404 and 7432. Follow
e same procedure. Verify the truth tables.
 74 Std. XII Science ■ Practical Ele
ctrorr
ic, p~rtll
Replace the IC and verify the truth table. Repeat this procedure for ICs 7408, 7404, 740o tv~ .2.
Pan II : Vcrificati 75
~2. ~ t, on of De Morgan' th
Observations : dfagraJDS : s corcrns
y
Ci~~ Morgan's first theorem: Logic equation: __
A and B are inputs and Y is output. A 8 +5V A+B==A-8
1. IC 7432 (OR gate) 0 0 0

Logic equation 0 I I A 2
I B
I 0 A+E
Y=A+B 3
I I I
-
Truth table +SV
IC 7404
2. IC 7408 (AND gate) 14 -=- +5V
A B y
14 IC 7408
Logic equation 0 0 (
3
A-B
Y=A·B 0 I ('
3 7
1 0 0 R
1 1 I
-
Truth table
Fig. 1.3 : De Morgan's first theorem . Circuit diagram
3. IC 7404 (Hex INVERTER)

~
+5V +5V
Logic equation A I 14 IC7400
Y=A B u--- A-B
Truth table R

4. IC 7400 (NANO gate) +5V ,;,,

.,,:,,
A 8 y IC7404
Logic equation 0 0 I 14 -= 5V
IC7432
Y=A·B 0 1 I 3 A+B
1 0 l
1 1 0
Truth table

5. IC 7402 (NOR gate) y . Circuit diagram

A B Fig 1.4: De Morgan's second theorem
Logic equation 0 0 I Procedure •• . • talc ICs 7402 7404 and 7408. Connect
0 1 l For the verification of De Morgan's first tbeorem, f e lated sv de to the ICs. Now give
Y=A+B
the circuits as shown in Fig. 1.3. Connect the suppl~ reg5u y or to ground). Verify the truth
0
I 0 (,
.~ 'th b connectmg to +
I I ') dluerent combinations of inputs (e1 er Y
tables. C 7404 and 7432. Follow
Truth table , nd theorem, take I s7400'
For the verification of De Morgan s seco
r,r ,\1 "ll1 -
the same procedure. Verify the truth tables.
 Science ■ Practical Electr0nL~I pf!'fR 11 ~t basic gates using NOR gates
d
~- XII
"
Obsemltiom : A and B are inputs. 'fo co (IC 7402) ·
77

De Morgan•s first theorem -

=-- +5V +5V
B LHS=A+B RHS=A·B
A
0 0 Y==A r---l_
iL
Pin14
--,
R i
0
I
1
0 1 IC7402 ·.,:,, Y=A+B

I I ,/f ·---
R
(a) IC7402

De Morgan's second theorem -

(b)

A B LHS =A·B RHS=A+B

+sv
0 0 +SV
0 l
SI
r·······--··-I'~:~--····....._.,
: I

1 0 ·2 :
I
I

1 1 ~ i
I
I

A iJ I
I
I

: 10 !
fvr 3 I
: x:>i
Part III: Construction of basic gates using NANO/ NOR gates - s2 I
I I
1 •Y=A·B
I
:5 I

Circuit diagrams : : I
I
I
I
R
To construct basic gates using NAND gates (IC 7400) - jBL./4~ !
~--~C7400...................IP1iiT....
I '-.

.J
I

+5V
Pin 14
+SV S 1
At
114
b3 ,
-
Y=A
+5V
s,
~i y =-A·r. tvr ~
(c) 1
j_ R
I

,,,:,, 5 ..l ~ R Fig. 1.6 : Construction of basic gates using NOR gates
IC7400 ,,,:,, I Pin 1 s (a) NOT gate, (b) OR gate, (c) AND gate
IC7400 ~-t
(a) (b) :i-·---- Procedure :
Take IC 7400. Connect the supply of regulated 5V de to the supply terminals (pin 14 to +5V
,
°'V and· pin 7 to ground). Construct NOT gate by making connections as shown in
t5V ')'
1 ..-----··3··I·······-···-····
.,--•·····- m 14
--·, Fig,(1.5) (a). Now give different combinations of inputs (either by connecting to +SV or to
/ground) and verify the truth table of NOT gate.
biI Y=A+B Similarly. construct AND gate and OR gate. Check the outputs for different combinations

~
of inputs and verify the truth tables.
4
····-·r.; Now take IC 7402. Construct NOT, OR and AND gates as shown Fig. (l.6) and verify
...
IC7400 -::-Pini°-
their truth tables.
~
~
Observat·
. ions : A and B are inputs and Y is the output.

ru
(c)
1. NOT gate using NANO gates:
Fig. 1.5 : Construction of basic gates using NAND gates
(a) NOT gate, (b) AND gate, (c) OR gate. Y=A
~

" ~,•
 Std. XII Science • Practical ElectrOl)jct
78 ~II 79
P . a high output only when all inputs are high F
y
A B
P'°.v1deSI Th~ NA
,opu •
ND , h h. • or NOT ga1c
gate as a igh output when I
h II •
.
output is always opposite to
0 0 rht at east one of ·rs.
2. AND gate using NANO gates: ate i,as a high output w en a mputs arc tow• I tnputs is low. The NOR
0 I
y =A· B g ,5 first theorem : Statement : The complement bf .
I 0 ~organ of the complements. a logical sum equals the logical
1 I
ve ,,,duct _ _ _
p . A+B=A·B
..ic equation •
A B y "°I,' , 8 second theorem : Statement : The com
0 0 .,10rgan
pe " . 1 um of the complements. P1ement of a logic product equals the
3. OR gate using NANO gates :
0 I 1og1ca s - - --
Y=A+B ·on • A •B = A + B .
1 0 quati •
1 1 IA" eThcrefore NOR gate is equivalent to bubbled AND gate and NANO t • •
. . . ga e 1s equ1va1cnr to
bblcd QR gate. OR, AND and NOT gates ~re the basic building blocks of all logic circuits.
b~t NAND or NOR gate~ can be ~sed to bu1~d a_ny ~asic gate. Hence, only NANO gates or
4. NOT gate using NOR gates :
Y=A ruA B y
B NOR gates are sufficient to build any logic c1rcuu. Therefore, NANO and NOR gates are
only·• .. 'Universal building blocks' or 'Universal gates·.
,/ calico as
A The JCs 7400, 7402, ~404, 7~08, 7432 ar~ from standard TTL family. ForITLdevices, any
, e from Oto 0.8 V 1s considered Low input and any voltage from 2 to 5 Vis considered
0 0 v~lt~~10 put. Any voltage from Oto 0.4 V is Low output and any voltage from 2.4 to 3.9 Vis High
s. OR gote using NOR gates 0 1
Hig t. ror 7400 series supply voltage range is 4.75 to 5.25 Vover a temperature rarige of Oto
outpu
Y=A+B 70°C.
1 0
1 1 Logic gates can be used to build_ fl_ip-flops, adders, digital counters etc. which can be used in
calculators, computers and other dtgttal sylltcms.
A B y Model Slips :
6. AND gate using NOR gates 0 0 SI' (1) : You arc given following ICs: -. -. •. .
Y =A· B 0 1 ip ( •) ldenti fy them and draw their pin configurations. Write their typical specific~;)
1 0 ~~- w
1 1 (h) Draw the circuit diagram for testing the logic gates.
• (5)
Conclusion : (c) Connect the circuit and get it checked by the exa111mer. . -
1. Input/ Output conditions of different ICs follow their respective truth-tables. Thus, all
X (d)
•
Verif the truth-table for each type o~ lo~1c ( I t one gate from each of
gate at_ e'.'5 ts
truth tables were verified. abov~ ICs) by ·giving different combmat1ons of logic mpu • (5)
I t 2. Logic circuits for De Morgan's theorems were constructed and their truth tables were d th-table for each. Hence write
verified. (c) Write the expected truth-table and observe tru (5)
r I the logic equation for each gate. (5)
3. Any basic gate cun he constructed using only NANO or NOR gates.
Theory (f) Oral. (5)
Gate i:- u logic rin:uit wi1h one or mmc input :-ignals. but only one output signal. Gates are Slip (2) You arc given following lCs : •• ·, •• . Write theirtypical specifica-
\.., tligirul circuits because the input und ou1pu1 signals arc either low (0) or high (I) voltages. A (a) Identify them and draw their pin configurattons. (5)
lruth table !--hov,,s nil inpul un<l output possibilities for a logic circuit. Total number of combina·
11
lions is 2 where. 11 is the number of input:-. OR. AND und NOT arc the basic gates. NANO tions. . d draw the circuit diagrams for verifying th~;·
(b) State De Morgan's th eorems an
..
ond NO}{ urc tlcrivctl gate:-. The OR gate has a high output if any input is high. The AND gate
 e
Std. XII Science ■ Practical 18,_. ~tt'PY.Wt
w;m.s
80 ...,roruc.

Connect the circuitc; and show them to the examiner.

(c) (5)
Test the outputs for various combinations of inputs.
(d) Experirnent No. 2
Tabulate the results (5) Study of a Boolean Equation
Compare the experimentally observed results and expected results.
(e) (5)
Oral. (f) (5)
~iJJl (i) To draw logic dia&ram for given Boolean equation.
Slip (3) : You are given following ICs : -, -. -.
(a) Identify the tCs and draw their pin diagrams showing the arrangement 0 f (ii) To simplify given logic equation and to draw the logic diagram_
Write the specifications of ICs. &ates. (iii) To construct the logic circuit and test it.
· . h b • • (5)
(b) Draw the circuit diagram tor constructing t e as1c gates usmg NAND/
Noa. ColllPonent list :
5
1" (c) Connect the circuit and get it checked by the examiner. '( )
5
(d) Switch the circuit ON and check the outputs for different combinations f. ( ) • Type of Component
. 01np SJ)edfications
Present the result m the fonn of truth table. I Uts, I

IC 7404
(c) Compare the expected result-; and experimentally observed results (in tah (S) Hex INVERTER TIL Supply V=5V
~~- ~5 7408 Quad- 2- Input AND gate TIL IC,
(t) Oral. ()
(5)

..
7432 Quad -2-Input OR gate TIL IC

mwz,,r~-~.., ~ ~ ~ - < & " < , . v...-.:-»x•

~~~~~
.,:;
•••.
:o~rr;: ; :
I
Resistor R 330 n, ± 5%, ! W. Carbon composnion.
4
LED .....................Colour ' Vp=...............
I. Define gate. State the types of basic and derived gates.
2. Explain basic gates with definition and logic equation.
3. Why NANO and NOR gates are called universal building blocks? Equipments and miscellaneous :
4. From which family are the ICs used for this experiment? What are voltage levels for Low 5 V de regulated power supply, switches (SPOT).
( and High inputs and outputs?
5. State De Morgan's theorems. What are the logic equations for De Morgan's theore~.?
Given Boolean Equation :
- -
Y =(A+ B) (A+ B) (A +C)

Logic diagram for given Boolean equation

□□□

A~A
C ~------1:5
A+B -
Y =(A+ B) (A+ B) (A+ C)
B ' I J

-
A+B

Fig. 2.1 : Logic diagram for given Boolean equation

XIIPract
lcal Electronics / 6

,
82
Std XII Science ■ Practical EJectr .
• o~1~
I
pAP~
~Fl II

+5V 83
Logic gates used in this logic diagram are :
IC 7408
Sr.No. Type of gate IC
1 NOT 7404
2 OR 7432 Y:::A·C
3 NOT 7404 R
4 OR 7432
5 OR 7432
6 AND 7408
Fig.
• 2•4 •• Circuit diagram /or simplified logic equlllion
Simplification of given logic equation : obserYations :
Y=(A+B) (A+B) (A+<:) Expected truth table Experimental truth table
=(A.A+A.B+A.BtB..B) (A+C)
=(A+A.B+A.B+O) (A+C)
s:1 Y=A·C l A C y
0 0
0 0
............... A.A=A, B.B=0 0 1 0 0 I
= A(l+ B+ B) (A +C) 1. 0 0 I 0
= A(l + 1) (A+ C) .............. B + B = 1 1 1 1 l I
=A(l) (X+c) conclusion :
= A.A + A.C ............... A.l =A Any
. Boolean
. equation
. can be simplified by using
. laws of Boolean algebra. Log1c • c1rcu1t
• . for
=0+AC ............... A.A= 0 simplified logic equation was constructed. Expenmental truth-table was verified by comparing
it with expected truth ~ table.
=AC
Theory: 'A
~==[)-- Y=A·C George Boole found the missing link between mathematics and logic by inventing symbolic
Fig. 2.2 : Simplified logic diagram logic, known as 'Boolean algebra'. Each variable in Boolean algebra has either of two values,
low (0) or high ( 1). This two state algebra can be used to solve logic problems and to analyze
For the simplified logic equation, only one AND gate is necessary. Therefore, use IC 7408. and design computer circuits. Its advantages are simplicity, speed and accuracy. In positive
Pin Connections : logic system, l represents the more positive of two voltage levels and Orepresents the other
voltage level. In negative logic, 1 represents the more negative of two voltage levels. Some
14 13 12 11 10 9 8 :important laws of Boolean algebra are :
+Va:,,
I I' 'I I I I I I I I I (1) A+ 0 = A (2) A · 1 = A (3) A+ 1= 1
(4) A·0=O (5) A+A=A (6) A·A=A
(7) A+ A = 1 (8) A · A = 0 (9) A = A
IC 7408 {10) A+ B =A. B (De Morgan's first theorem)
01) A· B =A+ B (De Morgan's second theorem)
02) A+AB=A (13) A+A·B=A+B
GND
2 3 4 5 6 7 Model Slip : You are given following Boolean equation y ==
)( (5)
Fig. 2.3 : Quad 2 - input AND gate IC - Pin connections . d list the gates required.
(a) Draw the logic diagram for the above equauon an

....-dil.liiJkffl,U,JIU A
i,':;<i\'Miti~
 Std. XII Science ■ Practical Ele
ctrori~
84
o•C d'tagr
(b) Reduce the equation using the laws of Boolean algebra and again draw the looi
~
(5) Experirnent No. 1
(c) List the ICs required. Give their pin connections and specifications. Studyo
(S) f Ex-OR Gate and its Use as Controlled lnvcncr
(d) Connect the circuit and test it.
(e) Verify the output of the circuit by comparing the experimental results and expected (S)
: (i)
To conslruct and test Ex- OR &ate and Ex- NOR gate using basic gates.
results. Tabulate the results. (S) I ~illl (ii)
To construct and test Ex-OR gate using NANO gates.
(f) Oral. (S) (iii) To study the operation of controlled invener.

IB-,~~,-., ., ~;-~~ ···'~"'='<1t<:i:~:-. ,, c,,otP00ent list

mwwt@f ~
Type of Component Specifications
I. Comment on Boolean 1J11;ebra. 'IC 7400
Quad - 2 - Input NAND gate ITL IC
7404 Hex lNVERTER TTL IC
2. Explain positive and negative logic.
7408 Quad • 2 • Input AND gate ITL IC
3. Which ICs are used for OR, AND and NOT gates?
7432 Quad • 2 • Input OR gate TTL IC
4. What are the logic outputs for A + A and A.A?
7486 Quad-2-Input Ex-OR gate TTL IC
5. What are the specifications for 1TL ICs?
Resistor R 220 Q ± 5%, .!.4 W. •carbon composition
LED ..................... colour, VF=.............

□□Q Equipments and miscellaneous •

5 V de regulated power supply, switches (SPDn.
wgic diagram :
+5V 740i 7~

7432
9
Y=A·B+A·B=AEBB

Fig. 3.1 : Ex- OR gaJe 11sing basic gates

IC
Sr.No. Type of gate
NOT 7404
l
NOT 7404
2
AND 7408
3
AND 7408
4
OR 7432
5 I
86
Std XII Science ■ Practical Elect
• • roni
C\
I pr !!fl 11
AP"'
14 13 12 ~
+Vee
Observations
Truth table of Ex-OR gate using basic gates

A B y
0 0 IC 7486 Quad 2- input
0 1
EX-OR gate IC
I I 0
I I 1

EX-NOR gate : F.1 2 3 4 5 - u

Connect a NOT gate at the output of EX-OR gate to convert it to EX-NOR gate. ig. 3.3 : Pin connectio 6 7 GND
6
frUlb table for IC 7486 : ns of IC 74&

A B y
2 0 0
Y=AEBB
0 I
1 0
I 1

5
+SV
s,
Fig. 3.2 : EX-NOR gate using basic gates

Sr.No. Type of gate IC

-- A
I
5 L._.../

1 3 12
6 NOT 7404 r--...... ~
V -
• = ;\ a: .i
--t.___.....,'11
I I 13
Observations : I2
s2
Truth table of EX-NOR gate using basic gates. IO
L---'
8
B
.L
-
A B y
0 0 Fig. 3.4 : EX-OR gate using NAND ga
0 1 Sr. No. 1 to 4 - NANO gates - IC 7400
I 0
EX-NOR gate :
1 1 r, gate using NANO gates
Connect a NAND gate used as NOT gate at the ouipi.t
to convert it to EX-NOR gate.

-,n~~"fltl. ~~.~~~
r: 'il~fl,;_ I
_,,f'J:"~
~~lJ
.i;
r~.
61,M,/ • h - ~
 Std. XII Science ■ Pract1ca1 Elect ,,
88 rori1c. w
p/f ale IC 7486 was tested and lruth lab!
et,OR g . e Was Verified.
Observutlons : 3, • f 4 bit controlled inverter was connected .
Truth table of EX-NOR gate C·rcu1t o
Truth table of EX-OR gate and its worki
using NANO gates 4, given
I 4 bit binary numbers. ng was demonstrated for
u~ing NAND gntcs
y A B y . /,
- A
0
B
0 0 0 1~e0r1 • X-OR (XOR) gate has two or more inputs and one out .
fhe E f 2 NOT gates, 2 AND gates and an OR gat Th put signal. Two input XOR gate
0 I • ts o
0 I
I 0
cons1s _ high output when 1t• has odd number of HIGH
e. e EX OR ·
. • gate 1s a logic circuit
I () wh\ch ha5 \r two input XOR gale. The XOR operatio inputs 0r when its inputs are·noi
I I I sarne l' n IS ca1led as MOD-2 addition.
_._I (he
-.a+ A •-B = A E9 B .
4 bit controlled inverter : A Boolean expression for a XNOR gate is y == Aia .
'{ :;'}'he

+ we 1 I 6 I 31 21
lied Inverter : X
I It contro 4-b· lied . . .
I D, D1 D, 00 4-B By using • 4 XOR gates, it contro inverter can be formed. Register 1s agroup of flip
f b' b'
5 4 4 bit register .
tores a word (group O its or mary number) . In Fig.(3.5), 4-bit register is shown.
Vee
JC 7475
O..K2
a.Kl
l
flops lhat7 75 is used as quad bistable lalch.11 contains lour Dlatches. A4-bit binary number
ffL ICst ed 1•0 it. When the CLK is low, Dis a don't care, Qwill remain latched in last state.
~ 121 G~~ 13
can be o~ • High input data is loaded into the flip-flops and appears at the output. Then when
~en CL iss Lo~, the output. retains the data. For examplej suppose that data input (binary
~ 11~ l'r . 11. • INVERT • ber) 1s D3 D2 D1 D°=0111, whenCLKgoesHigh,Q3 ~ Q,~= 0111.AfterCLK
1
the~ock.goe
13
num Lo this data is store.
goes w,
IC 7486 D
CLK Q n+I
3 6 8 11
0 X Qn (Last state)
Y, y2 Y, yo 0
1 0
Fig. 3.5 : 4 bit co11trollcd INVERTER Circ11il diagram
1 1 1
Note: In fig.3.5 instcnd of using 4-bit register (IC 7475), 4-bit input can be given directly to 4 XOR
gntcs with one common INVERT input.
Truth table of DDip-flop
Obscrvutlons : When INVERT input is Low, it transmits the register word to the output. But when
Input Output INVERT is High, it transmits the l's complement of the register word: For example, if
A, A, A, A,,= A= IO11, then a Low INVERT produces Y, Y, Y, YO=Y=I011. But aHigh
Sr. No. INVERT Ql Q, Qo yj y1 Y, Yo
Q;I
INVERT produces Y = 01()0.
i-

I Low (0) Applicatio~ : ,._

,,
.. Low (0) In solving arithmetic and logic problems.
J lligh ( 1) Model Slips : 'A.
7404 (3)
4 Hi~h ( I) Slip 1. : You are given the following ICs 7408, 7432, •
~
(1)
(a) Identify them
(1)
Cunduslon : (b) Define EX-OR logic.
(5)
I. EX-O1{ gall' wns l:Ons1ruc1cd using the basic gates and its truth table was verified. (c) Write the truth table of EX-OR gate (2 input).
d) D • the basic gates.
2, EX-OR gnto wl\s constructed using NANO gntes und its truth tuble was verified. ( raw the logic diagram of EX-OR gate using
 Std. XII Science ■ Practical Electron~
90

(e) Conn ect the circui t. (5)

. .
(f) Verify the worki ng of the circui d by you as per the tru th table.
t const ructe (3)
(g) Conv ert it to EX-N OR and again test the circui t. (2)
(fl) Test IC 7486. (S)
(i) Orals. • (S)
Slip 2. : You are given the following ICs 7400 and 7486.
(a) Identify them and draw their pin diagr ams show ing the layou t
of gates . (4)
(b) Defin e EX-O R logic. 0)
(c) Draw logjr- diagra m of EX-O R using NAN O gates .
How w:·: you conve rt it to EX-N OR? (5)
(d) Conn ect the circuit. (5)
(e) Verify the output as per the truth table. (5)
(f) Test IC 7486. (5)
(g) Orals. (5)
Slip 3. : You are given the IC 7486
(a) Identify the IC and draw its pin config uratio n.
(5)
(b) Draw the circuit diagra m of a 4-bit contro lled inverter.
(5)
(c) Write the worki ng of 4-bit contro lled inver ter and menti on one
appli cation wher e it can be
used.
(5)
(d) Conn ect the circuit of contro lled inverter.
(5)
(e) Demo nstrat e the worki ng of your circui t for any two 4-bit binar
y numb ers and note down
the input and outpu t numbers. Show them to the exam iner.
• (5)
(t) Orals .

1. Defm e EX-O R logic.

2. What do you mean by MOD -2 addition? How can it be perfo rmed
?
3. ~ow ma~y NAN D gates are neces sary to const ruct EX-N OR
g:1te?
4. What is the use of IC 7475 in contro lled invert er circui t?
5. Expla in the worki ng of contro lled inverter.
6. What is the use of contr olled invert er?

.
(Joo.
 l
__,.,.~~• .nl
pl~u
14
Experiment No. 5 +SV w
Study of R-S Flip - flop Using NANO or NOR Gates

Aim (i) To construct R-S flip-flop using NOR gates and to verify its bu ,
IC 7400
table. th
(ii) To construct R-S flip-flop using NAND gates and to verify its
table. truth
Component list

Type of Component Specifications 1 2 3

4 5 6
IC 7402
7400
Quad 2 - Input NOR gate ITL IC
Quad 2 - Input NAND gate ITL IC
------ (b)
-=--
Fig. 5.1 : (b) Quad. ·2 u,p11t
• NAND
1
Resistors R1 , ~ 330 Q, ± 5 % , 4 W. carbon composition. J.S ftip-OGP using NOR gates : Pin Conn«tion, IGlt IC 1400
LED -2 Colour;vF =............... -

Equipments and Miscellaneous :

5 V de regulated power supply, switches ( SPDT) - 4.
-- (
R
•
IC 7402
2_~ 1 Q

Rl

Pin Connections :
s Q

14 13 12 9 Q
11 10 8 R Q
+5V s 6

(b)
(a)
IC 7402
Fig. 5.1 : (a) Circuit diagram of R-S JUp-jwp using NOR gat,s
(b) Symbol
Obsenations :
Truth • Table
2 3 4 5 6 7 Action
(a) R s Q
No change
0 0 Last state
Fig: 5.1 : (a) Quad • 2 i11put NOR gate IC 7402 1 Set
0 1
Reset
1 0 0
Race
1 1 forbidden
Xb Pr1Ct1caJ Electronics I 7
~..ir~~?f
- ~~ ~~.--;~.
..f;-_ --w,- i~~
-~~~-'
•• + \I.J~,~~~~~~.
 racuca1 ~
98 lec1
t°" ~~II
p# ed to one of the inputs of the other NOR
con~ et the flip
R-S Flip-flop using NAND gates : 00
• fl op. ~~S(~) and RCResct) •
IC7400 t or res mputs allow us to
+5V
se R== O and S = 0, the output remains . th
3 Q When . . in e last state
0) when at least one of its mputs is High {I) Th • The output of a NOR gate is
R 1,0"' ( ' - • etefore when R
te provides a low output Q = o. The inputs ' =0 and S = I, lower
NOR ga . to upper NOR -
0 and O. Therefore, its output Q = I Th th . gate are Q and Rwhich
i,ecome - • us, e flip flop sets.
• 'larly when R= I and S =O, Q:: I and Q=O Th .
Q s11111 ' _ _ ' • us the lltp-fl0p reseis.When R_
't means we want Q - 0 and Q == o at the same u· Th' . -1 and
S ~ I, , . me. " is COnlradict Thertl
s ore.
5 Rl
r dus• sta1·ctable
te is forbidden. Race 1s an undesirable condition It .
•
operation.
ory.
• " never used because it leads to
'JI;, unpred
,. ■
. .flop using NAND gates :
R-S flip
Fig. 5.2: Circuit diagram of R-S flip-flop R-S flip-flop can be constructed by using two cross~uplcd NANO gates, L,. the OUlpUI of
Using NAND gates (Symbol same as in fig.S.J (b)) each NAND gate is connected to one of the inputs of the other NANO gate. S and R inputs
Observations : allow us to set or reset the flip-flop.

The output of a NAND gate is High (1) when at least one of its inputs is Low (0). When
R s Q Action R=oand S = 0, it means we want Q = I/and Q = 1 at the same time, which is contradictory. .
0 0 Because Q and Q are complementary outputs. Hence, this state is forbidden.
forbidden Race
0 I I Set =
When R' = 0 and S 1, as one input to upper NANO gate is low (0), its output Q = 1
I 0 0 Reset (setting). When R = I and S = 0, as one input to lower NANO gate is low, its output Q = 1.
I I Last state Q,being its complementary output, Q =0 (Resetting).
No change

Conclusion :
= =
When R 1 and S 1, the flip-flop remains latched in the last state.
Model Slip :
(i) R-S flip-flop was. constructed by usfog NOR gates and its tru~ table was verified. You are given following ICs (i) 7400, (ii) 7402.
(ii) R-S flip-flop was constructed by using NANO gates and its truth tab.le was veriliol.
{a) Identify them and write their specifications. (2)
(iii) In R-S flip-flop using NOR gates, for the state when R = O and S = 0, the olltpl
remains in the last state while for R-S flip-flop usipg NANO gates, this state is forbi~ {b). Draw circuit diagram of R-S flip-flop using NANO gates and write its truth
den as it causes racing.
table. (5)
(ivl In R-S flip-flop using NOR gates, the state when-R= 1 and S= I is forbidden while ii {c) Construct the circuit and verify the truth table. (5)
Theory: R-S flip-flop using NANo gates the output remains in the last state, for this conilitiol {d) Draw the circuit diagram of R-S flip-flop using NOR gates and write its truth
table. (5)
Aflip-flop is a two state circuit that can remain in either state indefinitely. It is also called 1
bistable nwltivibrator. An external trigger can change the output state. (e) Construct the circuit and verify the truth table. (5)
R-S flip-Dop using NOR gates: . Compare the truth table of RSFF using NANO gates and NOR gates and write •
(f)

R-S flip flop can be constructed

• by using two NOR gates. The output of each NOR g~u the difference. (3)
(5)
(g) Oral.
 Std. XII Science ■ Practical Elect,
100 0~1~

.... ~,'.>:\,, ~~' .' :; : '-'>

~ QUESTIONS FOR ORAL EXAMINATION

i. Define flip-flop. Which type of mul~ivibrator is a flip-flop?

Experirnent No. 6
Study of Multiplexer IC 74153

•
•
(1)
2. Explain the working of R-S flip-flop using NOR gates. • To verify the truth table of logic cireuit for 4to l line multiplexer.
3. Explain the working of R-S flip-flop using NANO gates. • ~itJl
(ii) To verify the truth table of IC 74153.
4. Why action of racing is not used in R-S flip-flop?
5. "ln a R-S flip-flop last state is always O". Comment on this statement. coJIIP"nent Jjst :
'l)'pe of Component
ClClQ I 7404 - l
Specificatiom
Hex Inverter 1TL IC
7421 - 2
Dual -4 - input AND gate TTL IC
~ 7432 - l I Quad 2 - input OR gate TTL IC
74153 - l Dual 4 : I line multiplexer
- I

1.0gic diagram :
I
IC7404
G 1- 2
Strobe
input { So 3 41 So
Control
-
V
Inputs S1 5 6 -s, so
IC 7421

Do I I T I t---:=::l ,----,
IC 7432

D• I I I I I :::j t...:.. L..r-·,.-3 9r---... 8

Data I I
inputs 1 • ~ -A -
02 I I I I I 10

D3

Fig. 6.1 : Logic diagram of 4 to 1 line multiplexer

-~--~-.
' ° ' ~~~ ~·
 Std. XII Science ■ Pracuca1 tie
102

~
Ctro11•
'''ct 4
13 11 10 9 8 11
•(JcJI Dual : 1 multiplexer output sarne as inpu~ loleJn poJe output 103
14 12 p/F jjoOS : Verification of troth table
+. Vee
I 5peP I Input -
Strobe Control
Output
(G,) s.
1 X
0 0
0 0
0 1
GND
1 2 3 4
0 1
5 6 7
. n•
Fig. 6.2: Pin connections of IC 7421 510
conch• •
I. Truth table was ven'fi1ed &,or given
• Iogic
• c1rcu1t
• · of 4
to l line multiplexer.
Truth table of 4: 1 multiplexer
2. Truth table was verified for IC 74153.
Input
Theol'Y :
Strobe Control Output Multiplexer (data seIector) ts
• • • 'th .
a circmt w1 many mputs and only one output. It gates one out
(G) s, so y veral inputs to a single output. The input selected is controlled by aset of select
f
ose (control)
. ts For selecting one out ofn.mputs, a set of mselect mputs .
is required, where 2• = n.
1 X X 0 ~~~er~ly a strobe (enable) input G is applied which helps in cascading and
is generally active-
0 0 0 Do low.
0 0 I D. 4: I multiplexer_ has 4 data input lines and only one output line. For selecting
0 1 0 one out of 4
D2 inputs for connectton to the output 2 select inputs are necessary. Strobe input
0 I I Gis applied as
DJ common input to all AND gates. The data output is equal to the state of
the selected data
IC 74153 pin configuration :
s
output. The output can be expressed as Y = Do S1 0 +0 1 S1 S0 +D2 S1
For the implementation of this equation 4 four -input AND gates and afour-inpu So+ D3 S1 S0•
t OR gate and
two Inverters to generate the complements of control inputs S1and S0 are necessary
Vee G, S0 0 1 D2 D1 D0 applied through an Inverter to all AND gates. When G=0, if select code is 00, . G input is
16 data D0 appears
15 14 13 12 11 10 atthe output. In this way, as shown in the truth table, ifinput conlrOI code is
II, data D, appear,
at the output. As 4:-input OR gate ·1c is not avajlabl_!:, 3 two-in@t OR gates
are ~sed.
IC 74153 can be used as dual 4: I line multiplexer in which output is same as
input.
MUX (1) Model Slip : (5)
(a) Draw the logic diagram of 4: I line multiplexer. (5)
(b) Write its truth table.
Find out the control inputs for different data inputs and verify the ouput as per
MUX (2) (c)
truth table on the given 1,oaid. (5)
You are given JC . 74153 ( or any other equivalent 4 to J line multiplexer IC).
(d) Draw its pin configuration and write the specifications from the data manual-(5)
1 2 3 4 5 6 7 8
G2 S1 D1 D2 D1 D0 Y2 GND Verify the truth table of IC . 74153(or equivalent IC) (5)
(5)
(e)
Fig. 6.3: Pin configurations of IC 74153
(t) Orals.
 6ttt0ri~
104
QUESTIONS FOR ORAL EXAMINATION Experiment No. 7
Study ofDeioultiplner Using IC 74139

1. What is a multiplexer? • (i) To verify the truth table oflogic cin:uit for I 1o
4line demultiplexer.
2. Explain the 1111th table of 4 : I multiplexer using gates. • (ll") To verify the truth table ofIC 74139 .
,4iJII
3. What is the use of strobe input ?
corllp011e11t Ust :
4. What are the specifications of IC 74153? 8ignals?
5. For n input signals, what is the equation for deciding
m control • __
'l)'pe_o_r_c_ornpo_n_e_nt_ _r-_ __ _ __
spedftcatioa,

7404 - 1 Hex Inverter 1TL IC.

JC · AND gate ITL IC.
T. Ie 3 - input
7411 - 2 np
CltlQ 74139 Dual 1: 4linedemultiplexer(decoder).

Logic diagram :
Data input IC7411

Do

D, l Data
output
so lines
7404
Control D1
Inputs
s,
IC7404 o,

Fig. 7.1 : Logic diagram of 1 : 4 d,,nultiplutr

14 13 12 11 m 9 8
+Vrx - .....

l Ol ..I I 111:::iyi'11 0~oND

11

1 2 3 4 5 6 7
Fig. 7.2 : Pin conntctions of IC 7411
 •W'• • I'
Std. XII Science • Pract;~ ~I !
.. r
106 1
'ctr°'i~ p,APff1II
Truth table ror logic circuit :
Input
I
Output c1usion : . . . 107
co" "'-"''th
11 table for given logic circuit of to .
t. u 1 41
Data s. s, Q= I _Truth table was verified for IC 741
inc dcrnutti 1
2 39_ Pcxcr was Verified.
0 X X ---
1 0 0~ Do 111CC'rY : ultiplexer is a logic circuit with one input a""
1
pem
l mcontrol sign
• als d uu rnany outputs 'T'L.. •
1 0 DI ' an noutput signals. The nurnbc . 'u1s CUtuit has one i.,t
igna ' cod d t • .
1 1 0 D2 s '" The select e e enruncs to Which output the dr of.control or scIect lines ism,
. where
P,. 2 • • . ata 1npu1 will be lransmiltcd.
1 1 D3 e demult1plexe_rs can be designed using gates or dcmut .
~
1 .
1CTFhor 1• •• 4 demultiplexer, as n = 4, m:: 2. 'T'L.
\

uic
data . t1_P_
input me lcxcrs arc avadable an MSI
Pin configuration of IC 74139 : 1
• t linCS enable only one gate at a time, and the data 'fJr!Qringoes 10 •U AND gat,s. Two
selec h the selected gate to the COrtcsponding output line ~ : the mput_hn, wiU pus
FE s, so Do D, D2 D) ~ug
connected 10 logic J level.. • a mput Im~ should bt
16 15 14 13 12 11 10 9
+Vee But for Ic 7~139, the FE mput should be Low. Two select i11plll lines enable ooly OGe oucpui .
•• e to be in logically Low (0) state. For ~xample, when FE input is Low. s =o. S =I. onl
:q,ut line is Low (0) and other outputlmcs arc High (I). 0 Y0 ,
1
DEMUX-1
vu: . .
Demultiplexer can be used as bmary-to-dccunal decoder with binary inputs applied at the
elect input lines and then the output will be obtained on the corresponding line. Demultiplexer
DEMUX-2 :c is very useful if multiple QUlput combinationalcircuit is to be designed. This need, minimum
package count.
Model Slip :
GND (a)
3 4 5 6 7 8 Draw the logic ~agram of 1to 4line demultiplexer.
(5)
S1 S0 D0 D1 D2 D (b) Write its truth table.
1
(5)
Specifications : Fig. 7.3: Pin configuration of IC 74139 (c) Find out the control inputs for the input data (High or Low) and verify the
output as per truth table on the given board. (5)
Dual I : 4 line demultiplexer (2 x 2 bit binary decoders) (d) You are given IC-74139(oranyequivalent 1to4lincdcmultiplcxer IC). Draw
2 - line to 4 - line decoder, Inverted input.
its pin configuration and write the specificatioos from data manual. (5)
Totem pole output.
(e) Verify the truth table oflC-74139 (or equivalent IC) .
Truth table for IC 74139 : (5)
(f) Orals . (5)

FE
Input

s. s.
Output • 1.
Q=O What is a demultiplexer?
I X 2.
X Explain the truth table of 1 : 4 demultiplexer using gato:S.
0 0 0
--- 3.
0 Do State the uses of demultiplexers.
0 l 4.
0 D, What are the specifications of IC 74139?
I 0
0 5. Explain the truth table of 1: 4demultiplexer using IC 741 39,
I I D2
..
D1
□□□
 1(»
7 0 1 1 1 -
Experiment No. 8 8 1 0 0 0
Study of Encoder Using IC 74147 9 1 0 0 1

-
.) 'Iioven.fy the tIUth table of decimal to BCD encoder for g·1ven I0 •
(1
Aim circllit 81c
(ii) To verify the tn1th table of IC 74147.

Component list :
specifications
Type of Component
Ii
Quad 2-input OR gate TTL IC.
IC 7432 - 3 13
Decimal to BCD encoder. A
IC 74147 - 1 2

Logic Diagram :
A (LSB) B

3 B 4 ---+"""'-..:.>.
s-___."'"'-,L_J
C
4 6 - -......~
5 C
6 1---'"-~
7. s
8 s-·--~~
9 _ _ _.......,
11
> - - - - - - D (MSB)
9
D (MSB)

Fig. 8.1 : Logic diagram ,t d imal Fig. 8.2 : Logic cirtuil of decimal to BCD encoder ,ui,,g IC 1432
Truth table of decimal to BCD OJ ec to BCD encoder
.
encoder using gates (Fig. 8 I or Fig. 8.2)
Decimal BCD Code
la, lb, le, ld, - IC I}
D C B A 2a, 2b, 2c, 2d,- IC 2 IC 7432-3 No. s
0 0 0 0 0 3a, 3b, 3c, 3d, - IC 3
I 0 0 0 1
2 0 0 As OR gate ICs with 4 or 5 input tenrunals are not available, Quad 2-input OR gate IC 7432
1 0
3 0 0 are used.
1
1 •
4 0 1 0 0
5 0 1 0 1
6 0 I 1 0
ll'nntrl nn N,-wr Pucl
 nce ■ Pra .
ct1ca1 E1
.ectro ~~II
110 ~,~ p# '
•ofl •
. 111
Pin configuration of IC 74147 : ,.. pcl~• b trt1th table of decimal to BCD eneoc1
v11 . 'f e . • erforgiven •.
NC D x) X2 x. x9 A 1 .......e trUth table was venfied for IC 7415'1. logic circuit was
15
13 12 11 10 9 z.1~ ~ v~d
•

Vo:. 'fbeOJ')' : ncoder converts an active input sign •

p..n e . a1mto a COded •
oeter bas 10 mputs - one ior each decimal digit
en~ 'fhis is Io line to 4 line encoder. In the deem:dtour outputs input signaJ. 0cc·
CO!Tespondi unal-10-BCD
.~e-(1) occurs on one of the decimal digit input r to BCD encode
)lijb If f l •
CD output fines. or examp e, tnput line 8 is only mes, the appr • r using ORng to the BCD
gates, when a
Hi h • ~•te levels occur on the four
BI and 1.,ows on outputs B, C and A which is BCD ~ ,1 will produc
e a High on ouipu1 D
011 Yd d because the BCD outputs are all Low whe •- (IOOO
,zee e . . )for 8. A
n t,1est are no Hi8h Odigit input is
I
• not
1be function of this encoder can be performed by IC
741 47 11
q,uts- According to the truth table, when all inputs are High • has
, . lllplll~
2 3 4 5 6 7 8 acl!ve Low' inputs and
0~ LOW tbeDCBAoutputis0110(equivalentto9ify
x, X X6 x x, c B o No IS . ' . al . . o
u
,alll outputs areHigh. Whcoinput
9active-low dec1m mput 1s converted to a complementedcomp ement the bits 1001) Th
5 1

Fig. 8.3: Pin configurations of IC 74147 BCD output. • us. an

IC 74147 is a priority enco~er because it gives priority to th
b'ghcs . •
Specifications :
Decimal to BCD encoder (priority encoder)
eX8ff1Ple, if inputs 4 and 8 are Low, the BCD output will be
complement of 1000) due to active Low operation Thus the h'
~~ mput. For
( · ·11 I • ht •g to i.e. Olli
To tern pole output, Active low inputs and outputs. the priority and it wi contro the encoding. Use • In key• boards. zg st active-Low inpul has

Truth table of IC 74147 Model Slip :

(a) Draw the logic diagram of decimal to BCD encoder. (5)
Active low decimal inputs Active low BCD outputs- (b) Write its truth table. (5)

- (c) Find out the control inputs for different decimal inputs and verify
1 2 3 4 s 6 7 8 9 D C B A the output as per truth table on the given board.
(5)
You are given IC 74147 (or any equivalent) decimal to BCD encoder.
I 1 I I I I
(d) Draw
1 I I l l I I its pin configuration and write the specifications.
(5)
0 1 I I I I l Verify the truth table of given IC.
I l l I l 0 (e) (5)
X 0 (5)
I I I I 1 1 l (t) Orals.
l 1 0 I
X X 0 l 1 1 1 1 1 I I 0 0
X X X 0 I I 1 1 1 I 0 1 l
X X X X 0 1 I l 1. What do you mean by an encoder?
I I 0 I 0
X X X X 2. Explain decimal-to-BCD encoder using OR gates.
X 0 1 1 1
• tbc hcp
. . encoderusingIC74147w1tb
I 1 0 0 I
X X X 3. Explain the working of decimal-to-BCD pnonty
X X X 0 I I I of a truth table.
X X 0 0 0
X X X 4. Why IC74147 is called 'priority encoder'?
X X 0 1
X 0 1 I 1
X X X 5. What is the use of an encoder? □□□
X X X X 0 0 I 1 0
 113
f g a b C

•••ent No. 9
Experi...
oder Using IC 7447/7448
Study of Dec....
IC7447
FND 5fr7
. ·t of decoder using IC 7447n448.
. ssemble the c1rcu1 .
Aim (1) To a . tion of the circmt. 3 4 5 6 7
(ii) To stu~Y the opera

B L.T. A gnd c.a. d.p.

Component list C
RBO
Specifications ---- Fig. 9.2: Pin connections of IC 7447
Type of Component Fig. 9J: Pin connections of FND
1 --
330 Q , ± 5% , 4 W carbon c~mposition. 507 display
Resistors - 9 No.s
14 pin, BCD to 7 - segment decoder IC. ~u~= . .
IC 7447 proc h k the resistors with the help of a multimeter. Assemble the circuit as shown in the
507 Common an~e display. • • era:. Connect ~e ~wer su~ply. Test the display by connecting pin 3 of the IC 7447 to
FND
diag d momentarily. Give BCD mputs to IC 7447 from the outputs of a decade counter or by
usmg sw1·tches• Observe the seven-segment display and write the observation table.
~un ,
Equipments and miscellaneous : _ Observation Table
\

5 V de power suppIY, swt'tches (SPDT type ) - 4' press to on switches- 2 .

BCD input Segment positions Display
Circuit diagram : + 5 V de

3 D C B A a b C d e f g
16 <_ _ _ __ nu
a > 0 0 ·o 0 1 1 1 1 1 1 0
D f
6 15
0 0 0 1 I
·g
14 f b I
C
2 a 0 0 1 0
13 FND
IC
b
g 507
B 7447 12 < > 0 0 1 1
1 di.splar
11 C
0 1 0 0
A 10 d
C C
7 0 1 0 1
f
e
9 d
3 8 :) 0 1 1 0
<
s 0 1 1 1
1 0 0 0
l O O 1

-
Fig. 9.1 : Ci;;uit diagram
Note :
• h
The inputs from IO 10 to 1111 s ou
.
Id not be given,
as these are forbidden BCD inputs.

XU practlcal Electronics / 8
 Pracu '\!f'>'
ca, El i• ti~
114 ectr011• ~~
'''Ci
p~"
Conclusion : .
. 7 .segment decoder/ dnver. ~oefel SliJJ : 115
IC 7447 can be used as BCD to (a)
You are given IC_744? / 7448 and 7- ~ t LED display. Identify the IC
and write its specifications. (5J
Theory : fd' · (b)
. . d t display numerical output o 1g1tal instrument .
Seven•seg~~t display is :cu~tors etc. The output is displayed in decimal nu~~ke digi~
Draw the circuit di&grarn for the testing ofabove JC. (~
(c) Connect it to obtain different digits for cliff~ BCD Ulputs_
multimete_rs, digital watches, BCD to ?•segment code. The decoder/driver circuit h rsyste~ (5)
:°e data ts converted:;m tput lines to drive a ?•segment display. If the outputs as 4 inpu; (d) Test the circuit for different in~Jtcaiditions.
Imes!or !C~_da;a :ust: of common•anode type. ICs 7446 and 7447 have active:e active. (e) Tabulate the observations. (5)
low, en e tsp ay ~ mmon-anode display FND 507 or MAN 72 is used ICow, olleii Oral.
collector output. There1ore, co . l FND 500 • • 74.tg· (f) (5)
active-high output. Therefore, common•cathode d1sp ay . is used. The 744g h ~
. .. ·stors on the chip Therefore, external resistors are not req . as 1~ (5)
own current 11m1tmg ~t • Utred.
2 111••u::::::c.:....a
LED display :
When a diode is forward•biased, free electrons combine with holes_ and radiate energy WhY common-~ode display is used with IC 7447?
they go from a higher energy level to a lower en~rgy level. In LED this energy is in fonn ii 1.
light The colour of light depends upon the matenal used. The compounds of gallium ~ 2. What is the function of IC 7447?
• · ye.11ow, bl ue, orange or mfrare~
• •--
and phosphorous are used to produce ~ed, green, (invisible 3. Explain LED display?
light. Advantages of LEDs are long hfe (more than 20 years), low voltage and fast on-o~
switching (in nanoseconds). 4. What are the functions of pins 3,4, and 5inIC7447?
In common-anode type seven-segment display all anodes are connected together and in 5. If IC7448 is usedinsteadofIC7447, whichchangesarcnecessaryinthecircuit?
common-cathode type all cathodes are connected together.
Working:
□□□
IC 7447 is a BCD to seven-segment decoder/driver. When a BCD input is given it provides
suitable grounds for seven-segment indicator. Therefore, LED display should be of common.
anode type like FND 507 or MAN 72. For example if BCD input is DCBA = 0111, output lines
for a,b,c are gounded which activates segments for number 7. Therefore, IC 7447 is active low
decoder driver.
The BCD input is obtained from the supply or ground by using the switches. The resistoo
are used in series with each segment to limit the current in each segment to a safe value
between 1 and 50 µ A depending on how bright you want the display to be.The functions of
different pins are described below :
Lamp test terminal (pin 3) is used to check the segments of LED. If it is grounded
(logic 0) all segments of display will be on.
Blanking input I Reverse blanking output (pin 4) : If this is connected to ground, the
disp!ay is switched off irrespective of BCD inputs RBO (pin 4) is used for cascading purposes
and ts connected to RBI (pin 5) of the next stage.
Re~erse blanking input (pin 5) : If it is grounded normal decoding is observed. for ~I
BC~ mputs except zero. For zero input, the display switches off. This is used for blanking oil!
leading zeros in multi-digit displays. _..

,..
~- ' • ..__,,.' I,\
' .
'lt~~·\ ,·
 ,~11-
.-011 : 121
Experiment No. 11
Copel J!alf· adder was constructed using logi
Construction of Half. adder ~ used for addition of 2 bits. c gates and its truth table .
can ""' Was venfied. Half-adder

Aim To construet hal f-adder using logic gates and to test the circu·t1 . 1'fleOrY ~alf-adder is a logic circuit that adds 2 bin d..
n AND t Th ary igits at a ti I
OR gate and an ga e. e output of XOR gate is the s~· t consists of an exclusive.
CARRY, Mand output of AND gate is
Component list :
Specifications ,roof:
Type or Component
= =
1• Let A= Oand B 0. Carry A.8 = 0.0 =o• Sum-_ 0 eo=0
IC 7408 Quad 2- input AND gate TrL IC = =
2. Let A 0 and B 1. Carry = 0 . I = 0.• Sum =0 e I = I.
7486 Quad 2 - input EX-OR gate 1iL IC
·1 3_Let A = 1 and B = 0. Carry = 1.0 = O. Sum = I e O= 1.
Resistor R1, ~ 330 n t 5% , 4 W •·carbon composition, = =
4. Let A 1 and B 1. Carry = I. I= I. Sum = 1 e l =o.
LED-2 ................ colour
Model Slip :
_(a) Draw the logic diagram of half-adder using logic gates.
Equipments and miscellaneous : (5)
(b) List the number of ICs required, write their specifications and
5 V de regulated powe~ supply, switches (SPOT) - 4. pin configurations. (5)
Diagram: Construct the circuit on the given board.
(c) (5)
+5V IC 7408 (d) Test the circuit for all ~sible input combinations. (5)
---=A I Tabulate the results. (5)
------, (e)
B Carry= A·B (5)
s 2 3 (f) Oral.
R,

I ~
3 - -
Sum= A EBB = A •B+ A •B
l'lilliilifflllili1;111~1it&"iiiiM

2 ~ 1. Define half-adder. Which gates are necessary ior construction of a half-adder?

IC 7486 ~ 2. Define AND gate. Define XOR gate.
- 3. State the logic equations for carry and sum in a half-adder.
Fig. 11.1 : Logic diagram of half-adder using logic gales
ICs required are given in the component list. For pin configurations of IC 7408 refer 10 4. What do you mean by mod- 2 addition?
Fig.( 1.1-b) and for pin configurations of IC 7486 refer to Fig. (3.3). 5. What is the use of half-adder?
Observations :
Truth Table □□□
A B Carry Sum
0 0
0 I
I 0
1 I
 123
Experiment No. 12
~

0 1 I
-
• Logic Gates 1 0 0
Full adder using
1 0 I
I I 0
To construct full adder using gates and to test the circuit. I
Aim I 1

Logic diagram : cl~ion :

- . .
-
+5V coo J'Ull•adder was co~~cted usmg logic gates and its truth table was Verified. Full-adder can
IC7408 IC7432 for binary addition of 3 bits.
t,eUsed
A 3 3
B Carry= (A· B)+ (A EB B)·C '}'beorY : • • • th dd 3 b'
R, ll adder is a logic crrcmt at can a its at a time. There are two outputs: SUM and
~Y. '!be full-adder consists of 2 AND gates, I OR gate and 2 XOR gates. Output of OR
~
• CARRY andoutputofXORgate is SUM. Logic equations: CARRY= (A.B)+(A@B).C
gate IS
SUM =A EB B EB C •
The third bit C in the input is ~e carry from a lower .co~umn. ~e CARRY output is h!gh,
IC7486 jhen two or more input bits are high. When odd number of mput bits to the XOR gate are high,
the SUM output is high.
Sum= AEBBEBC For example , Let A= 0, B =1 and C = 1
Carry= (o.1)+(oan).1 =o·+ 1.1 =1
SUM= A EBB EB.C =0EB lEBl =0.
Fig. 12.1 : Logic diagram of full adder using gates Model Slip :
k's required (a) Draw the logic diagram of full-adder using gates. . (5)
(b) List the required ICs with their specifications and pin configurations. (5)
I. IC 7408 - Quad - 2 - input AND gate TTL IC I
(5)
2. IC 7432 - Quad - 2 - input OR gate TTL IC (c) Construct the circuit on given board.
(5)
3. IC 7486 - Quad - 2 - input XOR gate TTL IC (d) Test the circuit for all possible input combinations.
(5)
For pin configurations of IC 7432 and 7408 refer to Fig. ( 1.1 - a) and ( 1.1 - b) respectively (e) Tabulate the results.
(5)
for pin configurations of IC 7486 refer to Fig (3.3). (t) Oral.
Observations :
Truth Table • of a full-adder?
for constrUcnon
1. Define full-adder. Which gates are necessaIY
A B C Carry Sum 2. Define AND gate, XOR gate and OR gate.UM in a full adder.
0 0 0
0 3. State the logic equations for CARRY andS
0 I 4
0 1 0 • What is the use of full aMer·? d high sum output can ~~~- • d?
.
5. For which conditions a high carry output an a □□□