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Columbia University
Department of Electrical Engineering

EE E4321. Problem Set #1. MOS Device Physics Review.
Due: Thursday, September 19, 2024, 5 PM EDT by electronic submission (see
below)
Please carefully follow these instructions. All problem sets should be submit-ted
electronically as a single PDF file attachment through Courseworks. If you do
your calculations with pencil and paper, please scan your work to submit it
electronically.
1. Basic first-order models. Consider a pMOS transistor with the following pro-
cess parameters:
tox = 9.6 nm
μp = 232cm2/V − sec
Esat = 4 × 104V /cm
VT = −1V
The device is operating at T = 300 K (kT /q = 26mV ).
The following equations are valid for velocity-saturated devices:

2
W μCox [(VSG − |VT |)VSD − 0.5VSD ]
ISD,triode = (1)
L 1 + VSD /(Esat L)
2(VSG − |VT |)
VSD,sat = (2)
1 + 2(VSG − |VT |)/(Esat L) + 1
(a) Consider one of these pMOS transistors with Ldrawn = 0.6μm and Wdrawn =
10μm. Assume that the effective and drawn dimensions are identical (ΔW = 0
and ΔL = 0). Considering velocity saturation (using the equations above), plot
ID as a function of VSD between 0 and 5.0 V for VSG = 0, 0.5, 1.0, 1.5, 2.5, 3.0,
3.5, 4.0, 4.5, 5.0 V. Assume V SB = 0. What effect (qualitatively) does velocity
1
saturation have on the current drive of the FET compared to a case in which the
carrier drift velocity does not saturate?
(b) Assume that STI (shallow trench isolation) is used so that sidewall capacitance
can be largely ignored for the source-drain diffusions. Assume that the source-
substrate and drain-substrate areal capacitances are defined by an abrupt junction
between a source-drain doping of NA = 1 × 1018 cm−3 and a substrate doping
of ND = 8 × 1016 cm−3 . Consider two pMOS transistors in series as shown in
the schematic below. The capacitance of node C is dominated by the diffusion
capacitance of the source-drain region. If the diffusion area of node C is 30 μm2 ,
what are the largest and smallest possible values of this diffusion capacitance (over
the possible reverse biases on this node with respect to the nwell)?
+5V
I
C D
2. Charging/discharging cut-off issues. Consider the following circuits for dis-

charging a capacitor, initially charged to 5 V. Assume that all the transistors are
enhancement mode with a threshold voltage of magnitude 1 V. Find the final val-
ues of the capacitor voltage (i. e., after a reasonable amount of time) and the
regions of operation the transistors pass through during the discharge transient.
2
+2 V
(b) (c)
(a)
+3 V
(d)
+5 V
3. Subthreshold leakage. If a current of 100μA through an nFET defines the V T

at 0.5 V, what is the subthreshold current at V GS = 0 at 25o C? Please assume an
“ideal” subthreshold slope of 60mV /decade.
3
4. Interpreting IV curves. Consider the three FET IV characteristics shown below.
Figure 1: ID versus VDS for a nFET with W = 1μm and L = 0.25μm. VGS varies
from 0.5 to 2.5 V on steps of 0.5 V.
4
Figure 2: ID versus VSD for a pFET with W = 1μm and L = 0.25μm. VSG varies
from 1.0 to 2.5 V on steps of 0.5 V.
Figure 3: ID versus VDS for a nFET with L = 0.25μm and W unspecified. VGS
varies from 0.5 to 2.5 V on steps of 0.5 V.
5
(a) Is the nFET of Figure 1 velocity saturated? Explain. How about the pFET of
Figure 2? If the devices are velocity saturated, estimate the saturation velocity for
electrons? for holes? (use tox = 5.8nm, ox = 3.45 × 10−13 F/cm to compute
Cox ).
(b) What is the width of the nFET of Figure 3?
5. Generalized scaling. In class, we discussed constant-field scaling. Instead as-

sume that the electric field changes by a factor of α while the physical dimensions
continue to scale by κ. Complete the following table:
Device dimensions (tox , L, W , xj ) 1/κ

Doping concentrations (NA , ND ) ακ
Voltage (V ) α/κ
Electric field (E) α
Depletion region width (Wd )
Capacitance (C = A/t)
Inversion-layer charge density
Long-channel Velocity-saturated
Carrier velocity (vdrif t )
Current (I)
Circuit delay time (τ ∼ CV /I)
Power dissipation (P ∼ V I)
Power-delay product (P τ )
Circuit density (∼ 1/A)
Power density (P/A)

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Columbia University

Department of Electrical Engineering

The following equations are valid for velocity-saturated devices:

2. Charging/discharging cut-off issues. Consider the following circuits for dis-

3. Subthreshold leakage. If a current of 100μA through an nFET defines the V T

(b) What is the width of the nFET of Figure 3?

5. Generalized scaling. In class, we discussed constant-field scaling. Instead as-

Device dimensions (tox , L, W , xj ) 1/κ

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