RT8024

1.5MHz, 400mA, High Efficiency PWM Step-Down

DC/DC Converter
General Description Features
The RT8024 is a high-efficiency pulse-width-modulated z 2.5V to 5.5V Input Range
(PWM) step-down DC/DC converter. Capable of delivering z Adjustable Output From 0.6V to VIN
400mA output current over a wide input voltage range from z 1.0V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V Fixed/
2.5V to 5.5V, the RT8024 is ideally suited for portable Adjustable Output Voltage
electronic devices that are powered from 1-cell Li-ion z 400mA Output Current, 1A Peak Current
battery or from other power sources within the range such z 95% Efficiency
as cellular phones, PDAs and handy-terminals. z No Schottky Diode Required
z 1.5MHz Fixed Frequency PWM Operation
Internal synchronous rectifier with low RDS(ON) dramatically
z Small SOT-23-5 and TSOT-23-5 Package
reduces conduction loss at PWM mode. No external
z RoHS Compliant and Halogen Free
Schottky diode is required in practical application. The
RT8024 automatically turns off the synchronous rectifier Applications
while the inductor current is low and enters discontinuous
z Cellular Telephones
PWM mode. This can increase efficiency at light load
z Personal Information Appliances
condition.
z Wireless and DSL Modems
The RT8024 enters Low-Dropout mode when normal PWM z MP3 Players
cannot provide regulated output voltage by continuously z Portable Instruments
turning on the upper P-MOSFET. RT8024 enter shutdown
mode and consumes less than 0.1μA when EN pin is pulled Ordering Information
low. RT8024(- )
Package Type
The switching ripple is easily smoothed-out by small
B : SOT-23-5
package filtering elements due to a fixed operation J5 : TSOT-23-5
frequency of 1.5MHz. This along with small SOT-23-5 and
Lead Plating System
TSOT-23-5 package provides small PCB area application. G : Green (Halogen Free and Pb Free)
Other features include soft start, lower internal reference
Output Voltage
voltage with 2% accuracy, over temperature protection, Default : Adjustable
and over current protection. 10 : 1.0V
12 : 1.2V
Pin Configurations 15 : 1.5V
18 : 1.8V
(TOP VIEW) 25 : 2.5V
FB/VOUT VIN 33 : 3.3V
Note :
5 4
Richtek products are :
2 3 ` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
EN GND LX
` Suitable for use in SnPb or Pb-free soldering processes.
SOT-23-5/TSOT-23-5
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.

DS8024-02 March 2011 www.richtek.com

1
RT8024
Typical Application Circuit
L
2.2µH
VIN 4 3 VOUT
VIN LX
2.2V to 5.5V CIN
4.7µF RT8024
COUT
1 5
EN VOUT 10µF
GND
2

Figure 1. Fixed Voltage Regulator

L
2.2µH
VIN 4 3 VOUT
VIN LX
2.2V to 5.5V CIN
C1
4.7µF RT8024 R1
1 5 COUT
EN FB
10µF
GND IR2
R2
⎛ R1 ⎞ 2
V OUT = V REF x ⎜ 1 + ⎟
⎝ R2 ⎠
with R2 = 300kΩ to 60kΩ so the IR2 = 2μA to 10μA,
and (R1 x C1) should be in the range between 3x10-6 and 6x10-6 for component selection.

Figure 2. Adjustable Voltage Regulator

Layout Guide
VIN GND VOUT VIN GND VOUT
CIN COUT CIN COUT

L L
VIN 4 3 LX VIN 4 3 LX

2 GND 2 GND
C1
VOUT 5 1 EN FB 5 1 EN

R1 R2
GND VOUT GND

Figure 3
Layout note:
1. The distance that CIN connects to VIN is as close as possible (Under 2mm).
2. COUT should be placed near RT8024.

www.richtek.com DS8024-02 March 2011

2
 RT8024
Functional Pin Description
Pin No. Pin Name Pin Function
1 EN Chip Enable (Active High, do not leave EN pin floating, and VEN < VIN + 0.6V).
2 GND Ground.
3 LX Pin for Switching.
4 VIN Power Input.
5 FB/VOUT Feedback Input Pin.

Function Block Diagram

EN VIN

RS1
OSC &
Current
Shutdown
Limit
Control
Detector
Slope
Compensation
Current
Sense

Control Driver LX
Logic
PWM
FB/VOUT Error Comparator
Amplifier
RC
Zero
COMP UVLO & Detector RS2
Power Good
Detector VREF

GND

DS8024-02 March 2011 www.richtek.com

3
RT8024
Absolute Maximum Ratings (Note 1)
Supply Input Voltage ------------------------------------------------------------------------------------------------------ 6.5V
Enable, FB Voltage ------------------------------------------------------------------------------------------------------- VIN + 0.6V
Power Dissipation, PD @ TA = 25°C
SOT-23-5, TSOT-23-5 ----------------------------------------------------------------------------------------------------- 0.4W
Package Thermal Resistance (Note 2)
SOT-23-5, TSOT-23-5, θJA ----------------------------------------------------------------------------------------------- 250°C/W
SOT-23-5, TSOT-23-5, θJC ----------------------------------------------------------------------------------------------- 130°C/W
Junction Temperature Range -------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------------ 200V

Recommended Operating Conditions (Note 4)

Supply Input Voltage ------------------------------------------------------------------------------------------------------ 2.5V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics
(VIN = 3.6V, VOUT = 2.5V, VREF = 0.6V, L = 2.2μH, CIN = 4.7μF, COUT = 10μF, TA = 25°C, IMAX = 400mA unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Voltage Range VIN 2.5 -- 5.5 V
Quiescent Current IQ IOUT = 0mA, VFB = VREF + 5% -- 50 100 μA
Shutdown Current I SHDN EN = GND -- 0.1 1 μA
Reference Voltage VREF For adjustable output voltage 0.588 0.6 0.612 V
Adjustable Output Range VOUT VREF -- VIN − 0.2 V
VIN = 2.2 to 5.5V, VOUT = 1.0V
ΔVOUT −3 -- 3 %
0A < IOUT < 400mA
VIN = 2.2 to 5.5V, VOUT = 1.2V
ΔVOUT −3 -- 3 %
0A < IOUT < 400mA
VIN = 2.2 to 5.5V, VOUT = 1.5V
ΔVOUT −3 -- 3 %
0A < IOUT < 400mA
Fix
VIN = 2.2 to 5.5V, VOUT = 1.8V
ΔVOUT −3 -- 3 %
Output Voltage 0A < IOUT < 400mA
Accuracy VIN = 2.8 to 5.5V, VOUT = 2.5V
ΔVOUT −3 -- 3 %
0A < IOUT < 400mA
VIN = 3.5 to 5.5V, VOUT = 3.3V
ΔVOUT −3 -- 3 %
0A < IOUT < 400mA
VIN = VOUT + 0.2V to 5.5V, VIN ≧ 3.5V
−3 -- 3 %
0A < IOUT < 400mA
Adjustable ΔVOUT
VIN = VOUT + 0.4V to 5.5V, VIN ≧ 2.2V
−3 -- 3 %
0A < IOUT < 400mA
To be continued
www.richtek.com DS8024-02 March 2011
4
 RT8024
Parameter Symbol Test Conditions Min Typ Max Unit
FB Input Current IFB VFB = VIN −50 -- 50 nA
VIN = 3.6V -- 0.3 --
PMOSFET RON PRDS(ON) I OUT = 200mA Ω
VIN = 2.5V -- 0.4 --
VIN = 3.6V -- 0.25 --
NMOSFET RON NRDS(ON) I OUT = 200mA Ω
VIN = 2.5V -- 0.35 --
P-Channel Current Limit IP(LM) VIN = 2.5V to 5.5 V 1 -- 1.8 A
EN High-Level Input Voltage VENH VIN = 2.5V to 5.5V 1.5 -- -- V
EN Low-Level Input Voltage VENL VIN = 2.5V to 5.5V -- -- 0.4 V
Undervoltage Lock Out threshold -- 1.8 -- V
Hysteresis -- 0.1 -- V
Oscillator Frequency fOSC VIN = 3.6V, I OUT = 100mA 1.2 1.5 1.8 MHz
Thermal Shutdown Temperature TSD -- 160 -- °C
Min. On Time -- 50 -- ns
Max. Duty Cycle 100 -- -- %
LX Leakage Current VIN = 3.6V, VLX = 0V or VLX = 3.6V −1 -- 1 μA

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard. Pin 2 of SOT-23-5/TSOT-23-5 packages is the case position for θJC
measurement.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

DS8024-02 March 2011 www.richtek.com

5
RT8024
Typical Operating Characteristics
Efficiency vs. Load Current Reference Voltage vs. Input Voltage
100 0.6010

VIN = 3.3V
90

Reference Voltage (V)

0.6005
80
Efficiency (%)

VIN = 5V
70 0.6000

60
0.5995
50

VOUT = 1.2V VOUT = 1.2V

40 0.5990
0.01 0.11 0.21 0.31 0.41 0.51 0.61 2.5 3 3.5 4 4.5 5 5.5
Load Current (A) Input Voltage (V)

Output Voltage vs. Load Current Current Limit vs. Input Voltage
1.220 2.5

1.215
2.0
1.210
Output Voltage (V)

VIN = 3.3V
Current Limit (A)

1.205 VIN = 5V 1.5

1.200
VIN = 2.5V 1.0
1.195

1.190
0.5
1.185
VOUT = 1.2V VOUT = 1.2V
1.180 0.0
0.01 0.11 0.21 0.31 0.41 0.51 0.61 2.5 3 3.5 4 4.5 5 5.5
Load Current (A) Input Voltage (V)

Frequency vs. Input Voltage Frequency vs. Temperature

1.50 1.50
VOUT = 1.2V, IOUT = 300mA
1.48
1.48
1.45
Frequency (MHz)
Frequency (MHz)

1.45
1.43

1.43 1.40

1.38
1.40
1.35
1.38
1.33
VOUT = 1.2V, IOUT = 300mA
1.35 1.30
2.5 3 3.5 4 4.5 5 5.5 -50 -25 0 25 50 75 100 125
Input Voltage (V) Temperature (°C)

www.richtek.com DS8024-02 March 2011

6
 RT8024

Output Voltage vs. Temperature Output Ripple

1.25
VIN = 3.3V, VOUT = 1.2V, IOUT = 400mA

1.23 VLX
(5V/Div)
Output Voltage (V)

1.21
VOUT
(5mV/Div)
1.19

1.17
ILX
(500mA/Div)
VIN = 3.3V, IOUT = 0A
1.15
-50 -25 0 25 50 75 100 125 Time (500ns/Div)
Temperature (°C)

Load Transient Response Load Transient Response

VIN = 3.3V, VOUT = 1.2V, IOUT = 100mA to 400mA VIN = 3.3V, VOUT = 1.2V, IOUT = 200mA to 400mA

VOUT VOUT
(20mV/Div) (20mV/Div)

IOUT IOUT
(200mA/Div) (200mA/Div)

Time (50μs/Div) Time (50μs/Div)

Power On Power Off

VIN = 3.3V, VOUT = 1.2V, IOUT = 400mA VIN = 3.3V, VOUT = 1.2V, IOUT = 400mA

VEN VEN
(5V/Div) (5V/Div)

VOUT VOUT
(1V/Div) (1V/Div)

I IN
(200mA/Div)
I IN
(200mA/Div)

Time (100μs/Div) Time (100μs/Div)

DS8024-02 March 2011 www.richtek.com

7
RT8024
Applications Information
current is exceeded. This results in an abrupt increase in
The basic RT8024 application circuit is shown in Typical
inductor ripple current and consequent output voltage ripple.
Application Circuit. External component selection is
Do not allow the core to saturate!
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency Different core materials and shapes will change the size/
followed by CIN and COUT. current and price/current relationship of an inductor.
Toroid or shielded pot cores in ferrite or permalloy materials
Inductor Selection
are small and don’ t radiate energy but generally cost
For a given input and output voltage, the inductor value
more than powdered iron core inductors with similar
and operating frequency determine the ripple current. The
characteristics. The choice of which style inductor to use
ripple current ΔIL increases with higher VIN and decreases
mainly depends on the price vs size requirements and
with higher inductance.
any radiated field/EMI requirements.
⎡V ⎤⎡ V ⎤
ΔIL = ⎢ OUT ⎥ ⎢1 − OUT ⎥
⎣ f × L ⎦⎣ VIN ⎦ CIN and COUT Selection
The input capacitance, C IN, is needed to filter the
Having a lower ripple current reduces the ESR losses in
trapezoidal current at the source of the top MOSFET. To
the output capacitors and the output voltage ripple. Highest
prevent large ripple voltage, a low ESR input capacitor
efficiency operation is achieved at low frequency with small
sized for the maximum RMS current should be used. RMS
ripple current. This, however, requires a large inductor.
current is given by :
A reasonable starting point for selecting the ripple current VOUT VIN
IRMS = IOUT(MAX) −1
is ΔIL = 0.4(IMAX). The largest ripple current occurs at the VIN VOUT
highest VIN. To guarantee that the ripple current stays
This formula has a maximum at VIN = 2VOUT, where IRMS
below a specified maximum, the inductor value should be
= IOUT/2. This simple worst-case condition is commonly
chosen according to the following equation :
used for design because even significant deviations do
⎡ VOUT ⎤ ⎡ VOUT ⎤ not offer much relief. Note that ripple current ratings from
L=⎢ ⎥ ⎢1− ⎥
⎣ f × ΔIL(MAX) ⎦ ⎣ VIN(MAX) ⎦ capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate the
Inductor Core Selection capacitor, or choose a capacitor rated at a higher
Once the value for L is known, the type of inductor must temperature than required. Several capacitors may also
be selected. High efficiency converters generally cannot be paralleled to meet size or height requirements in the
afford the core loss found in low cost powdered iron cores, design.
forcing the use of more expensive ferrite or mollypermalloy The selection of COUT is determined by the effective series
cores. Actual core loss is independent of core size for a resistance (ESR) that is required to minimize voltage ripple
fixed inductor value but it is very dependent on the and load step transients, as well as the amount of bulk
inductance selected. As the inductance increases, core capacitance that is necessary to ensure that the control
losses decrease. Unfortunately, increased inductance loop is stable. Loop stability can be checked by viewing
requires more turns of wire and therefore copper losses the load transient response as described in a later section.
will increase. The output ripple, ΔVOUT, is determined by :
Ferrite designs have very low core losses and are preferred ⎡ 1 ⎤
ΔVOUT ≤ ΔIL ⎢ESR + ⎥
at high switching frequencies, so design goals can ⎣ 8fC OUT ⎦
concentrate on copper loss and preventing saturation. The output ripple is highest at maximum input voltage
Ferrite core material saturates “hard”, which means that since ΔIL increases with input voltage. Multiple capacitors
inductance collapses abruptly when the peak design placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special

www.richtek.com DS8024-02 March 2011

8
 RT8024
polymer, aluminum electrolytic and ceramic capacitors are Efficiency Considerations
all available in surface mount packages. Special polymer The efficiency of a switching regulator is equal to the output
capacitors offer very low ESR but have lower capacitance power divided by the input power times 100%. It is often
density than other types. Tantalum capacitors have the useful to analyze individual losses to determine what is
highest capacitance density but it is important to only limiting the efficiency and which change would produce
use types that have been surge tested for use in switching the most improvement. Efficiency can be expressed as :
power supplies. Aluminum electrolytic capacitors have
Efficiency = 100% − (L1+ L2+ L3+ ...)
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple where L1, L2, etc. are the individual losses as a percentage
current ratings and long term reliability. Ceramic capacitors of input power. Although all dissipative elements in the
have excellent low ESR characteristics but can have a circuit produce losses, two main sources usually account
high voltage coefficient and audible piezoelectric effects. for most of the losses : VIN quiescent current and I2R
The high Q of ceramic capacitors with trace inductance losses. The VIN quiescent current loss dominates the
can also lead to significant ringing. efficiency loss at very low load currents whereas the I2R
loss dominates the efficiency loss at medium to high load
Using Ceramic Input and Output Capacitors currents. In a typical efficiency plot, the efficiency curve
Higher values, lower cost ceramic capacitors are now at very low load currents can be misleading since the
becoming available in smaller case sizes. Their high ripple actual power lost is of no consequence.
current, high voltage rating and low ESR make them ideal 1. The VIN quiescent current is due to two components :
for switching regulator applications. However, care must the DC bias current as given in the electrical characteristics
be taken when these capacitors are used at the input and and the internal main switch and synchronous switch gate
output. When a ceramic capacitor is used at the input charge currents. The gate charge current results from
and the power is supplied by a wall adapter through long switching the gate capacitance of the internal power
wires, a load step at the output can induce ringing at the MOSFET switches. Each time the gate is switched from
input, VIN. At best, this ringing can couple to the output high to low to high again, a packet of charge ΔQ moves
and be mistaken as loop instability. At worst, a sudden from VIN to ground.
inrush of current through the long wires can potentially
The resulting ΔQ/Δt is the current out of VIN that is typically
cause a voltage spike at VIN large enough to damage the
larger than the DC bias current. In continuous mode,
part.
IGATECHG = f(QT+QB)
Output Voltage Programming
where QT and QB are the gate charges of the internal top
The resistive divider allows the VFB pin to sense a fraction
and bottom switches. Both the DC bias and gate charge
of the output voltage as shown in Figure 4.
losses are proportional to VIN and thus their effects will
VOUT be more pronounced at higher supply voltages.
2. I2R losses are calculated from the resistances of the
R1
internal switches, R SW and external inductor RL. In
FB
continuous mode the average output current flowing
RT8024 R2
through inductor L is “chopped” between the main switch
GND
and the synchronous switch. Thus, the series resistance
Figure 4. Setting the Output Voltage looking into the LX pin is a function of both top and bottom
MOSFET RDS(ON) and the duty cycle (DC) as follows :
For adjustable about voltage mode, the output voltage is
set by an external resistive divider according to the following RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1−DC)
equation : V R1) The RDS(ON) for both the top and bottom MOSFETs can be
OUT = VREF (1 +
R2 obtained from the Typical Performance Characteristics
where VREF is the internal reference voltage (0.6V typ.)
DS8024-02 March 2011 www.richtek.com
9
RT8024
curves. Thus, to obtain I2R losses, simply add RSW to RL Where TC is the package case (Pin 2 of package leads)
and multiply the result by the square of the average output temperature measured by thermal sensor, PD is the power
current. dissipation defined by user's function and the θJC is the
Other losses including CIN and COUT ESR dissipative junction to case thermal resistance provided by IC
losses and inductor core losses generally account for less manufacturer. Therefore it's easy to estimate the junction
than 2% of the total loss. temperature by any condition.

Thermal Considerations Checking Transient Response

The maximum power dissipation depends on the thermal The regulator loop response can be checked by looking
resistance of IC package, PCB layout, the rate of at the load transient response. Switching regulators take
surroundings airflow and temperature difference between several cycles to respond to a step in load current. When
junction to ambient. The maximum power dissipation can a load step occurs, VOUT immediately shifts by an amount
be calculated by following formula : equal to ΔILOAD (ESR), where ESR is the effective series
resistance of COUT. ΔILOAD also begins to charge or
PD(MAX) = ( TJ(MAX) - TA ) / θJA
discharge COUT generating a feedback error signal used
Where T J(MAX) is the maximum operation junction by the regulator to return VOUT to its steady-state value.
temperature 125°C, TA is the ambient temperature and the During this recovery time, VOUT can be monitored for
θJA is the junction to ambient thermal resistance. overshoot or ringing that would indicate a stability problem.
For recommended operating conditions specification of 450
Single Layer PCB
Maximum Power Dissipation (mW)

RT8024 DC/DC converter, where TJ (MAX) is the maximum 400

junction temperature of the die (125°C) and TA is the 350
SOT-23-5, TSOT-23-5 Packages
maximum ambient temperature. The junction to ambient
300
thermal resistance θ JA is layout dependent. For
250
SOT-23-5/TSOT-23-5 packages, the thermal resistance θJA
200
is 250°C/W on the standard JEDEC 51-3 single-layer
150
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula : 100

50
PD(MAX) = ( 125°C - 25°C ) / 250 = 0.4 W for SOT-23-5/
0
TSOT-23-5 packages
0 20 40 60 80 100 120 140
The maximum power dissipation depends on operating Ambient Temperature (°C)
ambient temperature for fixed T J(MAX) and thermal Figure 5. Derating Curves for RT8024 Package
resistance θJA. For RT8024 packages, the Figure 5 of
derating curves allows the designer to see the effect of Layout Considerations
rising ambient temperature on the maximum power Follow the PCB layout guidelines for optimal performance
allowed. of RT8024.
The value of junction to case thermal resistance θJC is ` For the main current paths as indicated in bold lines in
popular for users. This thermal parameter is convenient Figure 6, keep their traces short and wide.
for users to estimate the internal junction operated
` Put the input capacitor as close as possible to the device
temperature of packages while IC operating. It's
pins (VIN and GND).
independent of PCB layout, the surroundings airflow effects
` LX node is with high frequency voltage swing and should
and temperature difference between junction to ambient.
be kept small area. Keep analog components away from
The operated junction temperature can be calculated by
LX node to prevent stray capacitive noise pick-up.
following formula :
TJ = TC + PD x θJC
www.richtek.com DS8024-02 March 2011
10
 RT8024
VIN VOUT
} Connect feedback network behind the output capacitors. L1
RT8024
4 3
Keep the loop area small. Place the feedback VIN LX
components near the RT8024. C1
R1
1 5
} Connect all analog grounds to a command node and EN FB
C4
then connect the command node to the power ground GND
2 C2 R2
10uF
C3
behind the output capacitors.
VIN
J1

Figure 6. EVB Schematic

Suggested Inductors
Component Inductance DCR Current Rating Dimensions
Series
Supplier (µH) (mΩ) (mA) (mm)
TAIYO YUDEN NR 3015 2.2 60 1480 3 x 3 x 1.5
TAIYO YUDEN NR 3015 4.7 120 1020 3 x 3 x 1.5
Sumida CDRH2D14 2.2 75 1500 4.5 x 3.2 x 1.55
Sumida CDRH2D14 4.7 135 1000 4.5 x 3.2 x 1.55
GOTREND GTSD32 2.2 58 1500 3.85 x 3.85 x 1.8
GOTREND GTSD32 4.7 146 1100 3.85 x 3.85 x 1.8

Suggested Capacitors for CIN and COUT

Component Supplier Part No. Capacitance (µF) Case Size
TDK C1608JB0J475M 4.7 0603
TDK C2012JB0J106M 10 0805
MURATA GRM188R60J475KE19 4.7 0603
MURATA GRM219R60J106ME19 10 0805
MURATA GRM219R60J106KE19 10 0805
TAIYO YUDEN JMK107BJ475RA 4.7 0603
TAIYO YUDEN JMK107BJ106MA 10 0603
TAIYO YUDEN JMK212BJ106RD 10 0805

DS8024-02 March 2011 www.richtek.com

11
RT8024
Outline Dimension

H
D
L

C B

A
A1
e

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.889 1.295 0.035 0.051
A1 0.000 0.152 0.000 0.006
B 1.397 1.803 0.055 0.071
b 0.356 0.559 0.014 0.022
C 2.591 2.997 0.102 0.118
D 2.692 3.099 0.106 0.122
e 0.838 1.041 0.033 0.041
H 0.080 0.254 0.003 0.010
L 0.300 0.610 0.012 0.024

SOT-23-5 Surface Mount Package

www.richtek.com DS8024-02 March 2011

12
 RT8024

H
D
L

C B

A
A1
e

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 1.000 0.028 0.039
A1 0.000 0.100 0.000 0.004
B 1.397 1.803 0.055 0.071
b 0.300 0.559 0.012 0.022
C 2.591 3.000 0.102 0.118
D 2.692 3.099 0.106 0.122
e 0.838 1.041 0.033 0.041
H 0.080 0.254 0.003 0.010
L 0.300 0.610 0.012 0.024

TSOT-23-5 Surface Mount Package

Richtek Technology Corporation Richtek Technology Corporation

Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com

Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.

DS8024-02 March 2011 www.richtek.com

13