VERILOG HDL [INTEL]:-

-----------------------------MODULE 1: VERILOG
OVERVIEW-----------------------------
Verilog is a IEEE standard Hardware Description Language, a text based language
used to describe circuits (or model hardware) to be implemented in hardware.
- Used for simulation & synthesis

Two ways to model your circuits:-

1. Behavioral modeling:
- A component is described by its input/output response
- Output behavior is described in relation to inputs
- You describe the functionality, not the structure of circuit
- Relies on synthesis engine to create correct circuits matching the behavior
- Behavorial code example of shift operation:
//
if(shift left) begin
out[0] <= #5 0;
for (j=1; j<8; j=j+1)
out[j] <= #5 out[j-1];
end
//

2. Structural modeling:
- A component is described by its interconnecting lower- level
components/primitives
- Both functionality & structure of circuit are described
- Particular hardware element are called out and wired together

Both structural and behavior models are used in modern designs

> Register Transfer Level (RTL): A type of behavioral modeling that defines input &
output relationships in terms of dataflow operations inside hardware model.
RTL constructs are synthesizable

> Synthesis: the translation and optimization of HDL code into circuit.

> RTL Synthesis: translation of RTL model of hardware into an omptimized technology
specific gate level implementation

RTL SYNTHESIS:-
The synthesis engine translates code into hardware using architectural elements
of your target device. Then it is optimized to ensure you have the optimal
implementation of your circuit description. E.g.
//
always @(a, b, c, d, sel)
case (sel)
2'b00: mux_out = a;
2'b01: mux_out = b;
2'b10: mux_out = c;
2'b11: mux_out = d;
endcase
//

TYPICAL RTL SYNTHESIS & SIMULATION FLOWS:-

Verilog models can be sent through two different flows,

1. Synthesis Flow: Synthesis compiler (e.g. Synplify, Altera's Synthesis Engine)

will
use the technology available in the target device library to translate and optimize
the verilog model into a technology-specific netlist that can be used for Timing
Analysis, Simulation or placed and routed into a specific device.

2. Simulation Flow: Using siumlators e.g. ModelSim, the simulation compiler will
simulate your Verilog model with stimulus provided by either a Verilog testbench
or through test vectors to output text or waveforms

> Most synthesis tools can also write out a post-synthesis Verilog file to check
the
synthesis results before place/routing. The output Verilog file from the synthesis
tool can replace the og Verilog files in the simulator. The same testbench and
test vectors can be used for verification.
> Additional simulation model files may be required depending on synthesis tool.
Can
be provided by synthesis vendor or generated by synthesis tool along with the
post-synthesis model.

-----------------------------MODULE 2: MODULE
STRUCTURE-----------------------------

BASIC MODELING STRUCTURE IN VERILOG:

A Verilog HDL model consists of:
//
module module_name (port_list);
port declarations
data type declarations - variables and nets are declared
circuit functionality
timing specifications - optional (applicable to simulation environments)
endmodule
//

> begins with keyword: module and ends with: endmodule

> case-sensitive, all keywords are lowercase
> whitespace is ignored (for readability)
> semicolon is the statement terminatior
> // for single line comment
> /* Multi-line comment goes here */
> Timing specification is for simulation

The following Verilog HDL module produces a Multiplier Accumulator Block:

- PORT LIST DECLARATION:

module mult_acc (out, ina, inb, clk, acclr);

- PORTS AND DATA TYPES:

input [7:0] ina, inb;
input clk, aclr;
output [15:0] out;

wire [15:0] mult_out, adder_out;

reg [15:0] out;

- CONTINUOUS ASSIGN STATEMENT SYNTHESIZED INTO A COMBINATORIAL ADDER:

assign adder_out = mult_out + out;
- SEQUENTIAL REGISTER CODE:
always @ (posedge clk or posedge aclr)
if (aclr) out = 16'h0000;
else out = adder_out;

- MODULE THAT DESCRIBES THE MULTIPLIER:

multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));

-
endmodule

MODULE DECLARATION:
- provides module name
- includes port list, which contains all inputs, outputs and bi-directional
connections
to a module.

PORT DECLARATIONS:
- associates each port with a port type. There are 3 types:
1. input
2. output
3. inout (bi-directional ports)
- structure: port_type port_name;
- buses have a square brackets following port type with bus size:
port_type [bus:size] port_name; {where [MSB:LSB]}
- For example,
input [7:0] ina, inb; > are 8 bit inputs
input clk, aclr; > 1 bit inputs
output [15:0] out; > 16 bit output bus

VERILOG 2001+ MODULE/PORT DECLARATION:

- you can now include port list and port declaration in a concise manner, E.G.
//
module mult_acc
(
input [7:0] ina, inb,
input clk, aclr,
output [15:0] out
);
//

DATA TYPES:
After port declaration, we declare data types.
There are 2 fundamental types of data in Verilog HDL:
1. Net data types: Nets represnt physical interconnects between processes or
functional
blocks. They need to be driven continuously and do not store value.
2. Variable data types: Used to temporarily store data. Similar to variables in
other
languages. They may be synthesized into hardware flip flops or registers or
combinatorial nodes depending on usage

> Nets are like wires, variables are like componenets

> FOUR common NET DATA TYPES (supported by synthesis):

1. wire - represents a node or connection | used for
2. tri - represents a tri-state node | interconnects
3. supply0 - logic 0 | used to represent a
 4. supply1 - logic 1 | constant logic value

EXAMPLE:
data_type [MSB:LSB] signal_type
- wire [7:0] out;
- tri enable

> VARIABLE DATA TYPES:

1. reg - unsigned variable of any bit size
= does not necessarily refer to a physical register, actual implementation
will
depend on usage
= use reg signed
2. integer - 32-bit signed variables
3. real, time, realtime - for simulation purposes only (not synthesis support)

-- Variable data types can only be assigned within a procedure, task or function.
-- Cannot be driven using the continuous assignment statement: assign

-- Bus declarations can be made the same way as wires using reg, e.g.
reg [MSB:LSB] signal-name;
reg [LSB:MSB] signal-name;
reg [7:0] out;
integer count;

> INSTANTIATION:
-- instantiation is when a computer system creates a new context based on a pre-
existing
model or scheme, the model is said to have been instantiated.
-- the enscapulated context that results from this is an instance of the model
-- once a module is declared, it may be instantiated at a higher level module by
using:
<component_name> #<delay> <instance_name> (port_list);

1. First we write the lower level component name, that we declared

2. A time delay through the component can be expressed using #delay but it is
optional.
Only used in simulation and not during synthesis.
3. Then we specify an instance name, a unique name applied to the component
instance
4. Finally, specify a list of signals to connect to inputs and outputs of the lower
level component.

-- Instantiating modules can create designs with multiple levels hierarchy to

achieve
easier maintainability. Modern designs typically have many layers of hierarchy

> CONNECTING MODULE INSTANTIATION PORTS:

-- when connecting signals to lower level module ports, there are two methods to
define
the port connections:
1. by ordered list
2. by name

-- instantiating 2 instances of half_adder modules using both methods, for a

full_adder
//
module full_adder (
 output fco, fsum,
input cin, a, b
);
wire c1, s1, c2;

half adder u1 (c1, s1, a, b);

half_adder u2 (.a(s1), .b(cin), .sum(fsum), .co(c2)); //.port(wire)
or u3(fco, c1, c2);
endmodule
//

1. By Ordered List:
- port connections defined by order of port list in lower-level module declaration
module half_adder (co, sum, a, b);
- order of port connection DOES matter (use for modules w/ few ports),
co -> c1, sum -> s1, a -> a, b -> b

2. By Name:
- port connections defined by name
- recommended method
- order of port connection DOES NOT matter
a -> s1, b -> cin, sum -> fsum, co -> c2

> PORT CONNECTION RULES:-

-- connections into and out of modules must obey certain rules.
-- ports of a module and the connections to a module can only be declared of
certain data type
-- when declaring a module, signals of the variable type cannot be used as input
or inout ports, while the net data type can be used in all situations.
-- implicitly, input & outputs default to wire if no type is specified.

-- when connecting a signal to a lower level module's ports, variables cannot be

connected to outputs or inouts of the module, while net data type can be used
in all situations.

TYPE REQUIREMENTS FOR PORT CONNECTION WHEN MODULES ARE INSTANTIATED:

1. driving from a variable or net > input from HLM to LLM > net (LLM)
2. variable or net > output from LLM to HLM > driving into a net (HLM)
3. net < inout b/w LLM and HLM > driving from/into a net (HLM)

> PARAMETERS:-
-- Parameters can be used to have a value assigned to a symbolic name.
-- Using the keyword: parameter
-- You can base construct information like size and settings on the symbolic name
to
make code readable and meaningful.
-- Parameters must resolve to a constant at compile time, they cannot be changed
during module execution
-- Parameters can be floating point ("real parameter")
-- Parameters can be overwritten during compilation from a module intantiating the
module containing the parameters.
-- Exception to this: by defining a parameter as a local parameter using:
localparam - local parameter cannot be overwritten at compile time.
//
parameter size = 8; // size is parameter equal to 8
localparam outsize = 16; // local parametr having value 16
reg [size-1:0] dataa, datab;
reg [outsize-1:0] out
//

+For Verilog-2001 plus, you can declare variable along module declaration:
//
module mult_acc
#(parameter size = 8)
(....);
//

> ASSIGNING VALUES - NUMBERS:-

Numbers can be assigned to variables in two ways:
1. Sized: 3'b010 = 3-bit wide binary number
! prefix 3 indicates size number
2. Unsized: 123 = 32-bit wide decimal number by default
! No specified base - defaults to decimal
! No specified size - defaults to 32-bit wide number

FORMAT OF NUMBER:
= size, tick, letter/letters for format, actual number

-- Decimal ('d or 'D): 16'd255 = 16-bit decimal

-- Hexadecimal ('h or 'H): 8'h9a = 8-bit hexadecimal
-- Binary ('b or 'B): 'b1010 = 32-bit binary
-- Octal ('o or 'O): 'o21 = 32-bit octal
-- Signed/2's complement representa ('s or 'S): 16'shFA = signed 16-bit hexa value
! here 16'shFA i equal to -16'h06

> NUMBERS:
-- For a negative number: specify a minus sign before the size or else error. E.g.,
-8'd3 = legal 8-bit negative number stored as 2's complement of 3

-- Special number characters:

- '_' for readability = 32'h21_65_bc_fe
- 'x' or 'X' for unknown value = 12'h12x (Unknown LSBs)
- 'z' or 'Z' for high impedance value = 1'bz (1-bit high impedance number)

! if MSB is 0, x or z, number is extended to fill MSBs with 0, x or z

! if MSB is 1, number is extneded to fill MSBs with 0

> ARITHMETIC OPERATORS:-

Verilog has +, -, *, /, %, ** (exponent)
! Some synthesis tools may not support divide or exponent
! Others only do if the second operand is a constant

-- the operators treat input vectors as whole numbers

-- if x or z values appear in operands, result will be unknown
-- carry bits are handled automatically if result is wider than operands
-- if result vector is the same size as the operands then carry will be lost

> BITWISE OPERATORS:-

The bitwise operators can be unary or binary and they include:
- NOT: '~'
- AND: '&'
- OR: '|'
- XOR: '^'
- XNOR: '^~' or '~^'

-- These operators operate on each bit of the operands.

-- If operand is of different sizes, smaller opperand is left-extended
-- The result is the size of the largest operand
-- x and z give known value results in AND only (in case of 0 & x)

> REDUCTION OPERATORS:-

Reduction operators are unary operations that reduce a vector to single bit. Such
as
- AND (&), OR (|), XOR (^) and XNOR (~^ / ^~) are same
- NAND: '~&'
- NOR: '~|'

-- Reduces vector (performed on single variable) to a single bit value. e.g.,

ain = 4'b1010; bin = 4'b10xz;
&ain gives 1'b0
|bin gives 1'b1
^bin gives 1'bx
-- X or Z are unknowns but may result in a known value

> RELATIONAL OPERATORS:-

Relational operates are used to compare operands, they return a single value.
These include >, <, >=, <=

-- Returns a 1 bit scalar value of Boolean (1 or 0)

-- If either operand contains X or Z, result will be unknown. E.g.,
ain = 3'b101; bin = 3'b110;
ain <= bin gives 1'b1
ain > bin gives 1'b0

> EQUALITY
Also used to compare values, returning one-bit True (1) or False (0) value

- ==: equality
- !=: inequality
- ===: case equality
- !==: case inequality

-- For == and !=, result will be unknown if operands contain x or z

-- Case equality/inequality supports x and z (considered distinct values and must
be matched exactly). Often used in simulation environments.

Examples:
Here, ain = 3'b101; bin = 3'b110; c = 3'b01x;
- ain != bin gives 1'b1
- cin == cin gives 1'bx
- ain === bin gives 1'b0
- cin === 1'b1

> LOGIC OPERATORS:-

Used to evaluate single expression or compare multiple expressions.
- Each operand is considered a single expression
- Expressions with zero value are false (0)
- Non-zero valued expressions are true (1)
- Can be unary or binary
- Usually used in if and while statements

- ! : Expression not true

- && : AND of two expressions
- || : OR of two expressions
- Returns 1 or 0, and X and Z give unknown result

EXAMPLE:
Here, ain = 3'b101; bin = 3'b000; c = 3'b01x;
- !ain gives 1'b10, !cin gives 1'bx and !bin gives 1'b1
- ain && bin gives 1'b0, bin && cin gives 1'bx
- ain || bin gives 1'b1, ain || cin gives 1'bx

> SHIFT OPERATORS:

Shifts a vector left or right some defined number of bits
- Left shifts (logical or arithmetic): vacated positions always filled with zero
- Right shifts:
= Logical: Vacated positions always filled with zero
= Arithmetic (unsigned): Vacated positions filled with zero
= Arithmetic (signed): Vacated positions filled with sign bit value (MSB val)
- Shifted bits are lost
- Shifts by X or Z values on the right operand return unknown

Here, ain = 3'b101; bin = 3'b01x;

- << : Logical shift left
ain << 2 gives 3'b100 and bin << 2 gives 3'bx00
- >> : Logical shift left
bin >> 2 gives 3'b000
- <<< : Arithmetic shift left
ain <<< 2 gives 3'b100 and bin <<< 2 gives 3'bx00
- >>> : Arithmetic shift right
ain >>> 2 gives 3'b111 (signed) and bin >>> 2 gives 3'b000 (signed)

> MISC. OPERATORS:

- ?: Conditional Operator: acts like a compressed if-then statement.
SYNTAX: (condition) ? true_value : false_value.
EXAMPLE: sig_out = (sel == 2'b01) ? a : b

- {} Concatenate: combines two or more vectors to form one large vector.

EXAMPLE: ain = 3'b010; bin = 3'110
{ain,bin} gives 6'b010110

- {{}} Replicate: takes one vector and replicates it a specified no. of times
EXAMPLE: {3{3'b101}} gives 9'b101101101

> OPERATORS PRIORITY

Use parenthesis to improve priority, clarity and readability.

1. UNARY OPERATORS (one operand): +, -, !, ~, &, ~& etc.

2. **
3. *, /, %
4. BINARY OPERATORS: +, -
5. <<, >>, <<<, >>>
6. ==, !=, ===, !===
7. BINARY OPERATOR: &
8. BINARY OPERATORS: ^, ~^, ^~
9. BINARY OPERATOR: |
10. &&
11. ||
12. ?:
13. {}, {{}}

SECTION 3: MAKING ASSIGNMENTS

Two ways to make assignments:
1. Continuous Assignment statements
2. Procedural Assignment statements

> CONTINUOUS ASSIGNMENT STATEMENTS:-

Used to represent combinatorial logic using expressions and operators.
wire[15:0] adder_out;
assign adder_out = mult_out + out

- Properties:
1. Left hand side must be a net data type (wire and tri)
2. Always active. When one RHS operands changes, expression is evaluated and
LHS net is updated immediately.
3. Continuous assignmetns can be made implicitly when net is declared. E.g.,
wire[15:0] adder_out = mult_out + out;
4. RHS can be net, register or function calls.
5. In simlation, delat values can be assigned to model gate delays. E.g.,
assign #5 adder_out = mlt_out + out

- Here, adder_out will be updated every 5 time units later

> PROCEDURAL ASSIGNMENT STATEMENTS:-

Made inside procedural assignment blocks. Two types of them:
1. initial block: Used to initialize behavorial statements for simulation
2. always block: To describe circuit functionality using behavorial statements
Always executing in looping fashion.

- Each always and initial block represents a separate process

- Processes run in parallel and start at siumlation time 0
- Statements inside a process execute sequentially
- always and inital blocks cannot be nested

> INITAL BLOCKS:-

Used in simulation for purposes of initialization or monitoring (may also be used
in
synthesis, e.g., using inital block to specify initial RAM content)

- Consists of behavorial statements, which execute sequentially (order matters)

- Starts at time 0, executes once during simulation and not again
- The duration of the block may be infinite
- Keywords 'begin' and 'end' must be used if block contains more than 1 statements
- For example,
+ Initialization + Monitoring + Turning something on once

> ALWAYS BLOCKS:-

Used to model a process that repeats continuously in a circuit.

- Also consist of behavorial statements

- Executes concurrently starting at time 0 and continuously in a loop
- All always block execute concurrently. Difference is in statements within
- Statements are executed sequentially. Order matters
- Keyword 'begin' and 'end' ust be used if block contains more than 1 statement
EXAMPLE:
//////////
module clk_gen
#(parameter period = 50)
(
output reg clk
);

initial clk = 1'b0 // Initializes clock signal to 0 at time 0

always // Toggles clock signal

#(period/2) clk = ~clk // #(time) sets delay
// Here always statement toggles value of clock every 25 time units

initial #100 $finish; // Stops simulation after 100 time units

endmodule
//////////

> TYPES OF PROCEDURAL ASSIGNMENTS:-

LHS of procedural assignment must be a variable data type. Either reg, integer,
real, time or realtime variables. RHS can be any valid expression or signal. The
value placed on variable will remain until another procedural assignment updates
it.

There are two types within an always or initial procedural,

1. Blocking Assignment (=): Executed in the order that they are specified in a
sequential block. Staements after a blocking assignment won't be evaluated
until blocking assignment has finished executing.

2. Nonblocking Assignment (<=): Allow scheduling of assignments without blocking

execution of statements that follow in a sequential block. Scheduled to execute
at the end of time step, moving on to following statements until execution.

> BLOCKING VS NONBLOCKING:-

1. Blocking:
//////////
initial
begin
a = #5 b;
c = #10 a;
end
//////////
Here, 'a' gets value of 'b' at timestep 5 and since this is a blocking assignment,
'c' does not get evaluated to 'a' until 10 more timesteps pass (15 timestep)

2. Nonblocking:
//////////
initial
begin
a <= #5 b;
c <= #10 a;
end
//////////
Here, compiler schedules assignment of 'a' at timestep 5 then moves on to next,
which schedules assignment of 'c' at timestep 10. at timestep 5, 'a' gets the
value of 'b' and at timestep 10, 'c' gets evaluated to 'a'

EXAMPLE:
//////////
always a( posedge clk )
begin
x <= next_x;
y <= x;
end
//////////
Here, y gets the value of x first then x gets next_x. Thus it takes two clock
cycles
for next_x to get to y. Here two registers are inferred.
If it was a blocking statement, the transfer would occur in the same clock edge
so only one ff (1-bit flip-flop register) is inferred.

> RULE OF THUMB FOR BLOCKING/NONBLOCKING:-

- Use blocking operator (=) for combinatorial logic.
- Use nonblocking operator (<=) for sequential logic.

> TWO TYPES OF RTL PROCESSES:-

-------
RTL (Register Transfer Language) is an intermediate representation close to
assembly language, e.g. used in compiler. It is used to describe data flow at the
register-transfer level of an architecture
--------
RTL SYNTHESIS is the process of converting RTL code, typically written in hardware
description languages like Verilog, into a gate-level netlist. It involves mapping
the functionality specified in the RTL code to a library of standard cells, such as
NAND, NOR, XOR gates, provided by the target technology.
--------
- Always block can be defined with an associated sensitivity list, which controls
the execution of an always block. It follows the keyword 'always' and beings with
the @ symbol. E.g.,
always @(sensitivty list which includes all inputs)

- Always block will only execute after change in any signal in the list.
- Sensitivity list can be further controlled by two keywords;
1. posedge - only positive edged transitions will trigger always block
2. negedge - only negative edged transitions will trigger always block

- Sensitivity list can be used to infer the two types of RTL processes:
1. Combinatorial Process: Sensitive to all inputs used in the logic. E.g.,
always @(a, b, sel)
always @* // * indicates all inputs
2. Clocked Process: Sensitive to clock or/and asynchronous control signals.
Does not include the d or ena inputs.
always @(posedge clk, negedge clr_n)