22/08/17

Concept of Verilog “Module”

• In Verilog, the basic unit of
hardware is called a module.
module module_name (list_of_ports);
– A module cannot contain definition
Lec ture 06: VERILO G LANG UAG E FEATURES input/output declarations
of other modules.
(PART 1) local net declarations
– A module can, however, be
instantiated within another Parallel statements
PROF. INDRANIL SENGUPTA
DEPARTMENT OF COMPUTER SCIENCE AND module. endmodule
ENGINEERING
– Instantiation allows the creation of
a hierarchy in Verilog description.

Hardware Modeling Using Verilog 2

This is also behavioral description.

• One possible gate level realization
/* A 2-level combinational circuit */
// A simple AND function module two_level (a, b, c, d, f); is shown.
This is a behavioral description. The
module simpleand (f, x, y); input a, b, c, d; • t1 and t2 are intermediate lines;
synthesis tool will decide how the
output f; termed as wire data type.
input x, y; realize f:
wire t1, t2; // Intermediate lines
output f; a) Using a single AND gate a t1
assign t1 = a & b; G1
assign f = x & y; b) Using a NAND gate followed by a b
assign t2 = ~(c | d); f
NOT gate. assign f = ~(t1 & t2); G3
endmodule
endmodule c
G2
d t2

Hardware Modeling Using Verilog 3

Hardware Modeling Using Verilog 4

• Point to note: Data Types in Verilog

– The “assign” statement represents continuous assignment, whereby the
• A variable in Verilog belongs to one of two data types:
variable on the LHS gets updated whenever the expression on the RHS
changes. a) Net
• Must be continuously driven.
assign variable = expression;
• Cannot be used to store a value.
– The LHS must be a “net” type variable, typically a “wire”.
• Used to model connections between continuous assignments and
– The RHS can contain both “register” and “net” type variables. instantiations.
– A Verilog module can contain any number of “assign” statements; they are b) Register
typically placed in the beginning after the port declarations. • Retains the last value assigned to it.
– The “assign” statement models behavioral design style, and is typically • Often used to represent storage elements, but sometimes it can translate to
used to model combinational circuits. combinational circuits also.

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(a) Net data type

• Nets represents connection between hardware elements. • Various “Net” data types are supported for synthesis in Verilog:
• Nets are continuously driven by the outputs of the devices they – wire, wor, wand, tri, supply0, supply1, etc.
are connected to. • “wire” and “tri” are equivalent; when there are multiple drivers
a driving them, the driver outputs are shorted together.
– Net “a” is continuously driven by the output of the AND gate. • “wor” and “wand” inserts an OR and AND gate respectively at the
connection.
• Nets are 1-bit values by default unless they are declared explicitly
as vectors. • “supply0” and “supply1” model power supply connections.
– Default value of a net is “z”. • The Net data type “wire” is most common.

Hardware Modeling Using Verilog 7

Hardware Modeling Using Verilog 8

module use_wire (A, B, C, D, f); module use_wand (A, B, C, D, f);

input A, B, C, D; input A, B, C, D;
output f; output f;
module using_supply_wire (A, B, C, f);
supply0 and supply1 have
wire f; wand f; input A, B, C; the greatest signal
// net f // net f output f; strength.
declared as declared as supply0 gnd;
‘wire’ ‘wire’
supply1
assign f = A & B; assign f = A & B;
vdd;
assign f = C | assign f = C | nand G1
D; D; (t1, vdd, A,
For A = B = 1, and C = D = 0, Here, function realized will be
endmodule endmodule B);
f will be indeterminate. f = (A & B) & (C | D)
xor
G2 (t2, C,
Hardware Modeling Using Verilog gnd); Hardware Modeling Using Verilog
9 10
and G3
(f, t1, t2); endmodule

Data Values and Signal Strengths Strength Type

• Verilog supports 4 value levels and 8 strength levels to model the functionality supply Driving
of real hardware. strong Driving • If two signals of unequal strengths get
Strength increases

– Strength levels are typically used to resolve conflicts between signal drivers of pull Driving driven on a wire, the stronger signal
different strengths in real circuits. will prevail.
large Storage
Value Level Represents • These are particularly useful for MOS
Initialization: weak Driving level circuits, e.g. dynamic MOS.
0 Logic 0 state • All unconnected nets are set medium Storage
1 Logic 1 state to “z”. small Storage
x Unknown logic state • All register variables set to
highz High impedance
“x”.
z High impedance state

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2
 22/08/17

END OF LECTURE 06 Lec ture 07: VERILO G LANG UAG E FEATURES

(PART 2)

PROF. INDRANIL SENGUPTA

DEPARTMENT OF COMPUTER SCIENCE AND
ENGINEERING

Hardware Modeling Using Verilog 13

(b) Register Data Type

• In Verilog, a “register” is a variable that can hold a value. • “reg” data type:
– Unlike a “net” that is continuously driven and cannot hold any value. – Default value of a “reg” data type is “x”.
– Does not necessarily mean that it will map to a hardware register during synthesis.
– It can be assigned a value in synchronism with a clock or even otherwise.
– Combinational circuit specifications can also use register type variables.
– The declaration explicitly specifies the size (default is 1-bit):
• Register data types supported by Verilog:
reg x, y; // Single-bit register variables
i. reg : Most widely used
reg [15:0] bus; // A 16-bit bus
ii. integer : Used for loop counting (typical use)
– Treated as an unsigned number in arithmetic expressions.
iii. real : Used to store floating-point numbers
– Must be used when we model actual sequential hardware elements like
iv. time : Keeps track of simulation time (not used in synthesis)
counters, shift registers, etc.

Hardware Modeling Using Verilog 15

Hardware Modeling Using Verilog 16

module simple_counter (clk, rst, count); module simple_counter (clk, rst, count);
input clk, input clk,
rst; output [31:0] rst; output [31:0]
32-bit counter with
count; count;
synchronous reset. 32-bit counter with
reg [31:0] count; reg [31:0] count;
• Count value increases at asynchronous reset.
always @(posedge clk) the positive edge of the always @(posedge clk or posedge rst) • Here reset occurs
begin clock. begin whenever “rst” goes high.
if (rst) • If “rst” is high, the counter if (rst) • Does not synchronize with
count = 32’b0; is reset at the positive edge count = 32’b0; clock.
else of the next clock. else
count = count + count = count + 1;
1; end
end endmodule
endmodule
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• “integer” data type: • “real” data type:

– It is a general-purpose register data type used for manipulating quantities. – Used to store floating-point numbers.
– More convenient to use in situations like loop counting than “reg”. – When a real value is assigned to an integer, the real number is rounded off
– It is treated as a 2’s complement signed integer in arithmetic expressions. to the nearest integer.
– Default size is 32 bits; however, the synthesis tool tries to determine the – Example:
size using data flow analysis. real e, pi;
– Example: initial integer x;
wire [15:0] X, Y; initial
integer C; begin x =
e = pi; //
Z = X +
2.7 Gets
Y; value 3
18;
• Size of Z can be
pi =
deduced to be 17 Hardware Modeling Using Verilog Hardware Modeling Using Verilog
19 314 20
(16 bits plus a
.15
carry).
9e-
2;
end

• “time” data type: Vectors

– In Verilog, simulation is carried out with respect to a logical clock called • Nets or “reg” type variable can be declared as vectors, of multiple bit widths.
simulation time. – If bit width is not specified, default size is 1-bit.
– The “time” data type can be used to store simulation time. • Vectors are declared by specifying a range [range1:range2], where range1 is
– The system function “$time” gives the current simulation time. always the most significant bit and range2 is the least significant bit.
– Example: • Examples:
time curr_time; wire x, y, z; // Single bit variables
initial wire [7:0] sum; // MSB is sum[7], LSB is sum[0]
... reg [31:0] MDR;
curr_time = reg [1:10] data; // MSB is data[1], LSB is data[10]
$time; reg clock;

Hardware Modeling Using Verilog 21

Hardware Modeling Using Verilog 22

Multi-dimensional Arrays and Memories

• Parts of a vector can be addressed and used in an expression. • Multi-dimensional arrays of any dimension can be declared in Verilog.
• Example: • Example:
– A 32-bit instruction register, that contains a 6-bit opcode, three register operands reg [31:0] register_bank[15:0]; // 16 32-bit registers
of 5 bits each, and an 11-bit offset. integer matrix[7:0][15:0];
reg [31:0] IR; opcode = • Memories can be modeled in Verilog as a 1-D array of registers.
reg [5:0] opcode; IR[31:26]; reg1 = – Each element of the array is addressed by a single array index.
reg [4:0] reg1, reg2, reg3; IR[25:21]; reg2 = – Examples:
reg [10:0] offset; IR[20:16]; reg3 = reg mem_bit[0:2047]; // 2K 1-bit
IR[15:11]; words reg [15:0] mem_word[0:1023]; // 1K 16-
offset = IR[10:0]; bit words

Hardware Modeling Using Verilog 23

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4
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Specifying Constant Values Parameters

• A constant value may be specified in either the sized of the
• A parameter is a constant with a given name.
unsized form.
Variables of type integer and real – We cannot specify the size of a parameter.
– Syntax of sized form: – The size gets decided from the constant value itself; if size is not specified, it is
are typically expressed in unsized
<size>’<base><number> form. taken to be 32 bits.
– Examples: • Examples:
4’b0101 // 4-bit binary number 0101 parameter HI = 25, LO = 5;
1’b0 // Logic 0 (1-bit) parameter up = 2b’00, down = 2b’01, steady = 2b’10;
12’hB3C // 12-bit number 1011 0011 1100 parameter RED = 3b’100, YELLOW = 3b’010, GREEN = 3b’001;
12’h8xF // 12-bit number 1000 xxxx 1111
25 // signed number, in 32 bits (size not specified)

Hardware Modeling Using Verilog 25

Hardware Modeling Using Verilog 26

// Parameterized design:: an N-bit counter

module counter (clear, clock, count);

parameter N = 7;
input clear, clock;
output [0:N] count;
count;
reg [0:N]
END OF LECTURE 07
always @ (negedge clock)
if (clear) Any variable assigned
within the “always”
count <= 0;
block must be of type
else
“reg”.
count <= count + 1;
endmodule

Hardware Modeling Using Verilog 27

Hardware Modeling Using Verilog 28

Predefined Logic Gates in Verilog

• Verilog provides a set of predefined logic gates.
– Can be instantiated within a module to create a structured design.
– The gates respond to logic values (0, 1, x or z) in a logical way.
Lec ture 08: VERILO G LANG UAG E FEATURES 2-input AND 2-input OR 2-input EXOR
(PART 3) 0&0=0 0|0=0 0^0=0
0&1=0 0|1=1 0^1=1
PROF. INDRANIL SENGUPTA 1&1=1 1|1=1 1^1=0
DEPARTMENT OF COMPUTER SCIENCE AND 1&x=x 1|x=1 1^x=x 0
ENGINEERING
0&x=0 0|x=x ^x=x
1&z=x 1|z=x 1^z=x
z&x=x z|x=x z ^x = x

Hardware Modeling Using Verilog 30

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List of Primitive Gates

• Some restriction when instantiating primitive gates:
and G (out, in1, in2); bufif1 G (out, in, ctrl); – The output port must be connected to a net (e.g. a wire).
G (out, in, ctrl); • An “output” signal is a wire by default, unless explicitly
nand G (out, in1, in2);
declared as a register.
or G (out, in1, in2); bufif0 G (out, in, ctrl);
G (out, in, ctrl);
– The input ports may be connected to nets or register type
nor G (out, in1, in2); variables.
notif0
G (out, in1, in2); – They have a single output but can have any number of inputs (except NOT
xor There are gates with tristate
xnor G (out, in1, in2);
notif1 and BUF).
controls
not G (out, in); – When instantiating a gate, an optional delay may be specified.
G (out, in); • Used for simulation.
buf • Logic synthesis tools ignore the time delays.

Hardware Modeling Using Verilog 31

Hardware Modeling Using Verilog 32

The `timescale Directive

`timescale 10ns/1ns
t3 • Often in a single simulation, delay values in one module need to be specified in
module exclusive_or (f, a, b); m3
input a, b; terms of some time unit, while those in some other module need to be
specified in terms of some other time unit.
output f; a f
m1 t1 m4 • The `timescale compiler directive can be used:
wire t1, t2, t3;
b `timescale <reference_time_unit> / <time_precision>
nand #5 m1 (t1, a, b); and
#5 m2 (t2, a, t1); and • The <reference_time_unit> specifies the unit of measurement for time.
m2
#5 m3 (t3, t1, b); nor t2 • The <time_precision> specifies the precision to which the delays are rounded
#5 m4 (f, t2, t3); off during simulation.
endmodule – Valid values for specifying time unit and time precision are 1, 10 and 100.

Hardware Modeling Using Verilog 33

Hardware Modeling Using Verilog 34

Specifying Connectivity during Instantiation

• Example: • When a module is instantiated within another module, there are
`timescale 10ns/1ns two ways to specify the connectivity of the signal lines between
– Reference time unit is 10ns, and simulation precision is 1ns. the two modules.
– If we specify #5 as delay, it will mean 50ns. a) Positional association
– The time units can be specified in s (second), ms (millisecond), us (microsecond), • The parameters of the module being instantiated are listed in the same order as
ps (picosecond), and fs (femtosecond). in the original module description.
b) Explicit association
• The parameters of the module being instantiated are listed in arbitrary order.
• Chance of errors is less.

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Hardware Modeling Using Verilog 36

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 22/08/17

module testbench; module testbench;

reg X1,X2,X3,X4.X5,X6; wire OUT; Positional reg X1,X2,X3,X4.X5,X6; wire OUT; Explicit
example DUT(.OUT(Y),.X1(A),.X2(B),.X3(C),
example DUT(X1,X2,X3,X4,X5,X6,OUT); Association .X4(D),.X5(E),.X6(F));
Association
initial module example module example
begin initial
(A,B,C, (A,B,C
$monitor ($time,” X1=%b, X2=%b, begin
D,E,F,Y) ,D,E,F,Y
X3=%b, X4=%b, X5=%b, X6=%b, $monitor ($time,” X1=%b, X2=%b,
; );
OUT=%b”, X1,X2,X3,X4,X5,X6,OUT); X3=%b, X4=%b, X5=%b, X6=%b,
wire t1, t2, wire t1, t2,
#5 X1=1;X2=0; X3=0; X4=1; X5=0; X6=0; OUT=%b”, X1,X2,X3,X4,X5,X6,OUT);
t3, Y; t3, Y;
#5 X1=0; X3=1; #5 X1=1;X2=0; X3=0; X4=1; X5=0; X6=0;
nand #1 G1 (t1,A,B); #5 X1=0; X3=1; nand #1 G1 (t1,A,B);
#5 X1=1; X3=0;
and #2 G2 (t2,C,~B,D); #5 X1=1; X3=0; and #2 G2 (t2,C,~B,D);
#5 X6=1;
nor #1 G3 (t3,E,F); #5 X6=1; nor #1 G3 (t3,E,F);
#5 $finish;
nand #1 G4 (Y,t1,t2,t3); #5 $finish; nand #1 G4 (Y,t1,t2,t3);
end
endmodule end endmodule
endmodule
endmodule
Hardware Modeling Using Verilog 37
Hardware Modeling Using Verilog 38

Hardware Modeling Issues module reg_maps_to_wire (A, B, C, f1, f2);

input A, B, C;
• In terms of the hardware realization, the value computed can be assigned to: output f1, f2;
– A “wire” wire A, The synthesis system
– A “flip-flop” (edge-triggered storage cell) B, C; will generate a wire for
– A “latch” (level-triggered storage cell) reg f1, f2; f1.
• A variable in Verilog can be either “net” or “register”. always @(A or B or C)
– A “net” data type always map to a “wire” during synthesis. begin
– A “register” data type maps either to a “wire” or a “storage cell” depending upon f1 = ~(A & B);
the context under which a value is assigned. f2 = f1 ^ C;
end
endmodule

Hardware Modeling Using Verilog 39

Hardware Modeling Using Verilog 40

// A latch gets inferred here

module a_problem_case (A, B, C, f1, f2);
module simple_latch (data, load, d_out);
input A, B, C;
input data, load;
output f1, f2;
output d_out;
wire A, The synthesis system
wire t; The “else” part is
B, C; will generate a wire for missing. So a latch will
f1, and a storage cell for always @(load or
reg f1, f2; be generated for “t”.
f2. data)
always @(A or B or C)
begin
begin
if (!load)
f2 = f1 ^ f2;
t = data;
f1 = ~(A & B); d_out = !t;
end
end
endmodule
endmodule

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 22/08/17

END OF LECTURE 08 Lec ture 09: VERILOG

OPERATORS
PROF. INDRANIL SENGUPTA
DEPARTMENT OF COMPUTER SCIENCE AND
ENGINEERING

Hardware Modeling Using Verilog 43

Verilog Operators Examples:

Arithmetic Operators: Logical Operators: (done && ack)
! logical negation (a || b)
+ unary (sign) plus
– Examples: && logical AND ! (a && b)
unary (sign) minus
+ binary plus (add) – (b + c) || logical OR ((a > b) || (c
(a – b) + (c * d) ==0))
– binary minus (subtract)
(a + b) / (a – b) ((a > b) && !
* multiply (b any
> c))non-zero value is treated as
a%b • The value 0 is treated as logical FALSE while
/ divide
a ** 3 TRUE.
% modulus
• Logical operators return either 0 (FALSE) or 1 (TRUE).
** exponentiation

Hardware Modeling Using Verilog 45

Hardware Modeling Using Verilog 46

Relational Operators: Examples:

Bitwise Operators:
Examples: wire a, b, c, d, f1, f2, f3, f4;
!= not equal ~ bitwise NOT
== equal (a != b) & bitwise AND assign f1 = ~a | b;
>= greater or equal ((a + b) == (c – d)) | bitwise OR assign f2 = (a & b) | (b & c) | (c & a)
<= less or equal ((a > b) && (c < d)) ^ bitwise exclusive-OR assign f3 = a ^ b ^ c;
> greater (count <= 0) ~^ bitwise exclusive-NOR assign f4 = (a & ~b) | (b & c & ~d);
< less

Relational operators operate on numbers, and Bitwise operators operate on bits, and return a value that is also a bit.
return a Boolean value (true or false).

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Reduction operators accepts a single word operand and produce a single bit as
Examples:
output. Shift Operators:
• Operates on all the bits within the word. wire [15:0] data, target;
>> shift right
<< shift left assign target = data >> 3;
Examples:
Reduction Operators: >>> arithmetic shift right assign target = data >>> 2;
wire [3:0] a, b, c; wire f1, f2, f3;
& bitwise AND
assign a = 4’b0111;
| bitwise OR Examples:
~& bitwise NAND assign b = 4’b1100;
Conditional Operator: wire a, b, c;
~| bitwise NOR assign c = 4’b0100;
cond_expr ? true_expr : false_expr; wire [7:0] x, y, z;
^ bitwise exclusive-OR assign f1 = ^a;
~^ bitwise exclusive-NOR assign a = (b > c) ? b : c;
// gives a 1 assign z = (x == y) ? x+2 : x-2;
assign f2 = & (a ^ b); // gives a 0
assign f3Modeling
Hardware = ^a & ~^b; // gives a 1
Using Verilog 49
Hardware Modeling Using Verilog 50

Concatenation Operator: Joins together bits from two or more module operator_example (x, y, f1, f2);
comma-separated expressions. input x, y;
{…, …, …}
output f1, f2;
Replication Operator: Joins together n copies of an expression wire [9:0] x, y; wire [4:0] f1; wire
{n{m}} m, where n is a constant. f2;
assign f1 = x[4:0] & y[4:0];
Examples: f2 = x[2] | ~f1[3];
assign f = {a, b}; assign f2 = ~& x;
assign f = {a, 3’b101, b}; f1 = f2 ? x[9:5] :
assign f = {x[2], y[0], a}; assign x[4:0];
assign f = {2’b10,
3{2’b01}, x}; assign
Hardware Modeling Using Verilog endmod Hardware Modeling Using Verilog
51 52
ule

+ – ! ~ (unary)
// An 8-bit adder description
Operator **
module parallel_adder (sum, cout, in1, in2, cin); Precedence * / %
<< >> >>>
Precedence increases

input [7:0] in1, in2;

< <= > >=
input cin; • Operators on same line have the
== != === !==
output [7:0] sum; same precedence.
& ~&
output cout; • All operators associate left to
^ ~^
right in an expression, except ?:
| ~|
assign #20 {cout,sum} = in1 + in2 + cin; • Parentheses can be used to
&&
endmodule change the precedence.
||
?:

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9
 22/08/17

Some Points
• The presence of a ‘z’ or ‘x’ in a reg or wire being used in an arithmetic
expression results in the whole expression being unknown (‘x’).
• The logical operators (!, &&, | |) all evaluate to a 1-bit result (0, 1 or
x).
END OF LECTURE 09
• The relational operators (>, <, <=, >=, ~=, ==) also evaluate to a 1-bit
result (0 or 1).
• Boolean false is equivalent to 1’b0.
Boolean true is equivalent to 1’b1.

Hardware Modeling Using Verilog 55

Hardware Modeling Using Verilog 56

Example 1
• The structural hierarchical description of a 16-to-1 multiplexer.
a) Using pure behavioral modeling.
b) Structural modeling using 4-to-1 multiplexer specified using behavioral
Lec ture 10: VERILOG MODELING model.
EXAMPLES c) Make structural modeling of 4-to-1 multiplexer, using behavioral
modeling of 2-to-1 multiplexer.
PROF. INDRANIL SENGUPTA
DEPARTMENT OF COMPUTER SCIENCE AND d) Make structural gate-level modeling of 2-to-1 multiplexer, to have a
ENGINEERING
complete structural hierarchical description.

Hardware Modeling Using Verilog 58

module muxtest;
reg [15:0] A; reg [3:0] S; wire
Version 1: Using pure behavioral modeling F;

mux16to1 M (.in(A), .sel(S), .out(F));

module mux16to1 (in, sel, out); initial
input [15:0] in;
input [3:0] sel; begin 0 A=xxxx, S=x, F=x
output out; $dump 5 A=3f0a, S=0, F=0
fil 10 A=3f0a, S=1,
e F=1 15 A=3f0a,
assign out = in[sel]; ("m
endmodule S=6, F=0 20
ux1 A=3f0a, S=c, F=1
6to
1.v
Selects one of the input bits depending upon the value of “sel”. cd"
);
$dump
var
Hardware Modeling Using Verilog 59 s Hardware Modeling Using Verilog 60
(0,
mux
tes
t);
$monitor ($time," A=%h, S=%h, F=%b", A,S,F);
#5 A=16'h3f0a; S=4'h0;
#5 S=4'h1;
#5 S=4'h6;
#5 S=4'hc;
#5 $finish;
end
endmodule

10
 22/08/17

Version 2: Behavioral modeling of 4-to-1 MUX

Structural modeling of 16-to-1 MUX
module mux16to1 (in, sel, out);
module mux4to1 (in, sel, out); input [15:0] in;
input [3:0] in; input [3:0] sel;
input [1:0] sel; output out;
output out; wire [3:0] t;

assign out = in[sel]; mux4to1 M0

endmodule (in[3:0],sel[1:0
],t[0]);
mux4to1 M1
(in[7:4],sel[1:0
],t[1]);
mux4to1 M2
(in[11:8],sel[1:
Hardware Modeling Using Verilog 61
Hardware Modeling Using Verilog
0],t[2]); 62
mux4to1 M3 (in[15:12],sel[1:0],t[3]);
mux4to1 M4 (t,sel[3:2],out);
endmodule

in[3:0] M0 Version 3: Behavioral modeling of 2-to-1 MUX

t[0]
Structural modeling of 4-to-1 MUX
t[1] module mux4to1 (in, sel, out);
in[7:4] M1 module mux2to1 (in, sel, out); input [3:0] in;
out 16-to-1 multiplexer input [1:0] in; input [1:0] sel;
M4 using 4-to-1 input sel; output out;
multiplexers output out; wire [1:0] t;
in[11:8] M2
t[2] sel[3] sel[2] assign out = in[sel]; mux2to1 M0
endmodule (in[1:0],sel[0],
t[3] t[0]);
in[15:12] M3 mux2to1 M1 (in[3:2],sel[0],t[1]);
mux2to1 M2 (t,sel[1],out);
sel[1] sel[0] endmodule

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Version 4: Structural modeling of 2-to-1 MUX

module mux2to1 (in, sel, out);

input [1:0] in;
Point to note:
in[1:0] M0 input sel; • Same test bench can be used for all the
t[0]
out 4-to-1 multiplexer output out; versions.
M2 using 2-to-1 wire t1, t2,
t3; • The versions illustrate hierarchical
multiplexers
in[3:2] M1 t[1] refinement of design.
sel[1] NOT G1
(t1,sel);
sel[0] AND G2
(t2,in[0],t
1);
AND G3
(t3,in[1],s
Hardware Modeling Using Verilog el); Hardware Modeling Using Verilog
65 66
OR G4 (out,t2,t3);
endmodule

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END OF LECTURE 10 Lecture 11: VERILOG MODELING EXAMPLES

(contd.)
PROF. INDRANIL SENGUPTA
DEPARTMENT OF COMPUTER SCIENCE AND
ENGINEERING

Hardware Modeling Using Verilog 67

Example 2 module ALU (X, Y, Z, Sign, Zero, Carry, Parity,

Overflow); input [15:0] X, Y;
Version 1: Behavioral description of a 16-bit adder. output [15:0] Z;
output Sign, Zero, Carry, Parity, Overflow;
• Generation of status flags:
– Sign : whether the sum is negative or positive assign {Carry, Z} = X + Y; // 16-bit addition
– assign Sign = Z[15];
Zero : whether the sum is zero
assign Zero = ~|Z;
– Carry : whether there is a carry out of the last stage assign Parity = ~^Z;
– Parity : whether the number of 1’s in the sum is even or odd assign Overflow =
(X[15] & Y[15] &
– Overflow : whether the sum cannot fit in 16 bits
~Z[15]) |
(~X[
15
]
Hardware Modeling Using Verilog Hardware Modeling Using Verilog
69 & 70

~Y
[1
5]
&
Z[
15
])
;

endmodule

module alutest;
reg [15:0] X, Y; Simulation Output
wire [15:0] Z; wire S, ZR, CY, P, V;
ALU DUT (X, Y, Z, S, ZR, CY, P, V);
0 X=xxxx, Y=xxxx, Z=xxxx, S=x, Z=x, CY=x, P=x, V=x
initial 5 X=8fff, Y=8000, Z=0fff, S=0, Z=0, CY=1, P=1,
V=1 10 X=fffe, Y=0002, Z=0000, S=0, Z=1, CY=1,
begin
P=1, V=0 15 X=aaaa, Y=5555, Z=ffff, S=1, Z=0,
$dump
fil CY=0, P=1, V=0
e
("a
lu.
vcd
");
$du
mpv
ars
(0, Hardware Modeling Using Verilog Hardware Modeling Using Verilog
71 72
alu
tes
t);
$monitor ($time," X=%h, Y=%h, Z=%h, S=%b, Z=%b, CY=%b, P=%b,
V=%b", X, Y, Z, S, ZR, CY, P, V);
#5 X = 16'h8fff; Y = 16'h8000; #5
X = 16'hfffe; Y = 16'h0002;
#5 X = 16'hAAAA; Y = 16'h5555;
#5 $finish;
end
endmodule

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Version 2: Structural description of 16-bit adder using 4-bit adder

blocks (with ripple carry between blocks).
module ALU (X, Y, Z, Sign, Zero, Carry, Parity, Overflow);
input [15:0] X, Y;
output [15:0] Z;
output Sign, Zero, Carry, Parity, Overflow;
wire c[3:1];

assign Sign = Z[15];

assign Zero = ~|Z;
assign Parity = ~^Z;
assign Overflow = (X[15] & Y[15] & ~Z[15]) |
(~X[15] & ~Y[15] & Z[15]);
.. Contd.

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Hardware Modeling Using Verilog 74

adder4 A0
adder4 A1
(Z[3:0], c[1], X[3:0], Y[3:0], 1’b0);
(Z[7:4], c[2], X[7:4], Y[7:4], c[1]);
Version 3: Structural Modeling of Ripple Carry Adder
adder4 A2 (Z[11:8], c[3], X[11:8], Y[11:8], c[2]); module adder4 (S, cout, A, B, cin);
adder4 A3 (Z[15:12], Carry, X[15:12], Y[15:12], c[3]); input [3:0] A, B; input cin;
endmodule output [3:0] S; output
cout; wire c1,c2,c3;
Behavioral description of a 4-bit adder
fulladder FA0
module adder4 (S, cout, A, B, cin); (S[0],c1,A[0],B[0],cin);
input [3:0] A, B; input cin;
fulladder FA1
output [3:0] S; output
(S[1],c2,A[1],B[1],c1);
cout;
fulladder FA2
(S[2],c3,A[2],B[2],c2);
assign {cout,S} = A + B + fulladder FA3
cin; endmodule (S[3],cout,A[3],B[3],c3);
Hardware Modeling Using Verilog 75
Hardware Modeling Using Verilog 76
endmodule

Version 4: Structural Modeling of Carry Lookahead Adder

module fulladder (s, cout, a, b, c); a s1 module adder4 (S, cout, A, B, cin);
s b
input a, b, c;
output s, cout; input [3:0] A, B; input cin;
wire s1,c1,c2; output [3:0] S; output
cout; wire p0, g0, p1, g1, p2, g2,
xor G1 (s1,a,b), G2 (s,s1,c), p3, g3; wire c1, c2, c3;
G3 (cout,c2,c1); c2
assign p0 = A[0] ^ B[0], p1 = A[1] ^ B[1],
and G4 (c1,a,b), G5 (c2,s1,c); c c1 p2 = A[2] ^ B[2], p3 = A[3] ^ B[3];
endmodule
cout assign g0 = A[0] & B[0], g1 = A[1] & B[1],
g2 = A[2] & B[2], g3 = A[3] & B[3];

Contd…

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77

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assign c1 = g0 | (p0 & cin),

c2 = g1 | (p1 & g0) | (p1 & p0 & cin),
How does a Carry Look-ahead Adder work?
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 &
cin), cout = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1
& g0) |
• The propagation delay of an n-bit ripple carry order is
(p3 & p2 & p1 & p0 & cin); proportional to n.
– Due to the rippling effect of carry sequentially from one
assign S[0] = p0 ^ cin,
S[1] = p1 ^ stage to the next.
c1, S[2] = p2
^ c2, S[3] =
• One possible way to speedup the addition.
p3 ^ c3; – Generate the carry signals for the various stages in parallel.
– Time complexity reduces from O(n) to O(1).
endmodule
– Hardware complexity increases rapidly with n.

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Hardware Modeling Using Verilog 80

Unrolling the Recurrence

• Consider the i-th stage in the addition process.
• We define the carry generate and carry propagate
Ai ci+1 = g +i p ci i = g i+ p i (g i-1 + pi-1ci-1) = g i+ p gi i-1 + p ipi-1
functions as: Si i-1
Bi FA
c
gi = Ai.Bi
ci = gi + pigi-1 + pipi-1 (gi-2 + pi-2ci-2)
pi = A i Ⓒ B i ci+1 = g i + pi gi-1 + pi pi-1 gi-2 + pi i-1
p i-2
p i-2c = …..
• gi = 1 represents the condition when a carry is
generated in stage-i independent of the other stages. ci+1 = gi + pi.ci
• pi = 1 represents the condition when an input carry C i i-1 i i
will be propagated to the output carry ci+1. ci+1 = gi +  gk  pj + c0  pj
k=0 j=k+1 j=0

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Hardware Modeling Using Verilog 82

B3 A 3 B2 A 2 B1 A 1 B0
Generation of the Carry and Sum bits A0
c4 = g3 + g2p3 + g1p2p3 + g0p1p2p3 + c0p0p1p2p3 4 AND2 gates
3 AND3 gates gi and pi Generator
c3 = g2 + g1p2 + g0p1p2 + c0p0p1p2 2 AND4 gates
g3 p3 g2 p2 g1 p1 g0
c2 = g1 + g0p1 + c0p0p1 1 AND5 gate
p0
1 OR2, 1 OR3, 1 OR4
c1 = g0 + c0p0 4-bit Carry Look Ahead Circuit
and 1 OR5 gate
S0 = A0 Ⓒ B0 Ⓒ c0 = p0 Ⓒ c0 c3 c2 c1 c0
S1 = p1 Ⓒ c1 4 XOR2 gates
S2 = p2 Ⓒ c2 xor xor xor xor
S3 = p3 Ⓒ c3 c4
S3 S2 S1 S0

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END OF LECTURE 11

Hardware Modeling Using Verilog 85

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