2019 IEEE International Conference of Intelligent Applied Systems on Engineering (IEEE ICIASE 2019)

Design Procedure for a Folded-Cascode and Class AB Two-Stage

CMOS Operational Amplifier
Hongyi Wang1,a, Zeyu Qiao1,b, Yanchao Xu1,c and Guohe Zhang1,d
1
School of Microelectronics, Xi'an Jiaotong University
No.28 Xianning West Road
Xi’an, Shaanxi, China
E-mail: wanghongyi@mail.xjtu.edu.cn

Abstract requirements of the operational amplifier. In addition, some

common operational amplifier structures such as symmetrical
This paper presents a low-noise two-stage operation op amps, telescopic op amps, and three-stage op amps have
amplifier design procedure based on standard CMOS process. also been studied by designers in [10]-[12].
Unlike the previous researches that depict the design flow With the rapid development of integrated circuit technology,
based on some simple circuit topologies for simplicity, this the power supply voltage of the chip is continuously decreasing.
paper adopts the folded cascade input and Class AB output To ensure adequate dynamic range, op amps with rail-to-rail
two-stage operational amplifier that is more admitted by input and output capabilities are becoming a design trend. As
academia and widely used into industry. This presented one of its implementations, the circuit architecture proposed in
procedure begins with the key noise requirement to firstly [13] is shown in Fig.1. It combining the folded-cascode input
determine the input difference pair whose transconductance is stage and the class AB output stage becomes a common basic
the most important parameter related to other electrical architecture. This paper aims to derive a design flow based on
characters. Then the expressions and relationships of other this architecture.
parameters (such as slew rate, bandwidth, gain, phase margin, The basic equations of the op amp will be shown in part Ⅱ,
power consumption and signal swing) are derived under the including the relationship among each key parameters ，
constraint of noise requirement. Besides that, all sizes of transistor size and the bias current. The complete design flow
devices are confirmed considering chip area, matching relation starting from the noise parameter is shown in part Ⅲ. The
and layout. The low noise amplifier under the guidance of this component value and the comparison between target value and
proposed design procedure is implemented on a standard simulation results are shown in part Ⅳ. The partial test results
0.18μm CMOS process. The measured results and simulation
is shown in part Ⅴ. Part Ⅵ is summary of the whole article.
are closed agree with the expect results. So this design
procedure offers designers an efficient way from electrical
Ⅱ. Basic Op amp Equations
characters to key devices sizes based on the common operation
amplifier circuit.
Fig. 1 shows a two-stage op amp structure with rail-to-rail
input and output capability. The first stage consists of a folded-
Key words: design procedure, operational amplifiers, low
cascade structure, and the rail-to-rail input is achieved by
noise and CMOS analog integrated circuits
paralleling the NMOS differential pair with the PMOS
differential pair. The second stage is the class AB output stage,
Ⅰ. Introduction
and the gates of the two output transistors change in the same
phase to produce strong driving capability. The bias currents of
CMOS operational amplifiers (op amp) are fundamental
M26 and M27 are proportional to the currents of M18 and M19
parts in analog and mixed-signal circuits. Op amp designers
by matching the size of the transistors. The stability is ensured
must make the tradeoff between numerous electrical
by two Miller capacitances on which the signal passes through
characteristics, e.g., noise, output swing, power consumption,
the cascode transistor thus cutting off the feed forward path and
stability, gain, band width, slew rate, short-circuit current and
eliminating the zero point of the right half plane.
so on. Therefore, it is necessary to derive a design procedure
Neglecting the channel length modulation effect and other
based on a specific architecture.
secondary effects, the current and transconductance expres-
As early as the end of the 20th century, scholars began to
sions of the transistors operating in the saturation region can be
study the design methodology of the op amp. The papers can be
obtained as follows:
divided into three categories according to the researched op
amp structure. The differential pair with active current mirror 1 W
n,pCox Veff2
ID  (1)
as the first-stage, common-source amplifier as the second-stage 2 L
is widely used to derive the design method. According to the
design flow mentioned in [1]-[4], the result can be matched
W 2I D W
g m n,pCox V
 eff  2 I D n,pCox (2)
with the design goal. And folded-cascode op amps were also L Veff L
widely studied as common circuit structures. The design For NMOS, Veff =VGS  VTH，N . For PMOS, Veff =VSG  VTH，P
methods for the fully differential folded-cascode circuit
structure are proposed in [5]-[9]. The width to length ratio of
the corresponding transistor can be calculated according to the A. Input-Referred Thermal Noise Spectral Density

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 2019 IEEE International Conference of Intelligent Applied Systems on Engineering (IEEE ICIASE 2019)

The noise generated by the common gate transistor is ignored shown in Fig. 1 is
at low frequencies. Besides, the noise generated by the second
stage divided by the gain is too small to be ignored. In order to
Vn,out 2 1  4g 4g 
Vn,in 2  2 2
4kT 2  m16,17  m9,10  (3)
simplify the design process, only the influence of the g m1,2 Rout1 g m1,2  3 3 
transistor’s thermal noise is considered. The input transistors
Due to the matching of the circuit, the following equation can
and the common source transistors contribute the most noise.
be obtained:
When the common mode level at Vdd/2, the P-type input
transistors operates and the N-type input transistors are turned gm1,2  gm3,4 =gm9,10 =gm16,17 (4)
off. The input-referred noise spectral density of the op amp
VDD

Ib7
M28 M5 M6 M9 M10 M18

M19 Cc
1

Ib3 Ib1
M11 M12 M20 M26
Vb1

Ib8 M24
Vin- M1 M2 Vin+ M13 Vout
M3 M4
Ib6 M25

Vb2
Ib4 Ib2 M14 M15 M23
M27 CL RL

Cc
M22
2

M29 M7 M8 M16 M17 M21

Ib5

Fig.1 Schematic of the two-stage OTA.

From (3) and (4), we obtain C. Slew Rate
32kT For the circuit shown in Fig. 1, load capacitance (external
g m1,2  (5) slew rate) and compensation capacitance (Internal slew rate)
3Vn,in 2 effects the SR. Because the class AB structure of output stage,
B. Gain and Bandwidth output driving current can reach up to tens of mA, so the
The dc gain of the op amp is influence of CL is negligible. Then the expression of SR can be
Av Av1 Av2 =  g m1,2 Rout1,2    g m27 RL 
obtained as follows:

(6) I b1 I b2
 g m1,2 g m12 rO12 rO10 g m27 RL SR =  (11)
Cc1 Cc2
When the load resistance is a fixed value, the second-stage
gain （ 10dB-20dB ） is allocated according to the gain D. Output Short-circuit Current
requirement, so the gm of output transistors is obtained Put the op amp in an open loop state, let the difference
Av2 voltage across the input be VDD/2 and connect the output to a
g m 26,27  (7) fixed level such as VDD /2. Under this extreme conditions, the
RL
op amp can output exceeding 100 mA current, which is called
The miller capacitance pushes the pole at the first stage the output short-circuit current.
output node as main pole and the secondary pole is generated at
V VDD W
the output node. The poles and unity gain bandwidth ISC = n,pCox （VGS  VTH） (12)
expressions for the op amp are as follows: Ron 2 L
1
p1  (8)
E. Power Consumption and Quiescent Current
2 g m12 rO12 rO10 g m27 RLCc1
For the op amp, the typical operating voltage is 5V, so the
1 total quiescent current can be obtained according to the power
p2  (9)
RLCL consumption. The specific expression is as follows:
g P
I tot = (13)
u  p1  Av  m1,2 (10) VDD
2Cc1
Before the total current is distributed, the matching rela-
tionship of the transistors should be clarified first. For the

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 2019 IEEE International Conference of Intelligent Applied Systems on Engineering (IEEE ICIASE 2019)

structure shown in Fig. 1, in order to ensure that the slew rate of 2

g m27
W 
positive step and negative step are same, we have   =
I D1,2 =I D3,4 =I D5,6 =I D7,8 =I D9,10 =I D16,17 (14)  L 27 2 I D27 pCox
(27)
The two bias currents Ib3 and Ib4 are the mirror source of ID1,2 , Av2
=
according to experience, we have 2  P / V  13I b1 / 6  4 I D18  pCox RL
I D1,2 =6I b3  6I b4 (15)
The output stage transistor (M26, M27) has a match with its Ⅳ Simulation Results
bias circuit (M18-M 20, M20-M 23): The low noise amplifier under the guidance of this proposed
VGS 26 =VGS 18 (16) design procedure is implemented on a standard 0.18μm CMOS
process. The related process parameters are shown in Table Ⅰ.
VGS 24 =VGS 19 (17)
TABLEⅠ
From (1), (16) and (17), we obtain PROCESS PARAMETERS (0.18 CMOS PROCESS)
I D 26 W / L 26 Process parameter NMOS PMOS
= (18) VTH0(V) 0.726 -0.758
I D 18 W / L 18 tox(m) 13.275  10-9 13.791  10-9
μ(cm2/V/s) 394.444 254.444
I D 24 W / L 24
= (19)
I D 19 W / L 19 Verify the feasibility of this design procedure by designing a
low noise op amp. The significant specifications are shown in
According to (13), (14) and (15), the output current is
TableⅡ, the target value in the first column and the simulation
13 result in the second column, in the case of supply voltage is
I D26，27 =I tot  I b1  4 I D 18 (20)
6 5V,load resistance is 600 Ω and load capacitance is 10pF.
According to the design experience, the output stage current
accounts for 30% to 40% of the total current. So we can TABLE Ⅱ
calculate the current ratio of ID26, 27 and ID 18, thus derive the MAIN PARAMETERS OF THE LOW NOISE CMOS OP AMP
output current. Parameter Target Simulated
DC gain : Avo(dB) >80 89
Ⅲ Design Procedure Unity-gain bandwidth: fu (MHz) 15 17
Slew rate: SR(V/μs) 9 9
A design step for the two-stage op amp (Fig. 1) can be Input white noise: Vn,in 2 (nV/ Hz ) 9@10kHz 8.5@10kHz
constructed as follows. Input offset voltage (mV) 1 0.5
Step 1) From (4) and (5), we can obtain Phase margin: MΦ (°) 60 60
32kT Common mode range: CMR(V) rail-to-rail rail-to-rail
g m1,2 =g m3,4 =g m5,6 =g m7,8 =g m9,10 =g m16,17 = (21) Output Swing: OS(V) rail-to-rail rail-to-rail
3Vn,in 2 Quiescent current: IQ(μA) 800 790
Step 2) Using (10) and (21) to calculate Cc1 Common mode rejection ratio: >75 79
g m1,2 32kT CMRR (dB)
Cc1  = (22)
2u 6u Vn,in 2 TABLE Ⅲ
Step 3) Calculate Ib1, Ib2 from (11) and (22) COMPONENT VALUE OF THE OP AMP
Parameter Value Unit
32kT  SR
I b1 =I b2 =SR  Cc1 = (23) (W/L)1,2 800/3 μm/μm
6u Vn,in 2 (W/L)3,4 640/6 μm/μm
(W/L)5,6 324/2 μm/μm
Step 4) From (2), (21) and (23), we can calculate (W/L)1, 2
2
(W/L)7,8 324/2 μm/μm
W  g m1,2 (W/L)9,10 324/2 μm/μm
  = (24) (W/L)16,17 324/2 μm/μm
 L 1,2 I b1,2 pCox (W/L)26 640/0.8 μm/μm
Step 5) From (2), (14) and (21), we can calculate (W/L)5, 6, (W/L)27 240/0.8 μm/μm
(W/L)9, 10, (W/L)3, 4, (W/L)7, 8 and (W/L)16, 17 Ib1, Ib2 180 μA
2
W  W  g m1,2 Ib3, Ib4 15 μA
  =   = (25) Ib5, Ib6, Ib7, Ib8 20 μA
 L 5,6  L 9,10 I b1,2 pCox ID26,27 320 μA
2
g m1,2 Cc1, Cc2 20 pF
W  W  W 
  =  =  = (26) According to the proposed design procedure, we can derive
 L 3,4  L 7,8  L 16,17 I b1,2 n Cox the values of transistor aspect ratios, bias current,
Step 6) Calculate (W/L)27 from (7) , (13) and (20) compensation capacitor shown in Table Ⅲ. As can be seen
from Table Ⅲ, the input transistor is large in size for reducing

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 2019 IEEE International Conference of Intelligent Applied Systems on Engineering (IEEE ICIASE 2019)

the influence of 1/f noise. The output transistor size is also large, wave as input signal to test SR. As shown in Fig.3 and Fig.4,
in order to provide a driving current over 100 mA and provide a SR+=8.9V/μs, SR- =9.1V/μs, meeting the target value.
larger gm.
Simulate the op amp using the circuit structure shown in Fig. Ⅵ Summary
1 of which parameter referring to the values in Table Ⅲ. The The design procedure for a folded-cascode and class AB
simulation results are shown in Table Ⅱ. Comparing the two two-Stage CMOS op amp has been presented. Simulation
column values we can find that the simulation results meet the results confirm that the proposed design step is closely in
requirements on the whole, which verify the practicality of the agreement with the target value. Besides, the test results give
design method. further verification of the practicality of the design procedure
which have important reference value for analog IC designers.
Ⅴ Test Results
Acknowledgement
The low noise amplifier under the guidance of this proposed This research was partly supported by the Core Electronic
design procedure is implemented on a standard 0.18μm CMOS Devices, High-end General Chips and Basic Software Products
process. The chip area is 0.32mm2 and the photo is shown in Projects of China (2017ZX01030204)
Fig.2.
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