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Serial No. of Booklet :

Code No. :1286

B. C. A. (Second Semester) Examination, 2022-23
AFFIX PRESCRIBED
RUBBER STAMP
Paper Second
DIGITAL ELECTRONICS AND
COMPUTER ORGANIZATION (MAJOR)
Course Code-BCA-202(T)
In Figures (sioi ):
Roll No.
2l3402&3L o4

In Words (grszi ):

Date:33..
Time : 2 Hrs. Signature of Invigilator
Max. Marks : 75

Important Instructions':
1 The candidate willwrite hisher Roll Number 1.
only at the places provided for, i. e., on the
cover page and on the OMR answer sheet at
the end and nowhere else.

2 Immediately on receipt of the question 2

booklet, the candidate should check up the
booklet and ensure that it contains all the
pages and that no question is missing. If the
candidate finds any discrepancy in the
question booklet, heshe should report the
invigilator within 10 minutes of the issue of
this booklet and a fresh question booklet
without any discrepancy is obtained.
3. No second question booklet shall be given to a 3.
candidate under any circumstances after 10
minutes. The candidate should be careful in
handling the question booklet and in filling the
OMR answer sheet given separately with this
booklet.

& (Contd. on the last page / 3 fa sfH Y. )

1. What is Digital Electronics ? 5. What will be the output from aD flip
(A) Field of electronics involving flop if D=l and the clock is low ?
the study of digital signal \(A) No change
(B) Engineering of devices that (B) Toggle between 0and 1
digital signal (C) 0
(C) Engineering of devices that (D) 1
produce digital signal 6. What input should be given to "S"
D)A of the mentioned when SR flip-flop is converted to JK
flip-flop ?
2. Which of the following is a type of
digital logic circuit ? (A) K.Q
(B) K.Q
(A) Combinational logic circuits
(C) J.Q
(B) Sequential logic circuits
Both (A) and (B)
7 What value is to be considered for a
(D) None of the mentioned
*don't care condition" ?
3. Which gates in Digital Circuits are (A) 0
required to convert aNOR-based SR (B) 1
latch to an SR flip-flop ? (C Efther 0or 1
(A)Fwo 2 input AND gates (D Any number except 0and 1
(B) Two 3 input AND gates 8 What will be the frequency of the
(C) Two 2 input OR gates output from a JK flip-flop, when
(D) Two 3 input OR gates J =1, K = 1and a clock with pulse
waveform given ?
4. Which of the following options (A) Half the frequency of clock
represent the synchronous control input
inputs in an S-R flip-flop ? (B) Equal to the frequency of clock
(A) S input
(C) Twice the frequency of clock
(B) R
input
(C) Clock
(D) Independent of the frequency of
\D BothS and R clock input
1286 / & (3) P. T.O.
 4n2.

9 In Digital Circuits, which of the 13. How many cycles of addition and 16. What determines the output from the
19 The decimal equivalent of the binary
following options represent the shifting in a 4-bit multiplier are combinational logic circuit in Digital number (1011; is
synchronous control inputs in aT flip required to perform multiplication Electronics ?
flop ?
using the shift method ? (A) Input signals from the past
(B) (12)
condition
(B) 0 (A) 1 (C) (11.11)
C) Clock (B, Input signals at the present (D) (9)
B} 2
(D) 1 moment
C) 4 20. The decimal equivalent of the octal
Input signals from both past and
10. How many errors can the Digital
(D) 8 number (645)g is
Electronics parity method find in a present

single word ?
|4 What kind of operation occurs in a (D) Input signals expected in future (A) (450)10
6 (49 Single error (B) (451)0
J-K flip-flop when both inputs J and 17. Any signed negative binary number is
B) Double error
K are equal to 1? recognised by its
\c t421)lo
(C) Triple error
(D) (501)10
(D) Multiple errors (A) Preset operation (A) MSB

11. What is the group of ls present in 8 (B) Reset operation (B) LSB 21. The quantity of double word is
cells of a K-map called ? (C) Byte
(C) Clear operation
(A) Pair (D) Nibble (A) 16 bits
) Toggle operation
(B) Quad B) 32 bits
(e) Octet 18. If the decimal number is a fraction,
15. Which of the following options (C) 4 bits
(D) Octave then its binary equivalent is obtained
represent the correct reduction
of (D) 8 bits
by the number continuously
12. Which of these flip-flops cannot be
XYZ + XYZ ?
U used to construct a serial shift by 2. 22. Latch is a device with
0
register ? (A) 0 (A) Dividing (A) One stable state

(A) D flip-flop (B) YZ (B Multiplying (B) Two stable states

(B) SR flip-flop (C) Adding (C) Three stable states

(C) X+X
) T flip-flop (D) Subtracting (D) Infinite stable states
(D) 2YZ
(D) JK flip- flop P. T. O.
1286 /& (5)
1286/ &
(4)

UI Me issue of
U a
wLNout any discrepancyfresh
is
question booklet
 23. why latches are called memory 27% The SR latch consists of 31. When both inputs of a J-K flip-flop 35. The basic latch consists of
devices?
(A) Iinput cycle, the output will 1A)Two inverters
(A) It has capability to store 8 bits of (A) Be invalid
(B)2 inputs (B) Two comparators
data.
(B) Change (C) Two amplifiers
(C) 3 inputs
(B) It has internal memory of 4 bits. (C) Not change
(D) 4 inputs (D) Two adders
It can store one bit of data. D) Toggle
(D) It can store infinite amount of 28.
36. In S-R flip-flop, if Q = 0 the output is
The NAND tatch works when both
32. The logic circuits whose outputs at said to be
data.
inputs are any instant of time depends only on
(A)Set
24. Two stable states of latches (A) 1 the present input but also on the past
B) Reset
are (B)» 0 outputs are called
(C) Previous state
(A) Astable and Monostable (C) Inverted (A) Combinational circuits
(D) Current state
(B) Low input and High output (D) Don't cares lB Sequentialcircuits
(C) Latches
C) High output and Low output 37. The logical sum of two or more
29. The first step of the analysis (D) Flip-flops
(D) Low output and High input logical product terms is called
procedure of SR latch is to
33. How many types of sequential circuits
How many types of latches
(A) label inputs (Ware there ? (A) SOP
are there ?
(B) label outputs (42 (B) POS
A) 4 (C) label states
(B) 3 (C) OR operation
(B) 3 (D) label tables (C) 4 (D) NAND operation
(C)' 2
(D) 5
(D) 5 30. When a high is applied to the set line
38. The expression Y = AB + BC + AC
of an SR latch. then 34. The sequential circuit also
shows the operation.
26. The full form of SR is called
(A) Qoutput goes high (A) EX-OR
(A) System Rated (A) Flip-flop
B) Set Reset (B) Q'output goes high (B) Latch
(B) SOP

(C) Qoutput goes low (C) POS

(C) Set Ready (C) Strobe
(D) Set Rated (D) Both Qand Qgo high (D) NOR
(D) Adder
1286 / & P. T. 0.
286 / & (6) (7)
 39. The expression Y = (A + B),(B + C) 43. Maxterm is the sum of 51. A three digit decimal number requires
of 47. Perform binary subtraction : 101111
for representation in the
(C+ A) shows the operation. the corresponding Minterm with its 010101 =?
conventional BCD format.
(A) AND literal complemented.
(A) 100100 (A) 3 bits
BPOS L4Tems (B) 010101 (B) 6 bits
(C) SOP (B) Words L(C 12 bits
(D) NAND (C) Numbers (D) 011001 (D) 24 bits
(D) Nibble
40. The canonical sum of product form 48. Binary coded decimal 52. A Karnaugh map (K-map) is an
of the function y (A, B) = A4+ B 44. Canonical form is a unique way of ( combination of abstract form of diagram
()
is
representing (A) Two binary digits organized as a matrix of squares.
(A) AB + BB +A'A (B) Three binary digits (AS Venn
(A) SOP
B AB+AB' + A'B (B) Minterm ) Four binary digits (B) Cycle
(C) BA + BA' +A'B' (D) Five binary digits (C) Block
(CBoolean expressions
(D) AB'+ A'B + A'B' (D) Triangular
(D) POS 49 The decimal number 10 is represented
41. A variable on its own or in its in its BCD form as There are cells in a 4
45. There are Minterms for
complemented form is known as (A) 10100000 variable K-map.
3variables (a, b, c).
(B) 01010111 2 R
(A) 12
(A) 0
(A) Product Term (C) 00010000 B)-16
(B) 2 (C) 18
B Literal (D) 00101011
(C) Sum Term (D) 8
(D) 1 50. When numbers, letters or words are
(D) Word
represented by a special group 54. The K-map based Boolean reduction
42. Canonical form is a unique way of 46. Perform binary addition : 101101 + is based on the following Unifying
of symbols, this process is
011011 =? Theorem:
( representing called

(A) SOP (A) 011010 A+A'=1

(A) Decoding
(B) Minterm (B) 1010100 (A) Impact
(B Encoding
B) Non-impact
(Boolean expressions (C) 101110 (C) Digitizing
(D) POS
(C) Force
(D) 1001000 (D) Inverting
(D) Complementarity
1286 / & 1286 /& P. T. O.
(8) (9)
 In case of XOR/XNOR simplification 66. Half adders have a major limitation in
59. It should be kept in mind that don't we have to look for the that they cannot
55. Each product term of agroup, w'.x.y'
following : (A) Accept a carry bit from a present
and w.y, represents the care terms should be used along
in that group. with the terms that are present
(A) Diagonal Adjacencies stage
(B) Offset Adjacencies (B) Accept a carry bit from a next
(A) Input in
(B) POS
(C) Straight Adjacencies stage

OSum-of- Minterms (A) Minterms AD Both Diagonal and Offset

(C) Accept a carry bit from a
Adjacencies previous stage
(D) Sum-of-Maxterms (B) Expressions
(C) K-map 63 Entries is known as (D) Accept a carry bit from the
56. Product-of-Sums expressions can be
implemented using (D) Latches mapping. following stages
(A)) 2-level OR-AND logic circuits ((A) Diagonal 67. The difference between half adder and
60. Using tie transformation method you
(B) 2-level NOR logic circuits (B) Sraight full adder is
(C) 2-level XOR logic circuits can realize any POS realization of (C) K
LB) Both 2-level OR-AND and NOR OR-AND with only: (D) Boolean
(A) Half adder has two inputs while
logic circuits full adder has four inputs
(A), XOR
Total number of inputs in a half adder (B) Half adder has one output while
57. Each group of adjacent Minterms (B) NAND is
full adder has two outputs
(group size in powers of twos)
correspornds to a possible product (C).AND A) 2 (C) Half adder has two inputs while
term of the given (B) 3
LD)NOR full adder has three inputs
(A) Function (C) 4
(D) All of the mentioned
(B) Value 61. There are many situations in logic (D) 1
(C) Set design in which simplification of 68. If A, B and C are the inputs of a full
(D) Word 65. If A and B are the inputs of a adder, then the Sum is given
logic expression is possible in terms
half adder, then the carry is given
58. Don't care conditions can be used of XOR and. operations. by
by
for simplifying Boolean expressions (A) A AND B ANDC
in (A) X-NOR A) A AND B
(B) A OR B ANDC
(A) Registers (B) XOR (B) A OR B
(B) Terms (C) A XOR B (C AXOR BXORC
(C) NOR
C K-maps (D) A EX-NOR B (D) A OR B OR C
(D) NAND
(D) Latches P. T.O.
1286 / & (11)
1286 /& (10)
 69. How many AND, OR and EXOR Let the input of a subtractor is A and 77. The basic building blocks of the 81 Which of the examples below
73 arithmetic unit in a digital computers
gates are required for the B, then what the output will be if expresses the commutative law of
are
configuration of full adder ? A =B? multiplication ?
(A) Subtractors
(A) 1, 2, 2 (A) 0 (A) A+ B= B+ A
(B) Adders
B2,1, 2 (B) 1 (C) Multiplexer
(B) A· B= B+A
(C) 3, 1, 2 (D) Comparator (C) A·(BC) =(A·B)·C
(D) 4, 0, 1 (D) B D_A- B=B·A
78. All logic operations can be obtained
70. Half subtractor is used to perform by means of The Boolean expression Y = (ABY is
74. Let A and B is the input of a 82
subtraction of subtractor, then the output will (A) AND and NAND operations logically equivalent to what single
4 2bits be (B) OR and NOR operations gate ?
(C) OR and NOT operations
(B) 3bits \(A) A XOR B KAJ-NAND
\DY NAND and NOR operations
(C) 4 bits (B) A AND B (B) NOR

(D) 5bits (C) A OR B 79. The design of an ALU is based (C) AND
) on
(A) A EXNOR B (D) OR
71. For subtracting 1from 0, we use to (A) Sequential logic
take a from neighbouring 75. Full subtractor is used to perform (B) Combinational logic 83 Which of the following expresions is
bits. subtraction of
(C) Multiplexing
) in the sum-of-products form ?
(D) De-multiplexing
(A) Carry (A) 2 bits (A) (A + B)(C +D)
80. Which statement below best describes
B) Borow B 3bits (B) (A * B) (C* (D)
a Karnaugh map ?
(C) input (C) 4bits (C) A*B* (CD)
(A) It is simply a rearranged truth
(D) Output (D) 8 bits table (DY A *B+C*D
(B) The Karnaugh map eliminates
72. How many outputs are required for 76. The output of a full subtractor is same 84. Which of the following expressions is
the need for using NND and
the implementation ofa subtractor ? as
NOR gates. in the product of-sums form ?
(A) 1 (A) Halfadder (C) Variable complements can be
eliminated by using Karnaugh (4A +(B),(C +D)
B) 2 Y(B)-Full adder (B) (AB) (CD)
maps.
(C) 3 (C) Half subtractor (C) AB (CD)
(D) A Karnaugh map can be used to
(D) 4 (D) Decoder (D) AB + CD
replace Boolean rules.
86 / & (12) 1286 /& P. T.O.
(13 )
 85. Which of the following logic 88._ The D flip-flop has input. 92. The instruction used in a program for 97. ROM consist of
expressions represents the logic O executing them is stored in (A) NOR and OR arrays
diagram shown ? (B) 2 the (B) NAND and NOR arrays
(C) 3 (A) CPU KONAND and OR arrays
(D) 4 (B) Control Unit (D) NOR and AND arrays

x 89. The D flip-flop has l(c, Memory 98 The full form of PROM is
(D) Microprocessor (A) Previous Read Only Memory
outputloutputs.
(B) Programmable Read Out
93. A flip-flop stores Memory
(A) X= AB' + A'B ( (A) 10 bit of information
(B) 3 (C)Programmable Read Only
(B) X= (AB) + AB (B) bit of information Memory
(C) 4
(C) X= (AB' + AB' (C) 2 bit of information (D) Previous Read Out Memory
(D) 1
D)X=AB + AB (D) 3 bit of information 99. The full form of EPROM

86. The device shown here is most likely : 90. AD flip-flop can be constructed from 0 is
94. A register is able to hold
V an flip-lop. (A) Easy Programmable Read Only
(A) Data
Memory
LaS-R (B) Word
D (B)Erâsable Programmable Read
(B) J-K (C) Nibble Only Memory
So
S1
(D) Both Data and Word (C) Eradicate Programmable Read
(C) T
Only Memory
(D) S-K 95. A ROM is defined as (D) Easy Programmable Read Out
(A) Comparator (A) Read Out Memory Memory
(B) Multiplexer, 91. Memory is a/an
(B) Read Once Memory 100. ASIC stands for
(C) Inverter (A) Device to collect data from other
LC) Read Only Memory (A) Application Special Integrated
D Demultiplexer, computer
(D) Read One Memory Circuits
(B) Block of data to keep data (B) Applied Special Integrated
87. In Dflip-flop, Dstands for 96. The full form of ROM is
(A) Distant
separately Circuits
(A) Read Outside Memory j(C)_ Application Specific Integrated
BY Data L(C Tndispensable part of computer
(B) Read Out Memory Circuits
(C) Desired (D) Device to connect through all (C) Read Only Memory (D) Applied Specific Integrated
(D) Delay over the world Circuits
(D) Read One Memory
286 / & (14) P. T.O.
1286 / & (15)

ulu renort t