Digital Systems1

Digital Systems
1. Analog signals are (continuous, discrete).

2. The operation of a digital circuit generally considered to be non-linear. (T or F).
3. The exact value of an input voltage is critical for a digital circuit. (T or F).
4. A graph that shows how one or more digital signals change with time is called a _____________.
5. What is the weight of the MSB of a 16-bit number?
6. How many bits are required to count up to decimal 1 million?
7. What range of decimal values can be represented by a 3-digit hex number?
8. How many bits are required to represent an 8-digit decimal number in BCD?
9. How many bytes are in a 32-bit string?
10. What is the largest decimal value that can be represented in binary using two bytes?
11. How many bytes are needed to represent the decimal value 8,46,569 in BCD?
12. Attach an even parity bit to the BCD code for decimal 78.
13. What logical level should be applied to the second input of a two input AND gate if the logic signal at the first
input is to be inhibited (prevented) from reaching the output?
14. Suppose a 3variable truth table has a HIGH output for these input conditions : 000, 010, 100 and 110. What is the
SOP?
15. How many fundamental products are there for two variables? How many for three variables?
16. How many entries are there on a 4-variable k-map?

17. On a k-map, two adjacent 1s are called a ________________
18. On a k-map, an octet contains how many 1s ?
19. Suppose a truth table has a low output for the first three input conditions : 000, 001, and 010. If all other outputs
are HIGH, what is the POS?
20. Write the SOP expressions for a circuit with four inputs and an output that is to be HIGH only when input A is
LOW at the same time that exactly two other inputs are LOW.
21. What is the output of an XNOR gate when a logic signal and its exact inverse are connected to its input?
Page 1 of 5
22. A device is needed to indicate when two LOW levels occur simultaneously on its inputs and to produce a HIGH
output as an indication. Specify the device.
23. The most suitable gate for comparing two bits is ________________________
24. Which of the following gates can be used an inverter?
a) AND
b) OR
c) XOR
d) None of the above
25. Which of the following gates cannot be used as an inverter

a) NAND
b) AND
c) NOR
d) XNOR
26. The Boolean expression A B C is a

a) sum term
b) literal term
c) product term d) complemented term
27. The Boolean expression AB CD is a

a) sum term
b) product term c) literal term
d) always 1
28. An example of a SOP expression is

a) A( B C ) AC
b) ( A B)( A B C )
c) AB AB ABC
d) Both answers (a)
and (b)
29. An example of a POS expression is
a) A B C
b) A( B C ) AC
c) ( A B )( A B C )
d) Both answers (a) and (b)
30. On a K-map grouping 1s produces

a) SOP expression
b) dont care condition c) POS expression
d) AND-OR Logic
31. When using dual symbols in a logic diagram

(a) bubble outputs are connected to bubble inputs
(b) the NAND symbols produce the AND operations.
(c) the positive OR symbols produce OR operations (d) all of these answers are true.
(e) none of these answers are true.
32. All Boolean expressions can be implemented with
(a) NAND gates only
(b) NOR gates only
(c) Combinations of NAND and NOR gates
(d) Combinations of AND,OR and inverter gates
(e) Any of these

33. An example of a data storage device is
(a) logic gate
(b) flip-flop
(c) comparator
(d) register
(e) both answers (b) and (d)
34. If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what are the inputs?
(a) A3A2A1A0 = 1010
(b) A3A2A1A0 = 1100
(c) A3A2A1A0 = 1110
(d) A3A2A1A0=0100
(c) multiplexers
(d) encoders
35. Data selectors are basically same as

(a) decoders
(b) de-multiplexers
36. A circuit with many inputs but only one output is called a __________________
37. A logic circuit with one input and many outputs is called a _________________
38. If an S-R latch has a 1 on S input and a 0 on R input and then S input goes to 0, the latch will be
(a) set
(b) reset
(c) invalid
Page 2 of 5
(d) clear
39. The invalid state of an S-R latch occurs when

(a) S=1, R=0
(b) S=0, R=1
(c) S=1, R=1
(d) S=0, R=0
40. For a gated D latch, the Q output always equals the D input
(a) before the enable pulse
(b) during the enable pulse
(c) immediately after the enable pulse
(d) answers (b) and (c)
41. Like the latch, the flip-flop belongs to a category of logic circuits known as
a) monostable multivibrators
b) bistable multivibrators
c) astable multivibrators
d) one shots
42. The purpose of the clock input to a flip-flop is to

a)
clear the device
b) set the device
c) always cause the output to change states
d) cause the output assume a state dependent on the controlling (S-R,J-K, or ) inputs.
43. For an edge-triggered flip-flop,
a) A change in the state of the flip-flop can occur only at a clock pulse edge
b) The state that the flip-flop goes to depend on the D input
c) The output follows the input at each clock pulse
d) All of these answer
44. A feature that distinguishes the J-K flip-flop from the S-R flip-flop is the
a) toggle condition
b) preset input
c) type of clock
d) clear input
J=0, K=0
d) J=0, K=1
45. A flip-flop is in the toggle condition when

a) J=1, K=0
b) J=1, K=1
c)
46. A J-K flip-flop with J=1 and K=1 has a 10 kHz clock input. The Q output is
a) constantly HIGH
b) constantly LOW
c) a 10 kHz square wave
d) a 5 kHz sq. wave
47. Asynchronous counters are known as

a) ripple counters
b) multiple clock counters
c) decade counters
d) modulus counters
48. An asynchronous counter differs from a synchronous counter in

a) the number of states in its sequence
b) the method of clocking
c) the type of flip-flops used
d) the value of the modulus
49. The modulus of a counter is

a) the number of flip-flops
b) the actual number of states in its sequence
c) the number of times it recycles in a second

d) the maximum possible number of states
50. A 4-bit binary counter has a maximum modulus of
a)
16
b) 32
c) 8
d) 4
51. A modulus-12 counter must have

a) 12 flip-flops
b) 3 flip-flops c) 4 flip-flops
d) synchronous clocking
52. Which one of the following is an example of a counter with a truncated modulus?
a) Modulus 8
b) Modulus 14
c) Modulus 16
Page 3 of 5
d) Modulus 32
53. A 4-bit ripple counter consists of flip-flops the each have a propagation delay from clock to Q output of 12 ns.
For the counter to recycle from 1111 to 0000, it takes a total of
a)
12ns
b) 24ns
c) 48ns
d) 36ns
54. A BCD counter is an example of

a) a full-modulus counter
b) a decade counter
c) a truncated-modulus counter
d) answers (b) and (c)

55. Which of the following is an invalid state in an 8421 BCD counter?
a) 1100
b) 0010
c) 0101
d)1000
56. Three cascaded modulus-10 counters have an overall modulus of

a) 30
b) 100
c) 1000
d)10,000
57. A 10 MHz clock frequency is applied to cascaded counter consisting of a modulus-5 counter, a modulus-8 counter,
and two modulus-10 counters. The lowest output frequency possible is
a) 10 kHz
b) 2.5 kHz
c) 5 kHz
d) 25 kHz
58. A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN mode is
a) 0001
b) 1111
c) 1000
d) 1110
59. The terminal count of a modulus-13 binary counter is

a) 0000
b) 1111
c) 1101
d) 1100
60. A stage in a shift register consists of

a) a latch
b) a flip-flop
c) a byte of storage
d) four bits of storage
61. To serially shift a byte of data into a shift register, there must be
a) 1 clock pulse
b) 1 load pulse
c) 8 clk pulses
d) 1 clk pulse for each 1 in the data
62. To parallel load a byte of data into a shift register with a synchronous load, there must be
a) one clock pulse
b) one clock pulse for each 1 in the data
c) eight clock pulses
d) one clock pulse for each 0 in the data
63. The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with
an initial state of 11100100. After tow clock pulses, the register contains
a)
01011110
b) 10110101
c) 01111001
d) 00101101
64. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register
a) in 8 s
b) in the propagation delay time of eight flip-flops
c) in 1s
d) in the propagation delay time of one flip-flop
65. A modulus-10 Johnson counter requires

a) ten flip-flops
b) four flip-flops
c) five flip-flops
d) twelve flip-flops
c) four flip-flops
d) twelve flip-flops
66. A modulus-10 ring counter requires a minimum of

a) ten flip-flops
b) five flip-flops
Page 4 of 5
67. When an 8-bit serial in/serial out shift register is used for a 24 s time delay, the clk frequency must be
a) 41.67 kHz
b) 333 kHz
c) 125 kHz
Page 5 of 5
d) 8 MHz

Digital Systems1

Uploaded by

Copyright:

Available Formats

Digital Systems1

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Digital Systems1

Uploaded by

Copyright:

Available Formats

Digital Systems

1. Analog signals are (continuous, discrete).

16. How many entries are there on a 4-variable k-map?

d) None of the above

25. Which of the following gates cannot be used as an inverter

26. The Boolean expression A B C is a

c) product term d) complemented term

27. The Boolean expression AB CD is a

b) product term c) literal term

28. An example of a SOP expression is

d) Both answers (a)

d) Both answers (a) and (b)

30. On a K-map grouping 1s produces

b) dont care condition c) POS expression

31. When using dual symbols in a logic diagram

(b) the NAND symbols produce the AND operations.

(b) NOR gates only

(c) Combinations of NAND and NOR gates

(d) Combinations of AND,OR and inverter gates

(e) Any of these

(e) both answers (b) and (d)

(b) A3A2A1A0 = 1100

(c) A3A2A1A0 = 1110

35. Data selectors are basically same as

39. The invalid state of an S-R latch occurs when

(b) S=0, R=1

(c) S=1, R=1

(d) S=0, R=0

(b) during the enable pulse

(c) immediately after the enable pulse

(d) answers (b) and (c)

42. The purpose of the clock input to a flip-flop is to

clear the device

b) set the device

c) always cause the output to change states

45. A flip-flop is in the toggle condition when

c) a 10 kHz square wave

d) a 5 kHz sq. wave

47. Asynchronous counters are known as

b) multiple clock counters

48. An asynchronous counter differs from a synchronous counter in

b) the method of clocking

c) the type of flip-flops used

d) the value of the modulus

49. The modulus of a counter is

b) the actual number of states in its sequence

c) the number of times it recycles in a second

51. A modulus-12 counter must have

54. A BCD counter is an example of

d) answers (b) and (c)

56. Three cascaded modulus-10 counters have an overall modulus of

59. The terminal count of a modulus-13 binary counter is

60. A stage in a shift register consists of

d) four bits of storage

d) 1 clk pulse for each 1 in the data

b) one clock pulse for each 1 in the data

c) eight clock pulses

d) one clock pulse for each 0 in the data

b) in the propagation delay time of eight flip-flops