Subject: Digital System Design (DSD) Sem: 3, EXTC

SUBJECT: DIGITAL SYSTEM DESIGN(DSD)
Sem: 3, EXTC
Question Bank for IA-2
1. Demultiplexer is also called as

a) Data Distributor
b) Data Selector
c) Mux
d) Input to output coder
2. 1-bit magnitude comparator has

a) One input and two outputs
b) Two inputs and two outputs
c) Two inputs and three outputs
d) Three inputs and three outputs
3. Carry look ahead logic uses the concept of

a) Inverting the inputs
b) Complementing the outputs
c) Ripple factor
d) Generating and propagating carries
4. The number of 4:1 MUXES required to construct 32:1 MUX are

a) 11
b) 8
c) 10
d) 12
5. Comparators are used in

a) CPU
b) Motherboard
c) Hard Drive
d) Memory
6. If Strobe input is high then the multiplexer is
a) Enable
b) Disable
c) Saturation
d) High Impedance
7. Demultiplexer is basically a
a) Parallel to Serial converter
b) Storage device
c) Code Converter
d) Serial to Parallel converter
8. If we record any music in any recorder, such type of process is called

a) Multiplexing
b) Encoding
c) Decoding
d) Demultiplexing
9. A combinational Circuit that changes Code into set of signals is called

a) Encoder
b) Code converter
c) Decoder
d) Demultiplexer
10. In a BCD adder if the sum is a valid BCD number then the logic state of correction logic is
a) 0000
b) 0110
c) 0111
d) 1000
11.The Forbidden state of SR Flip Flop is overcomed by

a) JK master Slave Flip Flop
b) JK Flip Flop
c) D Flip Flop
d) T Flip Flop
12. If the data bit at the input is required to be passed on to output without any change the
most suitable flip flop is
a. T Flip Flop
b. D Flip Flop
c. SR Flip Flop
d. JK Flip Flop
13. How is a J-K flip-flop made to

toggle?a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
14.In a master-slave flip-flop, when is the Slave enabled?

a. When the Clock is High
b. When the Clock is Low
c. During level of the Clock
d. When the Clock is Disabled
15.What is the significance of the J and K terminals on the J-K flip-flop?
a. There is no known significance in their designations.

b. The J represents "jump," which is how the Q output reacts whenever the clock goes
highand the J input is also HIGH.
c. The letters were chosen in honor of Jack Kilby, the inventory of the integrated
circuit.
d. All of the other letters of the alphabet are already in use.
16. A positive edge-triggered D flip-flop will store a 1 when .

a) the D input is HIGH and the clock transitions from HIGH to LOW
b) the D input is HIGH and the clock transitions from LOW to HIGH
c) the D input is HIGH and the clock is LOW
d) the D input is HIGH and the clock is HIGH
17.If both inputs of an S-R flip-flop are LOW, what will happen when the clock goes high?
a. The output will reset
b. An invalid state will exist.
c. The output will toggle.
d. No change will occur in the output
18.The simplest type of shift register is
a. SISO
b. SIPO
c. PIPO
d. PISO
19. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out
shift register that is initially clear. What are the Q outputs after four clock pulses?
a) 10011100
b) 11000000
c) 00001100
d) 11110000
20.Asynchronous counter is also called as

a. Parallel Counter
b. Ripple Counter
c. BCD Counter
d. Mod Counter
21. In Asynchronous Counter using T Flip flop inputs T of all the flip flops is connected to
a) Logic 0
b) Clear Input
c) Clock Input
d) Logic 1
22. Parallel loading of data in a counter refers to

a) Each FF is loaded with data on a separate clock.
b) All FFs are preset with data
c) Counter is Cleared
d) Counter is Stored with all 1’s
23. Speed of ripple counter is limited by the propagation delay of

a) Flip flops only with gates
b) Only circuit gates
c) each flip-flop
d) All flip flops and gates
24. Counter which counts randomly without going in sequence is called as _

a) Random Counter
b) Up/down Counter
c) Skipping state Counter
d) Serial Counter
25. State diagram provides

a) exactly the same information as the state table
b) Information about characteristic equation
c) graphical representation of states
d) Information about the truth table
26. Which of the following is not a shift Register Counter

a) Ring Counter
b) BCD Counter
c) Jhonson’s Counter
d) Twisted Ring Counter
27.The counter Obtained by connecting complement of output of last FF to the input of the
first FF is
a) Jhonson’s Counter
b) BCD Counter
c) Ring Counter
d) Up/down Counter
28. Another name for Up Down Counter is
a) Dual counter
b) Multi counter
c) Two counter
d) Multimode Counter
29. The major disadvantage of shift register counters is

a) Not all the states are utilized
b) Complexity in Operation
c) Slow operation
d) Lower Throughput
30.The PLD in which both OR and AND array are programmable is
a. PLA
b. PAL
c. RAM
d. Buffer
31.Current sourcing capability of PLA can be improved by using

a. Input Buffer
b. Memory Units
c. Output Buffer
d. Invert/Non-Invert Matrix
32.The major disadvantage of RAM is

a. Access speed is too slow
b. Its matrix size is too big
c. High power consumption
d. It is volatile
33. The difference between static RAM and dynamic RAM is

a. Static RAM must be refreshed, dynamic RAM does not
b. There is no difference
c. Dynamic RAM must be refreshed, static RAM does not
d. SRAM is slower than DRAM
34. The inputs in the PLD is given through
a. NAND gates
b. OR gates
c. AND gates
d. NOR gates
35.Which of the following is electrically erased and reprogrammed by the user?

a. EEPROM
b. PROM
c. RAM
d. Flip Flop
36.Boolean functions in standard SOP form only can be implemented using

a. PAL
b. PLA
c. RAM
d. PROM
37.PAL is an abbreviation of
a. Programmable AND Logic
b. Programmable Array Logic
c. Preset Array Logic
d. Preset AND Logic
38.Language that describes the behaviour or structure of digital circuit /IC’s is

a. Hardware Data Language
b. Hardware Description Language
c. Hardware Description Logic
d. Hard Description Language
39.VHDL Program format consists

a. Library declaration,Architecture
b. Library declaration,Entity
c. Entity, Architecture
d. Library declaration,Entity,Architecture
40.There are types of Port Modes
a. 3
b. 2
c. 4
d. 5
41.Keyword Process is used in modeling

a. Data Flow
b. Structural
c. Mixed
d. Behavioural
42.Boolean expressions are used in modeling

a. Data Flow
b. Structural
c. Mixed
d. Behavioural
43.The number of OR gates required for a Decimal-to-BCD encoder are

a. 2
b. 10
c. 4
d. 3
44.Which of the following is INCORRECT with reference to PLA

a. It has both programmable OR and AND array
b. It provides full decoding to the variables
c. One application of a PLA is to implement the control over a datapath
d. Massive functions can be implemented uing PLA
45. The minimum number of inputs required to be specified in the entity with
which program for UP/DOWN counter can be written in VHDL are
a. 3
b. 2
c. 5
d. 6
***********

Subject: Digital System Design (DSD) Sem: 3, EXTC

Uploaded by

Copyright:

Available Formats

Subject: Digital System Design (DSD) Sem: 3, EXTC

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Subject: Digital System Design (DSD) Sem: 3, EXTC

Uploaded by

Copyright:

Available Formats

SUBJECT: DIGITAL SYSTEM DESIGN(DSD)

Question Bank for IA-2

1. Demultiplexer is also called as

2. 1-bit magnitude comparator has

3. Carry look ahead logic uses the concept of

4. The number of 4:1 MUXES required to construct 32:1 MUX are

5. Comparators are used in

8. If we record any music in any recorder, such type of process is called

9. A combinational Circuit that changes Code into set of signals is called

11.The Forbidden state of SR Flip Flop is overcomed by

13. How is a J-K flip-flop made to

14.In a master-slave flip-flop, when is the Slave enabled?

15.What is the significance of the J and K terminals on the J-K flip-flop?

a. There is no known significance in their designations.

16. A positive edge-triggered D flip-flop will store a 1 when .

20.Asynchronous counter is also called as

22. Parallel loading of data in a counter refers to

23. Speed of ripple counter is limited by the propagation delay of

24. Counter which counts randomly without going in sequence is called as _

25. State diagram provides

26. Which of the following is not a shift Register Counter

29. The major disadvantage of shift register counters is

31.Current sourcing capability of PLA can be improved by using

32.The major disadvantage of RAM is

33. The difference between static RAM and dynamic RAM is

35.Which of the following is electrically erased and reprogrammed by the user?

36.Boolean functions in standard SOP form only can be implemented using

38.Language that describes the behaviour or structure of digital circuit /IC’s is

39.VHDL Program format consists

41.Keyword Process is used in modeling

42.Boolean expressions are used in modeling

43.The number of OR gates required for a Decimal-to-BCD encoder are

44.Which of the following is INCORRECT with reference to PLA

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.