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Clock Jitter
Effects on Sampling: A Tutorial
Carlos Azeredo-Leme

Abstract
The effect of jitter in data converters is analyzed, with a focus on the frequency domain treat-
ment of the corresponding phase noise. The analysis is mostly intuitive, to give the reader a
good feeling for the mechanisms involved. Both open loop oscillators and phase locked loops
are considered as clock sources. Several application examples are included to illustrate the con-
cepts. Jitter self-referenced measurements are also covered with their relationships to jitter.

Digital Object Identifier 10.1109/MCAS.2011.942067

Date of publication: 25 August 2011

26 IEEE CIRCUITS AND SYSTEMS MAGAZINE 1531-636X/11/$26.00©2011 IEEE THIRD QUARTER 2011
 1. Introduction

C
lock Jitter is probably the most obscure specifi- Clock
cation in data converters. It basically describes
the timing errors in the sampling operation due
to clock disturbances.
In fact, the clock applied to the data converter de- C
termines the timing of the samples produced from the
input signal. Therefore, the clock must be treated as a Input agnd Sampled
delicate analog signal and any disturbances minimized. Signal Signal
Assuming an Analog-to-Digital Converter, ADC, the
Figure 1. Sampling operation.
clock is determinant to the sampling process that nor-
mally takes place at the very first stage. Fig. 1 shows a
simplified form of a sampler.
When the clock goes HIGH, the switch is closed and
the capacitor is charged to the value of the input signal. Error Amplitude
When the clock goes LOW, the switch is opened and the
capacitor stores the value of the input signal that will be
processed further for digitization.
Jitter
In this circuit, it is the instant when the clock goes
LOW that determines the sampling time, the falling edge
of the clock. Any small disturbances to the amplitude
of the clock have no effect because the switch is a bi-
nary device and distinguishes clearly the state HIGH
Figure 2. Sampled value uncertainty vs. sampling time
from LOW even if it fluctuates a little in amplitude. But uncertainty (jitter).
any timing disturbance has a direct effect on the value
sampled and generates an error.
This error cannot be corrected later in the ADC be- For a sinewave of frequency f in and amplitude Ain, the
cause it is already attached into the sampling sequence maximum error is at the zero crossings:
being processed for digitization and will impact the
overall performance of the ADC. verror max 5 Dt Ain 2pfin. (2)
Therefore, clock jitter is critical to the performance
of an ADC and must be specified appropriately. How In order to have this error below 0.5 LSB in a N-bit
much of it is acceptable? How do timing errors translate data converter with input range 1/2Ain, the maximum
into the overall performance? To answer these ques- value of the jitter is
tions is the purpose of this Tutorial.
Ain 1
verror , S Dt , . (3)
2N 2p fin 2N
II. Why Jitter Matters
As data converters have evolved to always-higher sam- For example, for a 12 bit 100 MS/s ADC with maximum
pling frequencies and higher resolutions, they become bandwidth of 50 MHz, the peak-to-peak jitter specifica-
more sensitive to the external conditions. Clock timing tion is 0.8 ps. This kind of jitter requires a very high per-
quality is one of them. formance clock generator.
Nyquist Sampling Theorem assumes periodic sam- The same analysis applies to Digital-to-Analog con-
pling. Any deviation to the ideal sampling instant is de- verters, DACs, where the relevant clock is the one at the
fined as “jitter”. Fig. 2 illustrates how jitter generates an last interface from the discrete-time domain, where the
error. signal samples get sampled-and-held for further contin-
Assuming a jitter value of Dt on the sampling instant, uous-time processing.
the error produced is proportional to the derivative of
the input signal [1], [2]: III. Sampling Errors Due to Jitter
Jitter statistics are typically similar to random noise.
dvin Therefore, equation (3) is often exaggerated. Most rel-
verror 5 Dt . (1)
dt evant is to reflect the effect of jitter on SNR.

C. Azeredo-Leme is with Synopsys Inc., Lagoas Park, Ed. 4, 2740-267 Oeiras, Portugal.

THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 27

 The jitter sampling error is not affected by the
actual clock frequency.

achieved, SNRTotal, that includes the intrinsic perfor-

90 mance of the ADC and the effect of the clock jitter, can
5 ps 10 ps 20 ps
80 then be expressed as [4]:
50 ps 100 ps
70
SNR (dB)

60
SNRTotal 5 220 log"10 1
2SNRADC 2
1 10 1
2SNRJitter 2
10 10 3 dB 4 . (6)
50
40
30 Fig. 3 illustrates this equation for an SNR ADC of 65 dB. It
20 shows the SNRTotal as a function of the sampling clock
0.1 1 10 100 1,000
jitter (rms) and signal frequency (f in).
Fin (MHz)
Some key points can be derived from this analysis:
Figure 3. SNR degradation due to sampling clock jitter for 1) The jitter sampling error is not affected by the
a converter with SNRADC 5 65 dB. actual clock frequency
2) SNR performance at low frequency is not impact-
Let’s denote D trms as the standard deviation of clock ed by jitter
jitter (or root mean square). We can then re-write the 3) But at high frequency, jitter can be the dominant
sampling error in (1) as: limiting factor on SNR performance
Tables 1 and 2 illustrate this for some concrete cases
dvin Ain
s 1 verror 2 5 Dtrms sa b 5 D trms # 2p fin , (4) assuming an ADC with an intrinsic SNR of 65 dB.
dt "2 As can be seen, for a 1 MHz signal, the SNRtotal is close
where s 1 2 is the root mean square operator. to the SNR ADC , with little impact from jitter. However, for
The resulting SNR on the sampled sinewave is a 50 MHz signal, the SNRtotal degrades strongly with the
then [3]: effect of jitter.

Ain / "2 IV. Jitter in the Frequency Domain

SNRJitter 5 20 log £
Ain ≥ The traditional method presented above, based on
Dtrms # 2pfin
"2 equation (5) to obtain the SNR as a function of clock jit-
5 220 log 1 Dtrms # 2pfin 2 3 dB 4 . (5) ter and signal frequency, has some limitations.
Firstly, it assumes a very extreme situation of a full-
This SNRJitter limitation must be added to the intrin- scale sinewave input at the maximum frequency corner
sic ADC SNR limitation, SNR ADC . SNR ADC is typically de- of the signal bandwidth. Although this situation may
termined by quantization and thermal noise and is de- happen in some applications, most commonly the input
pendent on the ADC implementation. The overall SNR signal energy is spread over some bandwidth much be-
low the sampling frequency. On the other hand, in sub-
Table 1. sampling systems the signal band is actually above the
sampling frequency.
Maximum Fin Jitter
Secondly, it attaches all the sampling error to the
1 MHz 13.15 ps rms output signal even if part of it may lie out-of-band and,
50 MHz 2.63 ps rms therefore, is removed by a later filter stage.
Allowed clock jitter assuming SNR ADC 5 65 dB for achieving an SNRTotal of 60 dB In order to take these situations into account, a spec-
trum representation of the sampling error is required.
Table 2. The voltage sampling error is given by the sampling
time error, or jitter, multiplied by the time derivative of
Maximum Fin SNRTotal
the input signal at the sampling time:
1 MHz 64.9 dB
50 MHz 47.6 dB dvin 1 t 2
verror 1 k 2 5 Dt 1 kTS 2 . ` . (7)
Overall SNR assuming SNR ADC 5 65 dB and a jitter of 13.15 ps rms dt kTS

28 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

 Taking the discrete-time Fourier transform (DTFT) [5],

dvin 1 t 2 F (Δt)
F 1 verror 1 k 22 5 F 1 Dt 1 kTS 22 * Fa ` b, (8) (dB)
dt kTS

where F denotes the DTFT and * denotes convolution.

Therefore, the spectrum of the sampling error is the con-
volution of the jitter spectrum with the spectrum of the
time-derivative of the input signal at the sampling instants. fLoopBw Log f
Assuming that the input signal and the clock are in-
Figure 4. Typical spectrum shape of the clock jitter pro-
dependent (for example, the signal is not disturbed by duced by a PLL.
the clock and not already sampled), then (8) can be
simplified to

Verror 1 f 2 5 DT 1 f 2 * j 2pf # Vin 1 f 2 , (9)

(dB.m/Hz)
which relates directly the spectrum variables of, re-
spectively, the sampling error, the jitter and the input
signal.
Assuming a sinewave as the input, the jitter spectrum f1 f2 FS f3 (Hz)
will be scaled by the value of the input frequency (in (dB.m/Hz)
rad/s), and will be centered on its frequency by the con-
volution operation:
Ain
Verror 1 f 2 5 2pfin # # DT 1 f 2 fin 2 . (10)
"2 f3–FS f1 f2 (Hz)

The clock is often derived from a PLL using a ring Figure 5. Illustration of the jitter spectrum on sinewave
or LC oscillator. Then, the spectrum of its jitter follows inputs.
the shape illustrated in Fig. 4. It is reasonably flat within
the loop bandwidth, and falls outside. Therefore, most
of the jitter energy is at relatively low frequencies.
Fig. 5 illustrates the resulting spectrum for an input
signal composed of several sinewaves of different frequen-
cies. In the upper plot, there are three sinewaves at fre-
quencies respectively f1, f2, and f3 and the clock at frequen-
cy FS. The clock jitter can be seen as side-lobes around
its center frequency, corresponding to the jitter spectrum
scaled by the clock frequency itself (or phase noise).
The bottom plot shows the spectrum of the sampled
signal until half the sampling frequency. As expected,
the sampling error shows as side-lobes around the re-
spective center frequencies, with amplitude propor-
tional to the radian frequency of the sampled sinewave.
Most interesting is f3 that is above the clock frequency
and therefore is sub-sampled. Even if it is shifted to low
Figure 6. Plot of the phase noise on a spectrum analyzer.
frequency f3 2FS, its sampling error is the largest be-
cause it is proportional to the frequency of input signal
that is sampled. of noise. Fig. 6 illustrates a plot of the spectrum around
the clock frequency. The phase noise is clearly visible as
V. Phase Noise sidelobes around the clock frequency.
The spectrum of jitter is very difficult to measure direct- Some spectrum analyzers with a phase noise module
ly. But it is quite straightforward to measure the phase allow plotting the frequency axis relative to the clock
noise of a clock signal. A common spectrum analyzer center frequency. This allows obtaining a single-sideband
can be used, if the clock amplitude is reasonably free spectrum plot in logarithmic scale as shown in Fig. 7.

THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 29

 A. Phase Noise to Jitter Conversion
Phase Noise of (2.6 GHz PLL) Mdiv = 2,600 From (11) f 1 t 2 has the following relationship with jitter [7]:
0
Phase Noise (dBc/Hz)

–20
f 1 kTS 2 5 2p FS # Dt 1 kTS 2 , (14)
–40
–60
which shows that the clock phase noise is the same as
–80
–100 the clock jitter scaled by its own radian frequency, 2pFS.
–120 That is equivalent to referencing jitter to the clock pe-
–140 riod. For example, a 100 MHz clock with a jitter of 10 ps,
100 1,000 10,000 100,000 1,000,000 has a phase noise of 0.00628 rad, or 0.36 deg, or 0.1% of
Frequency Offset (Hz)
the clock period.
Figure 7. Plot on a spectrum analyzer with phase noise In the frequency domain, where the clock phase
measurement. noise is most commonly represented, it is then equal to
the clock jitter scaled by 2pFS :

The phase noise of a clock signal is its phase modula- FS 1 f 2 5 2pFS # DT 1 f 2 . (15)
tion due to the time-domain instabilities, or jitter. For
simplicity, let’s represent the clock as a sinewave of fre- To obtain the total jitter from phase noise, the phase
quency FS [6]: noise scaled by 1/ 2pFS is integrated over frequency in
power density 1:
vclock 5 Asin 1 2p FS 1 t 1 Dt 1 t 222
` `
5 Asin 1 2pFS t 1 f 1 t 22 , 1 1
(11) Dtrms 5 F2 1 f 2 df 5 2 10L1f2/10df . (16)
2pFS Å 30 2pFS Å 30

where f 1 t 2 is the phase noise in the time domain.

Assuming f 1 t 2 small, B. Derivation of SNR from Phase Noise
Substituting (15) in (10), we obtain the spectrum of the
vclock > Asin 1 2pFS t 2 1 A cos 1 2p FS t 2 f 1 t 2 . (12) sampling error on a sinewave as a function of the clock
phase noise:
The second term of this expression is the additive
fin Ain
noise due to the phase modulation. The phase noise ap- Verror 1 f 2 5 F 1 f2fin 2 . (17)
FS "2
pears multiplied by a cosine at the clock frequency. It
follows that in the frequency domain the spectrum of As expected, it shows the phase noise spectrum
the phase noise, F 1 f 2 , is convolved with the noise-free scaled by the ratio of the input frequency to the clock
clock and appears as sidebands around its center fre- frequency centered at the input frequency.
quency, as seen in Fig. 6. In order to obtain the in-band noise that will affect
It is often represented as L 1 f 2 , or single-sideband the SNR, (17) is integrated in power over the system
phase noise power spectrum, and is equal to the noise passband 1 Fmin , Fmax 2 . The resulting SNR is
power spectral density per Hertz at the frequency Fs 1 f
divided by the clock signal power A2/ 2. It is called sin-
A2in / 2
gle-sideband because only one side of the noise power SNR J 5 10 log ° ¢
e
Fmax 2
Verror 1 f 2 df
is taken into account, so it includes only half the noise Fmin

energy. Therefore, it is related to F 1 f 2 as

Fmax
fin L1f2fin2 /10
5 220 log ° 3 10 df ¢ . (18)
1 FS Å Fmin
L 1f 2 5 10 log a F2 1 f 2b
2
Notice that there is no factor 2 because the integration
L1f 2 is over both sidebands of L 1 f 2 2Fmin can be lower than Fin.
F1f 2 5 2# 10 10 . (13)
Å
1
In fact we are abusing language a little by using spectral represen-
L 1 f 2 is normally represented in dBc/Hz and corre- tations. Since these are random variables, phase noise and jitter can
only be expressed in power spectral density. We are further abusively
sponds to what is presented in a spectrum analyzer at off- assuming that F(f) is real. The power spectral density should be ex-
set frequencies from the clock center frequency (Fig. 7). pressed as F*(f) . F*(f) instead of F 2 (f).

30 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

 In Section 7 this equation will be illustrated with sev-
eral practical examples. But before, let’s get some more L(f)
1/f Noise
insight into phase noise in typical clock sources. –30 dB/dec
(dBc/Hz)

Thermal Noise
VI. Phase Noise of Oscillators and PLLs
–20 dB/dec
Amplitude Noise
A. Oscillator Phase Noise
The phase noise of an oscillator is composed of two main
regions as illustrated by Fig. 8. The larger region is due fkp Log foffset
to thermal noise that has an effect like frequency modu-
lation and therefore generates sidebands falling inverse- Figure 8. Phase noise of an oscillator.
ly proportional with frequency offset. In a log plot, they
result in a slope of 220 dB/dec. At low frequency offsets,
there is a region with a slope of 230 dB/dec due to up- cause the signal is synchronized at the beginning of
conversion of 1/ f noise. The corner frequency between each horizontal frame.
the two regions, fkp, is at a lower frequency than the 1/ f
noise corner frequency, and dependent on the oscillator B. PLL Phase Noise
implementation [8], [9]. A PLL, see Fig. 9, behaves as a lowpass filter for the phase
The flat curve is the amplitude noise of the oscilla- noise of the input clock reference and as a highpass filter
tor. Contributions for the amplitude noise come mainly for that of the locked VCO. Most common implementa-
from buffers in the signal path, the oscillator itself has tions have a second order transfer function [10]. In the
very low amplitude noise due to its own mechanisms for case of the input clock reference, the PLL also applies a
amplitude stabilization. gain, M, equal to the ratio of output frequency to input
When observing the oscillator output in a spectrum frequency. Considering Fin 1 f 2 the phase noise of the in-
analyzer, the resulting curve is the combination of both put clock reference and FVCO 1 f 2 the phase noise of the
noises, as illustrated by the dashed curve. locked VCO, the output phase noise is given by:

Total Noise and Jitter M f

Fout 1 f 2 5 Fin 1 f 2 1 11 F 1 f 2 . (19)
From (16), jitter is the integral of this curve from zero f Å FLoop VCO
11
to infinite, divided by the clock frequency. But the total Å FLoop
integrated noise or jitter with such a curve is infinite,
which obviously cannot correspond to practical cases. Typically, the input clock comes from a crystal oscil-
At high frequency offsets, the flat amplitude noise rolls lator and consequently, has very low phase noise, even
off at the system bandwidth. after amplification by M. It will impact the output phase
At low frequencies, the integration is also unbounded noise only at very low offset frequencies.
due to the 1/ f 2 slope, and more so with the 1/ f noise gen- The locked VCO phase noise is often relatively large,
erating a 1/ f 3 slope. This reflects the effect of the oscil- especially if it is built as a ring oscillator. And most of its
lator frequency drifting with time due to noise. In fact, energy is at low frequencies, as illustrated in Fig. 8. The
the phase will diverge without limit when the frequency highpass transfer function of the PLL is therefore very
drifts off. It is similar to the popular random-walk pro- convenient and effectively improves substantially the
cess that generates unbounded trajectories. overall phase noise performance.
In practical situations, the jitter is defined rela- The PLL internal blocks, specially the phase detec-
tive to the observation period, taking the average tor, generate additional noise that is transferred to the
clock frequency as the reference to measure the jit-
ter against. That is equivalent to applying a highpass
transfer function to the phase noise spectrum with
cut-off frequency equal to the inverse of the averaging Loop
Loop VCO
Filter VCO
period used. In actual applications this limit is relat- Filter

ed to the signal processing being done. For example, Clock Out

in telecommunications, this lower limit often corre- Clock In Phase
Phase Divider
Divider
Detector
Detector by M
by M
sponds to the symbol rate. In audio, it corresponds
to 20 Hz, the lower limit of human audibility. And in
Figure 9. Phase locked loop.
video it corresponds to the horizontal refresh rate be-

THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 31

 At high offset frequencies the amplitude noise domi-
L(f) Input Reference nates and generates a flat region visible on a spectrum
(dBc/Hz) Phase Detector and Charge Pump analyzer plot.
VCO –20 dB/dec The dashed curve shows the combined spectrum at
Spur the output of a PLL and can be compared with Fig. 7 that
shows an actual measurement.
Amplitude
Noise
An oscillator also picks up noise from the supplies or
the substrate. This noise is typically generated by the
fLoop Log foffset actual activity in the chip and can show up as spurs on
the phase noise spectrum. An example is illustrated in
Figure 10. Phase noise of a PLL. Fig. 10 by the vertical line.

VII. Application Examples

output with a lowpass transfer function similar to the In the following, several application examples will be
input clock reference. studied. The master clock will be assumed to be pro-
The resulting phase noise spectrum at the output is duced by a PLL and have the phase noise spectrum as
illustrated in Fig. 10. The curve for the locked VCO phase in Fig. 11 for a clock frequency of 1 GHz. For simplicity
noise gets filtered down by a steep 40 dB/dec slope be- the noise density is flat within the band, correspond-
low the PLL loop bandwidth. Therefore, its 220 dB/dec ing to a situation of similar noise contributions by the
slope is bent downward below fLoop. Even the 1/ f region VCO and the phase-detector/charge-pump. We neglect
is bent-down by the loop filter action. the reference clock phase noise (dashed line on the low
The phase noise of the input reference clock is rel- frequency corner) because in many cases it is below the
evant only at very low offset frequencies. slowest relevant signal rates.
The phase-detector and charge-pump noise may be- Integrating the area of the solid curve (multiplied
come the dominant phase noise contribution below the by 2 for double-sideband) gives the total phase noise
PLL loop bandwidth. power. Taking the square root gives the rms phase
noise:

` 10 280/10
L(f)
Reference Noise fTotal 5 2 e0 2
df 5 0.056 rad rms. (20)
–80 dBc/Hz f
(dBc/Hz) 11 a b
ã 100 # 103
–20 dBc/Hz
Jitter is then

1 0.056
Dtrms 5 v fTotal 5 5 8.9 ps rms. (21)
S 2p109
100 kHz Log foffset
Fig. 12 plots the cumulative noise power as a percent-
Figure 11. Clock phase noise at 1 GHz.
age of the total along frequency. It shows that half the
phase noise power is within the loop band (100 kHz).
And most of the remaining noise is still below 1 MHz. In
the case of a phase noise spectrum mostly dominated by
100
VCO noise, as in Fig. 7, the phase noise energy would be
75 concentrated at the loop band corner frequency.
(%)

50
A. Sampling of Generic Sinusoidal Signals
25 Let’s assume an ADC sampled at 100 MHz. We need to
divide the 1 GHz master clock, generated with the PLL
0
described above, by a factor of 10, see Fig. 13. This divid-
03

04

05

06

07

er will add some flat phase noise as the horizontal line

+

+
E

E
00

00

00

00

00

in Fig. 10. But we assume this is low enough so that we

1.

1.

1.

1.

1.

Frequency (Hz) can neglect it. Let’s further assume that the input signal
Figure 12. Cumulative phase noise power in percentage.
bandwidth is limited at 25 MHz and a digital filter after
the ADC removes all energy above that.

32 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

 The 100 MHz clock will have the same jitter as the
1 GHz master clock. And its phase noise will have the Divider
Divider 1-GHz
1 GHz
same spectrum shape but scaled down by 10, or shift- 100-MHz Clock by 10
by 10 Clock
Clock
ed down by 20 dB, resulting in a total phase noise of
0.0056 rad rms.
25-MHz
25 MHz
The worst case input signal is a sinewave with an am- Input Signal ADC
ADC Output
Low Pass
Lowpass
Signal
plitude equal to the ADC input range at a frequency just
enough below 25 MHz such that most of the phase noise Figure 13. ADC clocked at 100 MHz from a 1 GHz master
still stays within the passband of the digital filter. Let’s clock.
then assume it is 24 MHz.
Using (18) we can now obtain the SNR limitation due Key points:
to jitter: 1) The actual sampling frequency is not relevant.
fin What is relevant is the master clock phase noise
SNRJ 5 220 loga " e025 MHz10 LF 1f2fin2dfb
s
and its frequency ratio to the signal.
Fs
2) The worst-case situation is a maximum amplitude
fin 25 MHz 1 LMCk1f2fin2 sinewave just enough below the passband limit so
5 220 log ° e0 10 df ¢ , that most of the convoluted phase noise is in-band.
1 Å 10
F 3) Any headroom will directly improve the SNR result.
10 MCk

where FS is the actual sampling frequency, 100 MHz, B. Sub-Sampling

equal to the master clock divided by 10. And the cor- Some applications, such as direct IF sampling, use sub-
responding phase noise, LFs, is equal to the master clock sampling operation. In this situation the input signal is
phase noise scaled down by the same factor 10. The end near one of the clock harmonics and after sampling it is
result is the same as using the master clock phase noise shifted to baseband by aliasing.
and assuming 1 GHz for FS , because the division factors For example, let’s assume an input signal frequency
cancel in the numerator with the denominator. It is inde- of 302 MHz. After sampling it gets shifted to 2 MHz due
pendent of the actual sampling frequency. The SNR limi- to aliasing with the 3rd clock harmonic, see Fig. 14.
tation due to jitter is only a function of the master clock The resulting SNR limitation is now:
phase noise and of the ratio of its frequency to the input
302 MHz
signal frequency2. SNRJ 5 220log a 0.056 radb 5 35.4 dB. (23)
1 GHz
In this example, the integral limits include most
of the phase noise energy because of the choice of This clearly shows that systems operating in sub-
signal frequency just enough below the passband sampling require very clean clock sources. In fact, the
limit. requirement is directly related to the input signal fre-
We can then use the total phase noise of the master quency and it is independent of the actual sampling
clock obtained in (20) and scale it by the ratio of the frequency.
input frequency to the masterclock frequency:
C. Interferer Situation
24 MHz Let’s now consider a situation in which the in-band re-
SNRJ 5 220 log a 0.056 radb 5 57.4 dB. (22)
1 GHz ceived signal is very weak. For example, it is 60 dB below
the ADC input range. The passband is the same 25 MHz.
In the situation that the maximum signal amplitude
has some headroom below the ADC input range, this
headroom would have to be added to the result. For
(dBm/Hz)

example, in radio equipment some headroom margin

must be allowed to allow for sudden changes in signal
strength at the antenna that are not immediately com- 100 302
(MHz)
(dBm/Hz)

pensated by the automatic gain control (AGC). Assum-

ing such headroom to be 10 dB, the SNR limitation due
to jitter on this ADC would be 67.4 dB.
2 25 (MHz)

2
Or, using (21), it is a function of the master clock jitter and the input Figure 14. Sub-sampling situation.
frequency solely.

THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 33

 example is OFDM, consisting of multiple sub-bands (of-
ten above 1000 sub-bands) tightly packed side-by-side
Passband
0 dBFS such that they fill completely the available channel band.
–6 dBFS Therefore, these systems are very efficient in band occu-
Interferer
pation. And they are also very robust to interference be-
Weak In-Band
Signals
cause only the sub-band masked by the interferer is lost
and it is easily recovered by forward error correction.
–60 dBFS Similarly for multipath nulls. Examples of systems using
25 26
OFDM are WLAN, WIMAX, Digital TV, UMTS and LTE.
(MHz)
Such a system is not straightforward to analyze for
Figure 15. Situation with an out-of-band interferer. the effect of jitter on the sampling clock, because there
is no single sinewave carrier to convolve with the clock
phase noise. Instead, it is a multi-carrier signal, one car-
But there are strong interferer signals out-of-band. rier for each sub-band.
These interferer signals can be as strong as 26 dBFS, One characteristic of OFDM modulation is its large
meaning that there is 6 dB headroom to the ADC input peak-to-rms ratio, or crest factor – typically 15 dB. That
range. Let’s further assume that the closest interferer to means that it needs relatively large headroom from the
the passband is at 26 MHz, see Fig. 15. ADC input range. The SNR derivations used a sinewave
After the ADC this interferer is completely removed that has a peak-to-average ratio of 3 dB. Therefore, ad-
by the digital lowpass filter. But due to the phase noise ditional headroom of 12 dB must be considered for such
convolution process, some of the sampling noise will fall OFDM modulated signals.
in-band and will affect SNR. More specifically, the phase Phase noise at frequency offsets below the carrier
noise above 1 MHz offset frequency on the lower side- separation produce a common rotation to all the car-
band. Integrating L 1 f 2 for offset frequencies above 1 MHz: riers and can be compensated with signal processing.
` That is why some pilot tones are normally included in
10 280/10
f1 MHz 5 3 2
df 5 0.01 rad rms. (24) the constellation. Therefore, only the phase noise at off-
106 f
11 a b set frequencies above the carrier separation is relevant.
ã 100 # 103 For simplicity, we can consider an OFDM signal as
Note that this time there is no multiplication by two multiple sinewaves, one for each carrier. Let’s assume
because only one sideband contributes. 1000 sub-bands in a 10 MHz channel at baseband (be-
The resulting SNR limitation, already including 6 dB tween 25 MHz and 15 MHz). The power of each carrier
for the headroom, is then: is 1/1000th of the signal power (230 dB) because they
are uncorrelated with each other. And the signal power
26 MHz
SNRJ 5 220 log a 0.01 radb 1 6 5 78 dB, (25) is 15 dB below the ADC input range. Therefore, each car-
1 GHz
rier is at 245 dBFS. This is illustrated in Fig 16. Let’s fur-
which results on a SNR on the weak input signal of just ther assume that for proper demodulation of this signal
18 dB. the SNR must be better that 35 dB (enough for QAM-256
on each carrier).
D. OFDM Modulated Signals The clock phase noise will be convolved with each
In telecommunications, many systems use modulation carrier scaled by the carrier frequency. Normally, the
techniques that generate a broad flat spectrum. An carriers’ separation is small and below the PLL loop
bandwidth. And the channel width is much larger than
the PLL bandwidth.
Channel Then, assuming a clock phase noise spectrum like
Power Is –15 dBFS in Fig. 11, most of the convolved noise energy for each
1,000
–45 dBFS/Carrier carrier stays within the channel, scaled by the carrier
Carriers
frequency from 0 to 5 MHz. The average noise power per
Jitter- carrier occurs for the carrier at 5 MHz / "3 5 2.88 MHz3.
Induced
Noise Adding over the 1000 carriers cancels with the 230 dB
factor of the carrier power.
–5 0 5 (MHz)
3
Calculated as "1 e05 MHz f 2 df 2 / 15 MHz2 5 15 MHz2 / 1"3 2. This is valid
Figure 16. OFDM channel and noise due to sampling jitter. also for any uniform rectangular power spectrum signals, not only
multi-carrier based.

34 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

 The SNR limitation due to jitter is, then, given by:

2.89 MHz

(dBm/Hz)
SNRJ 5 220 log a 0.056 radb 1 12 5 88 dB. (26)
1 GHz

Two conclusions are evident. One is that the SNR is

independent of the number of carriers. Second, the re- FS (Hz)
sulting SNR is much above the required 35 dB, showing
Passband

(dBm/Hz)
that OFDM modulation is very robust to sampling jitter,
being limited instead by nearby interferer situations as
described above.

FIN FS /2 (Hz)
E. Broadband Phase Noise
Imagine a situation in which the clock signal is routed Figure 17. Sampling of broadband phase noise.
through a large digital core with insufficient isolation
precautions. This can happen in a large SOC with not
careful enough planning of the clock distribution. Then, erence input clock frequency. Additionally, any spurs on
the clock signal will be corrupted with broadband noise the supply or substrate easily leak into the clock distribu-
from the several gates crossed, crosstalk from neighbor- tion network, modulating the phase and appearing as dual
ing lines and supply/substrate noise. The bandwidth of spurs on the phase noise plot, one at each side of the clock
this noise extends well above the clock frequency as frequency. These are very difficult to track and correct on
seen in Fig. 17, limited by the digital gates speed. After a large SOC, even with very good isolation practices.
sampling, the high frequency components of the phase Often, clock spurs have insufficient energy to sig-
noise fold back into the Nyquist band 0-to-FS due to nificantly contribute to the total phase noise or SNR of
aliasing and can become the dominant source of phase the sampled signal. But the corresponding spurs on the
noise compared with the low frequency components. sampled signal can limit the resulting SFDR performance
In our example system, only the band from 0 to of a system. Modern systems are very sensitive to SFDR
25 MHz will be captured due to the digital lowpass filter because this parameter determines the systems ability
following the ADC, as shown by the box in Fig. 17. There- to resolve weak signals in a crowded spectrum with un-
fore, half the broadband noise is removed due to the wanted and strong nearby interferers.
oversampling used in this ADC. In Sigma-delta ADCs, Spurs on the clock phase noise spectrum are trans-
the oversampling is much higher, of the order of 100. ferred to the sampled signal by the same mechanism as
In these systems, the robustness of the ADC to broad- phase noise [4], [11]. They are convolved with the signal
band phase noise is very good because about 99% of the and scaled by the ratio of the signal frequency to the
noise is removed in the decimating digital filters. clock frequency.
For example, let’s assume a 100 MHz clock with a spur
F. Clock Divider at 61 MHz offset with amplitude 250 dBc, and an input
We concluded before that by dividing, the phase noise sinewave of 20 MHz. The spurs on the sampled signal
is simply affected by the division factor (assuming the would be at 19 and 21 MHz and with amplitude 264 dBc.
divider is ideal and adds no noise). In many cases, the spurs are at quite large frequency
However, that does not include the effect of aliasing. offsets. In these cases, they normally generate spurs on
In fact, the noise above the divided clock frequency is the sampled signal outside the signal band. Then, these
aliased and it is folded down. Therefore, the high fre- spurs may either:
quency flat portion of the phase noise (flat line in Fig. 18)
is scaled with the square root of the division ratio.
Scales Directly with Division
VIII. Clock Spurs Broadband Phase Noise
L(f ) Extending Beyond FS Scales
Spurs like the vertical line in Fig. 10 represent determin- (dBc/Hz) with the Square Root of the
istic jitter. They can arise through many possible mecha- Division
Folding
nisms. If the loop filter of a PLL is improperly designed, a due to Aliasing
residual leakage of the reference input clock appears on
the VCO control voltage, generating a frequency modu- FS /M FS Log foffset
lation of the output clock. That results in spurs on both
Figure 18. Phase noise scaling with clock division.
sides of the clock with frequency offsets equal to the ref-

THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 35

 signal would fall in the aliasing band
(dBc) at 70 MHz. It would then be folded
down to 30 MHz, see Fig. 19b.
Clock
Now, if the system included a
25 MHz lowpass filter after the
–50 ADC, the above spur would fall
outside its passband and would
50 100 150 (MHz) then be removed.
(a)
But if there was an interferer at
(dBc) Passband 30 MHz, it would generate a spur
at 80 MHz that would fall back in
Folding Due to Aliasing
band at 20 MHz due to aliasing,
Sampled Spur
see Fig. 19c.
–60.5
20 30 FS/2 70 (MHz) IX. Jitter Measurement
It is quite difficult to measure jit-
(b) ter directly. The jitter definition is
(dBc) the time error of the clock edges
Interferer Out-of-Band relative to the ideal position. But
Folding Due to Aliasing how to know the ideal position?
Normally, the jitter-free clock sig-
Sampled Spur nal is not available.
–60.5
In practice, a self-referenced
20 30 FS/2 80 (MHz) measurement is often used [12],
(c)
[13]. Different definitions exist.
Figure 19. Examples of spurs aliasing. The jitter itself is also denoted
tracking jitter, timing jitter or ab-
solute jitter. We will now proceed
1) Fold down into the signal band due to aliasing to relate it to the self-referenced measurements.
2) Get removed by the system filters if they fall in a
rejection band A. Period Jitter
3) Fall back into the signal band by sampling of an Period jitter, also known as edge-to-edge or cycle-to-
out-of-band interferer cycle jitter4, is the variation of the clock period. It can
Considering the example above but with the spurs at be easily measured on an oscilloscope triggering on one
frequency offsets of 650 MHz, the spur of the sampled rising edge of the clock and looking at the time varia-
tions of the next rising edge.
This measurement gives an important specification
Δtrms for digital circuits timing, because it shows the time
available for the signals settling within a clock period.
Analytically, it is the discrete time difference of jitter:

(a) DtPeriod 1 kT 2 5 Dt 1 kT 2 2 Dt 11 k21 2 T 2 (27)

Trigger Accumulated
Point Jitter corresponding to a transfer function 1 12z 21 2 , or
2 sin 1 pf/ Fs 2 in the frequency domain.
It can then be related to phase noise as:

L1f 2 2
1 pf
2 # 10 10 a2 sina bb df .
`
Period Jitter DtPeriod 5 e
2pFS Å 0 FS
(28)
(b)

Figure 20. Measurement of accumulated jitter: (a) clock

4
with jitter and (b) clock triggered on an edge showing the The term cycle-to-cycle jitter is also sometimes used to refer adjacent
accumulated jitter with time. period jitter, which is the difference between two consecutive periods.
We will not cover this definition in this work.

36 IEEE CIRCUITS AND SYSTEMS MAGAZINE THIRD QUARTER 2011

 teristics. Some application examples were used to dem-
100
onstrate situations of sub-sampling, presence of out-of-
τ = 1/2πBWPLL band interferers, broadband signals, broadband jitter
Accumulated Jitter (ps rms)

Jitter
and spurs. Jitter is often measured by self-referenced
10 methodologies, which must be carefully interpreted to
obtain the actual jitter value affecting sampling.

Accumulated Carlos Azeredo-Leme (M’86). Received

1 Jitter
the Licenciado degree in E.E. from Insti-
Period Jitter
at 1 GHz tuto Superior Técnico, Portugal, in 1986,
the M.S.E.E. degree from Instituto Supe-
0.1 rior Técnico, Portugal, in 1990 and the
1 10 100 1,000 10,000 100,000
Delay τ (ns) Ph.D. degree from ETH-Zurich, Switzer-
land, in 1993.
Figure 21. Accumulated jitter as a function of delay, t. Since 1994 he holds a position as Professor Auxiliar
at the Instituto Superior Técnico, Lisbon, Portugal.
B. Accumulated Jitter From 1993 to 2007, he was co-founder and member
Accumulated jitter is similarly measured as period jitter, of the Board of Directors of Chipidea Microelectronics,
but taking a later clock edge (Fig. 20). It is a function of with the position of Chief Technical Officer. There, he
the number of clock periods between the triggered edge was responsible for complete mixed-signal solutions,
and the measurement edge. analog front-ends and RF. He worked in the areas of au-
Analytically, it is also a discrete time difference of jitter: dio, power management, cellular and wireless communi-
cations and RF transceivers.
DtAcc 1 kT, M 2 5 Dt 1 kT 2 2 Dt 11 k 2 M 2 T 2 (29) He is now with Synopsys Inc. as a senior staff mem-
ber of Analog IP.
corresponding to a transfer function 1 12z2M 2 , or His scientific interests are in analog, mixed-signal and
2 sin 1 pf MTs 2 in the frequency domain. RF IC design, focusing on low-power and low-voltage.
It can then be related to phase noise as:
1 2
References
Lf
1
2 # 10 10 1 2sin 1 pft 22 2df ,
` [1] B. Brannon and A. Barlow, “Aperture uncertainty and ADC system
DtAcc 1 t 2 5 e (30)
2pFS Å 0 performance,” Analog Devices, Inc., Applicat. Note AN-501.
[2] D. Redmayne, E. Trelewicz, and A. Smith, “Understanding the effects
where t 5 MTS . of clock jitter on high speed ADCs,” Linear Technology, Inc., Design Note
1013.
Fig. 21 shows the accumulated jitter as a function of t, [3] P. Simon, “Little known characteristics of phase noise,” Analog De-
assuming the phase noise of Fig. 11, on the 1 GHz clock. vices, Inc., Applicat. Note AN-741.
The accumulated jitter increases with t, starting at [4] M. Mota, “Understanding clock jitter effects on data converter per-
formance and how to minimize them,” Synopsys, Inc., White Paper.
0.3 psrms for t 5 1 ns (the clock period). It stabilizes for [5] V. Arkesteijn, E. Klumperink, and B. Nauta, “Jitter requirements of
large t at 12.6 psrms, which is "2 Dtrms. This is expected the sampling clock in software radio receivers,” IEEE Trans. Circuits
Syst. II, vol. 53, no. 2, pp. 90–94, Feb. 2006.
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jitter on both edges and the jitter is added in variance and jitter,” Analog Devices, Inc., Applicat. Note AN-756.
[14]. Another interesting observation is that the start of [7] W. Kester, “Converting oscillator phase noise to time jitter,” Analog
Devices, Inc., Tutorial MT-008.
the curve stabilization is for t around the value of the [8] T. Lee and A. Hajimiri, “Oscillator phase noise: A tutorial,” IEEE J.
PLL loop time constant 1 1/ 2pBWPLL 2 . This observation Solid-State Circuits, vol. 35, no. 3, pp. 326–335, Mar. 2000.
[9] K. Kundert, Predicting the Phase Noise and Jitter of PLL-Based Fre-
shows that a good estimation of jitter is to measure the
quency Synthesizers. The Designer’s Guide Community.
accumulated jitter for longer than the loop time con- [10] D. Lee, “Analysis of jitter in phase-locked loops,” IEEE Trans. Cir-
stant, and divide it by "2 . cuits Syst. II, vol. 49, no. 11, pp. 704–711, May 2002.
[11] T. Neu, “Impact of sampling-clock spurs on ADC performance,” Ana-
log Applicat. J., 3Q 2009.
X. Conclusions [12] N. Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer, “On the jitter
requirements of the sampling clock for analog-to-digital converters,”
Jitter is a critical specification for accurate and fast
IEEE Trans. Circuits Syst. I, vol. 49, no. 9, pp. 1354–1360, Sept. 2002.
data converters. Not only is the total jitter of relevance, [13] U. Moon, K. Mayaram, and J. Stonick, “Spectral analysis of time-
but also its spectrum distribution needs consideration. domain phase jitter measurements,” IEEE Trans. Circuits Syst. II, vol. 49,
no. 5, pp. 321–327, May 2002.
Clocks from open loop oscillators and from phase [14] J. McNeill, “Jitter in ring oscillators,” IEEE J. Solid-State Circuits, vol.
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THIRD QUARTER 2011 IEEE CIRCUITS AND SYSTEMS MAGAZINE 37