Doping

Dopants can be introduced into silicon by the following methods:

i) during crystal growth;

ii) during epitaxy;
iii) by diffusion;
iv) by ion implantation.

The first two techniques produce uniform, global doping in the films (i.e. across the entire
wafer). Diffusion and implantation are used to vary the dopant concentration locally.

7.1 Diffusion
Diffusion is the movement of atoms from high-concentration regions to areas of lower
concentration. In semiconductor device fabrication, diffusion is a technique to drive dopants
such as boron, phosphorus, arsenic, etc. into the silicon lattice.

The process is carried out at temperatures in the range of 900ºC – 1200ºC in furnaces identical to
those used for thermal oxidation. The wafers are simply exposed to a gas with dopants. The
dopant source can be either gas or solid. For gas source diffusion, the most common doping
gases for phosphorus and boron are POCl3 and BBr3, respectively. For solid source diffusion, the
dopants are in wafer form. These are simply placed next to the target wafer.

Doping masks can be used to dope only selected regions on the wafer:

Diffusion doping through a mask

Doping profile

The concentration dependent diffusion flux j is given by Fick’s law:

𝛿𝑁
𝑗 = −𝐷 ( )
𝛿𝑥

where D is the diffusion coefficient in (cm2·s-1), N is the concentration in (cm-3) and x is the
diffusion length. The diffusion coefficient is a function of the dopant frequency factor D0 and
activation energy Ea (material properties):

𝐸𝑎
𝐷 = 𝐷0 exp (− )
𝑘𝑇
where k is Boltzmann’s constant, k = 1.38 × 10-23 (J/K) or 8.62 × 10-5 (eV/K), and T is the
temperature in (K).

The diffusion length or junction depth xj can be approximated as a function of D and the
exposure time as follows:

𝑥𝑗 ≈ 2√𝐷𝑡

The concentration profile of the dopant follows a complementary error function distribution
(erfc), i.e. it features a strong peak at the surface:

𝑥
𝑁(𝑥, 𝑡) = 𝑁0 erfc ( )
4𝐷𝑡

where N0 is the dopant concentration at the surface, which does not change as long as more
dopant is always available.

7.2 Ion Implantation

In doping by ion implantation, accelerated ions hit the silicon wafer, penetrate into the silicon
and slow down through collisions before coming to rest. This is the main doping method for
current CMOS fabrication processes. The sideways spreading of doping by ion implantation is
much better than diffusion, therefore, lateral doping profiles can be controlled much better.
This is important in advanced CMOS where dimensions are small!

A typical implanter setup is shown in the figure. The doping gas (e.g. PH3, BF3, AsH3) is loaded
and passed through in ion source. The ion source has a heating filament which breaks up the gas
into positively charged ions (e.g. P+, B+, As+), which are ejected from the ion source towards a
mass analyser by a 40 kV voltage. The mass analyser selects the desired ions by adjusting a
magnetic field so that only the desired mass-to-charge ions are redirected to the acceleration
tube, where they are accelerated to the desired implantation energy before they are finally
directed towards the wafer. High vacuum is important in order to minimise collisions. This is a
slow process because the beam (a few millimetres wide) must be scanned across the wafer. A
Faraday cage is used to monitor the delivered implantation dose.
 Schematic of an implanter

Masks

Patterned photoresist, oxides and nitrides can be used as implant masks. Photoresist is suitable
for a wide range of implantation energies. However, incorporation of photoresist into the wafer
can happen during implantation, so a thin oxide layer is usually grown before applying the
resist in order to prevent resist incorporation in the wafer.

Oxide or nitride mask are used for high energy implantation since photoresist is not sufficiently
opaque to high energy bombardment.

Doping profile

The ions reach the wafer surface at high energy but they are slowed down by collisions with
atoms in the film. Collisions produce a stochastic scattering of the entering ions which results in
a Gaussian distribution of ions in the wafer. The depth with maximum ion concentration (the
Gaussian peak) is known as projected range Rp. The straggle p is the deviation in the range in
the implantation direction, i.e. the width of the doping profile. The lateral straggle ⊥ is the
range deviation in a direction perpendicular to the implantation direction. Rp, p and ⊥ are
shown in the figure.

Projected range Rp, projected straggle p and lateral straggle ⊥

The doping distribution as a function of depth can be calculated with the following expression:

2
(𝑥 − 𝑅𝑝 )
𝑁(𝑥) = 𝑁0 exp (− )
2 𝜎𝑝 2
where x is the distance from the surface and N0 is the peak doping concentration, which is a
function of the implantation dose S (in ions/cm2)

𝑆
𝑁0 =
√2𝜋 𝜎𝑝

Finally, the junction depth xj can be calculated as:

𝑁0
𝑥𝑗 = 𝑅𝑝 − 𝜎𝑝 √2 ln
𝑁𝐵

where NB is the background doping level of the substrate.

Channelling

Channelling occurs when the incident ions align with a major crystallographic direction and find
a clear path through the atomic array. The result of this effect is a deeper ion penetration since
collisions are less likely. An example of a clear trajectory that implanted ions can follow is the
view of the silicon lattice along the <110> direction, shown in the figure (left). The graph
compares the doping profile resulting from channelling (solid line with black dots) with a
normal Gaussian profile (dotted line). Channelling results in an exponential tail of the doping
profile.

Left: silicon structure viewed along the <110> axis. Right: doping
profile due to channelling

Channelling can be reduced by:

a) tilting the wafer at about 7º to the beam in order to prevent the ions from entering the
channels; or
b) growing a thin amorphous layer (e.g. SiO2) on top of the semiconductor in order to deflect the
ions trajectories before entering the lattice.

Implant damage and annealing

When ions enter the semiconductor substrate, a series of collisions with the lattice atoms
reduces their energy until they stop. If collisions are nuclear (i.e. between the nucleus of the
incident ion and the nucleus of the host atom) the host atom may be displaced from its lattice
site. Moreover, upon collision the displaced atom may have acquired sufficient energy to
displace another lattice atom. The result is a damaged lattice. The damaged region extends from
the surface to depths beyond the implantation projected range. Damage creation depends on:

 implant species (heavy ions produce more damage)

 energy (more energy produces more damage)
 dose (more dose produces more damage)

If the implantation dose are too high (S > 1014 cm-2), crystallinity in the semiconductor may be
completely lost. Below doses of 1014 cm-2, lattice vacancies and interstitials are the predominant
damage type and they can be repaired.

Since poor crystallinity will affect the electrical properties of the semiconductor (low mobility of
electrons and holes), the damage must be repaired. High temperature annealing is used to
recrystallise the semiconductor. In addition, annealing will activate the dopants since must
implanted ions are not located in substitutional sites. The high temperature will then restore the
crystal and incorporate the implant ions into the lattice so they become electrically active.

Furnace annealing
Annealing is commonly carried out in a multi-zone hot wall furnace (similar to those used for
thermal oxidation and diffusion doping). High-purity gases (Ar or N2) are introduced to control
the environment.

Rapid thermal annealing

This method is faster than furnace annealing as it can heat the wafers up to 600ºC – 1100ºC in a
few milliseconds. The processing chamber is made of either quartz, silicon carbide or stainless
steel. Quartz windows allow the optical radiation to pass. Tungsten filaments or high power
halogen lamps are used as radiation sources. The wafers are heated up by radiation (as opposed
to convection in furnace annealing). The heating depends on the relative proportion of
absorption and reemission of energy by the wafer. These processes generally depend on the
surface properties of the wafer. Therefore regions with metal might heat quicker than those
without metal. In addition, wafers at different process stages might require different amounts of
power to get to the same temperature. Since the process is fast, it is difficult to measure the
temperature. However, A pyrometer measures the spectrum of light emitted by the backside of
the wafer. As the spectrum of radiation emitted by silicon at various temperatures is well
understood, the pyrometer is able to determine the wafer temperature reasonably well.