LECTURE 4

Nagia ali
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C O M B I N AT I O N A L C I RC U I T S
• Logic circuits for digital systems
– Combinational

– Sequential

• A combinational circuit
– outputs at any time are determined from the present
combination of inputs.
– Performs operation specified by a set of Boolean functions.

23 October 2024 INTRODUCTION TO LOGIC DESIGN

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OUTLINE OF CHAPTER 1

Combinational
Circuits

Binary Comparator Decoders Encoders Multiplexers

Binary Adder
Multiplier

23 October 2024 LOGIC DESIGN

1.1 COMBINATIONAL
CIRCUITS
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C O M B I N AT I O N A L C I RC U I T S
• Combinational circuit consist of
– Input variables

– Logic gates
• Accept signals from the inputs
• Generate signals to the output

– Output variables

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DESIGN PROCEDURE
• For a given a problem statement:
– Determine the number of inputs and outputs

– Derive the truth table

– Simplify the Boolean expression for each output

– Produce the required circuit

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DESIGN PROCEDURE
Code conversion example
• Code converter is a circuit that makes the two systems
compatible even though each uses a different binary code.
• To convert from binary code A to binary code B;

Input: Output:
supply the bit generate the
combination of Combinational corresponding
elements Circuit bit
specified by code combination
A of code B.

23 October 2024 INTRODUCTION TO LOGIC DESIGN

1.4 BINARY ADDER -

Nagia ali
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B I N A RY A D D E R - 1
• The most basic arithmetic operation is the addition of two binary digits.
• Simple addition consists of 4 possible elementary operations:
– 0+0=0

– 0+1=1

– 1+0=1

– 1 + 1 = 10

• First 3 operations produce a sum of one digit.

• In the 4th operation, the binary sum consists of two digits.

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B I N A RY A D D E R - 1
x y C S
Half Adder
0 0 0 0
• Adds 2 bits
0 1 0 1
– 2 inputs
1 0 0 1
– 2 outputs
1 1 1 0
• Produces SUM and CARRY.
S= + xy’
x’y
C=
x SUM xy
HA (S)
y CARRY
(C)

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B I N A RY A D D E R - 1
Half Adder
x
S = x’y + xy’ y’
x
C = xy S S
y
x’
y
C

x
C
y (b) S =x⊕ y, C =xy

(a) S =xy’+x’y, C =xy

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B I N A RY A D D E R - 1
x y z C S
Full Adder
0 0 0 0 0
• Adds 3 bits
0 0 1 0 1
– 3 inputs
0 1 0 0 1
– 2 outputs
0 1 1 1 0
• Produces SUM and CARRY. 1 0 0 0 1
x 1 0 1 1 0
SUM
y FA (S)
z CARRY 1 1 0 1 0
(C)
1 1 1 1 1
S= + + +
x’y’z x’yz xy’z’ xyz
C= + + +
x’yz xy’z xyz’ xyz
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B I N A RY A D DC E=Rx ’ -y z1+
S = x’y’z + x’yz + xy’z’ + xy’z + xyz’ +
xyz xyz

S = x ⊕y ⊕ z

y y
yz yz
x x
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 0
1 1 1
m4 m5 M7 m6 m4 m5 M7 m6
x 1 x 1
1 1 1 1 1

z z xz+ yz
C = xy+

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B I N A RY A D D E R - 1
Full adder implementation:
x’
y’
z

• S = x’y’z + x’yz + xy’z’ + xyz x’

y
z’

S x
• S = x ⊕y ⊕ z x
y’
y S
z’ S
z
• C = x’yz + xy’z + xyz’ + xyzx x
y
y z x
•
x
C = xy + xz + yz z y y

x
z
x
y C
z

x
C y
z
z
C

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23 October 2024 INTRODUCTION TO LOGIC DESIGN

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23 October 2024 INTRODUCTION TO LOGIC DESIGN

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23 October 2024 INTRODUCTION TO LOGIC DESIGN

1.5 MAGNITUDE
COMPARATOR
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M AG N I T U D E C O M PA RAT O R
• Compare two numbers (A and B)
• 3 outputs <, =, >
– A > B, A = B, A<B

• Consider compare 4-bit number to 4-bit number

A3 A2 A1 A0
– A = A 3 A2 A1 A0 B3B2B1B0

– B = B 3 B2 B1 B0 Magnitude
Comparator

A>B A=B A
23 October 2024
<B
INTRODUCTION TO LOGIC DESIGN
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M AG N I T U D E C O M PA RAT O R
• A = B if:
– A3 = B3 AND A2 = B2 AND A1 = B1 AND A0 = B0
Ai Bi xi (A = B) x3 = A3’ . B3’ + A3 . B3
0 0 1
x2 = A2’ . B2’ + A2 . B2
0 1 0
x1 = A1’ . B1’ + A1 . B1
1 0 0
1 1 1 x0 = A0’ . B0’ + A0 . B0

x i = A i’ . + A i . B i
Bi’
x = x3 . x2 . x1 . x0 = (A
= B)
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M AG N I T U D E C O M PA RAT O R
• A > B if
– Ai = 1 and Bi = 0
Ai Bi yi (A > B) y3 = A3 . B3’
0 0 0
y2 = x3 . A2 . B2’
0 1 0
y1 = x3 . x2 . A1 . B1’
1 0 1
1 1 0 y0 = x3 . x2 . x1 . A0 . B0’

yi = A i .
Bi’
y = y3 + y2 + y1 + x0 = (A
> B)
23 October 2024 INTRODUCTION TO LOGIC DESIGN
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M AG N I T U D E C O M PA RAT O R
• A < B if
– Ai = 0 and Bi = 1
Ai Bi zi (A < B) z3 = A3’ . B3
0 0 0
z2 = x3 . A2’ . B2
0 1 1
z1 = x3 . x2 . A1’ . B1
1 0 0
1 1 0 z0 = x3 . x2 . x1 . A0’ . B0

z i = A i’ .
Bi
z = z3 + z2 + z1 + z0 = (A
< B)
23 October 2024 INTRODUCTION TO LOGIC DESIGN
1.6 DECODERS
 24

DECODERS
• Discrete quantities of information are represented in digital
systems by binary codes.
• A binary code of n bits is capable of representing up to 2n
distinct elements of coded information.
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique
output lines.

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DECODERS
Only one
• Example: 2-bit binary number lamp will
turn on!

1
0 1
0
0
1
x1 Binary
0
1 0
1
Decoder
0
1
x0
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DECODERS
• 2-to-4 Line Decoder D3
D

Decoder
A D2
Binary
3
D
B D1
2
D
A B D0 D11 D2 D3 D0
0 0 1 0D 0 0 D3= A’B’
0
0 1 0 1 0 0 D2= A’B A
1 0 0 0 1 0 D1= AB’ B
1 1 0 0 0 1 D0= AB
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DECODERS
• 3-to-8 Line Decoder (Binary to Octal Conversion)
x y z D0 D1 D2 D3 D4 D5 D6 D7
D
0 0 0 1 0 0 0 0 0 0 0
7
0 0 1 0 1 0 0 0 0 0 0
Decoder D 0 1 0 0 0 1 0 0 0 0 0
x
Binary

6 0 1 1 0 0 0 1 0 0 0 0
y D 1 0 0 0 0 0 0 1 0 0 0
z
5 1 0 1 0 0 0 0 0 1 0 0
D 1 1 0 0 0 0 0 0 0 1 0
4 1 1 1 0 0 0 0 0 0 0 1

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DECODERS
• 3-to-8 Line Decoder (Binary to Octal Conversion)
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0 D0= x’ y’
0 0 1 0 1 0 0 0 0 0 0 z’
D1= x’ y’
0 1 0 0 0 1 0 0 0 0 0 z
D2= x’ y
0 1 1 0 0 0 1 0 0 0 0 z’
D3= x’ y
1 0 0 0 0 0 0 1 0 0 0 z
D4= x y’
1 0 1 0 0 0 0 0 1 0 0 z’
D5= x y’
1 1 0 0 0 0 0 0 0 1 0 z
D6= x y
1 1 1 0 0 0 0 0 0 0 1 z’
D7= x y z

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DECODERS
• 3-to-8 Line Decoder (Binary to Octal Conversion)
D7 D7= x y z
D6 D6= x y
D5 z’
D5= x y’
D4 z
D4= x y’
D3 z’
D3= x’ y
D2 z
D2= x’ y
D1 z’
D1= x’ y’
D0 z
D0= x’ y’
z’
x
y
z
23 October 2024 INTRODUCTION TO LOGIC DESIGN
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DECODERS
D7 Example: Full Adder
D6
D5 S(x, y, z) = ∑(1, 2, 4, 7)
Decoder
x x
Binary

D4
y y C(x, y, z) = ∑(3, 5, 6, 7)
D3
z z
D2
D1
D0

S
C
23 October 2024 INTRODUCTION TO LOGIC DESIGN
1.6 ENCODERS
 32

ENCODERS
• An encoder is a digital circuit that performs the inverse
operation of a decoder.
• An encoder has (or fewer) input lines and n output lines.
• The output lines generate the binary code corresponding to
the input value.

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ENCODERS
• Example: 4-to-2 Binary Encoder Only one switch should
be activated at a time
x1
x4 x3 x2 y1 y0
y1
x2 x1
Binary y0 0 0 0
x3 Encoder 0 0
1
x4 0 0 1
0 1
0
0 1 0
1 0
23 October 2024
0
INTRODUCTION TO LOGIC DESIGN
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ENCODERS
• Example: Octal-to-Binary Encoder
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Y2 Y 1 Y 0
Y2= D7+D6+D5+D4
0 0 0 0 0 0 0 1 0 0 0
Y1= D7+D6+D3+D2
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0 Y0= D7+D5+D3+D1
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
23 October 2024 INTRODUCTION TO LOGIC DESIGN
1.7 MULTIPLEXERS
 36

M U LT I P L E X E R S
• A multiplexer (MUX) is a
combinational circuit that selects
A
binary information from one of

MUX
B
Q=
Q
many input lines and directs it to a
C C
B
D
A
single output line.
D
• The selection of a particular input
line is controlled by a set of S0 S1
1
0 01
selection lines.
• There are 2n input lines and n
selected lines.

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M U LT I P L E X E R S
• 4-to-1 Multiplexer
A
S0 S1 Q
A MUX
0 0 A B
B
Q=
Q Y
C C
B
D
A
0 1 B C
D
1 0 C
D
1 1 D
S0 S1
1
0 01

S1 S0

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M U LT I P L E X E R S
• Example: F(x, y) = ∑ (0, 1, 3)
x y F 1 I0
0 0 1 1

MUX
I1 D F
0 1 1 0
I2
1 0 0 1
S1 S0
1 1 1 I3
xy

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M U LT I P L E X E R S
• Example:F(x, y, z) = ∑(1, 2, 6, 7)
x y z F
0 0 0 0
0 0 1 1
F=z
0 1 0 1
z I0
0 1 1 0
F = z’ z’ I1
MUX Y
1 0 0 0
0 I2
1 0 1 0
F=0 1 I3 S1 S0
1 1 0 1
F=1
1 1 1 1 x y
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M U LT I P L E X E R S
• Example:F(A, B, C, D) = ∑(1,3,4,11,12,13,14,15)
A B C D F
0 0 0 0 0
F=D D I0
0 0 0 1 1
0 0 1 0 0 D I1
0 0 1 1 1 F=D
0 1 0 0 1 D’ I2
0 1 0 1 0 F = D’
0
0
0
1
1
1 0
1 1
0
0 F=0 I3 MUX Y F
0
1
1
0
0
0 0
0 1
0
0 F=0 D
I4
1 0 1 0 0
1 0 1 1 1 F=D 1 I5
1 1 0 0 1
1 1 0 1 1 F=1 1 I6
1 1 1 0 1 S2 S1 S0
1 1 1 1 1 F=1 I7
A B C
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D E M U LT I P L E X E R S
Y3 Y3
Y
I DeMUX 2
Y1 Y2
S1 S0 Y0 I
Y1

S1 S0 Y3 Y2 Y1 Y0 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0 S1
1 1 I 0 0 0 S0

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D E M U LT I P L E X E R
Y3

Decoder
D3
A

Binary
Y D2
I DeMUX 2 B
Y1 D1
E
S1 S0 Y0 D0
E A B Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 X X 0 0 0 0

0 0 0 0 0 I 1 0 0 0 0 0 1

0 1 0 0 I 0 1 0 1 0 0 1 0

1 0 0 I 0 0 1 1 0 0 1 0 0

1 1 I 0 0 0 1 1 1 1 0 0 0

23 October 2024 INTRODUCTION TO LOGIC DESIGN