7.advanced Concepts
7.advanced Concepts
Concepts
Race Around Condition
• When two expressions are scheduled to
execute at same time, and if the order of the
execution is not determined, then race
condition occurs.
module race; module race;
reg out; reg out;
reg in; reg in;
initial initial
begin begin
in = 1; in = 1;
#1 out <= in; out <= in;
$display(out); $display(out);
end end
endmodule endmodule
Types Of Race Condition
1. Write-write Race
It occurs when same register is written in
both the blocks.
EXAMPLE:
always @(posedge clk)
a = 1;
always @(posedge clk)
a = 5;
2. Read-Write Race:
It occurs when same register is read in
one block and writes in another.
EXAMPLE:
always @(posedge clk)
a = 1;
always @(posedge clk)
b = a;
module test ;
reg a; Active Region
a=x
T1 a=0
initial a=0; //T1
endmodule
NBA and postponed
regions
What is the output ?
module test; Active region
reg a,b; a=1;b=0;
Samples value of b in the active region.
Executes $display in the active region.
NBA Region
a<=2
Postponed Region
initial begin $strobe(a)
$strobe ("Strobe a=%0d
",a);
a=1;
a<=2;
end
endmodule
What is the
output ?
module test;
reg [2:0] a;
NBA Region
initial begin
a <= 0;
a <= 0; a <= 1;
a <= 1; Final value of a is 1
end
endmodule
module test1;
reg [1:0]a,b,c;
initial
begin
a = 1; //blocking //R1
$display($time,"D",a);//2 //R1
a <= 2; // nonblocking //R3
$monitor($time,"M",a);//R4
$strobe($time,"M",a);//R4
end
endmodule
module test2;
reg [1:0]a;
Initial begin:B1 //1. if it executes same time
//2. if it executes in same region
a=1;//R1 //3. if it happens to same variable
//4. different execution gives
end different outputs
initial begin:B2
a=2;//R1
end
initial $monitor(a);
endmodule
File Handling
Note:
Here ‘t1’ is a file handle(which should be declared as
integer in test bench) to access the file called
“abc.txt”.
Opening a file
Syntax:
$fdisplay(<file_handle>,”<data_name>”,<data>);
Ex:
repeat(100) begin //writing into file abc.txt
a = $random;
$fdisplay(t1,"a ",a);
end
Note:
Here ‘t1’ is a file handle to the file abc.txt data (i.e., a)will be shown in abc.txt file after
simulation.
Random number generated using system task are given to a for 100 times.
These 100 times “abc.txt” file will be written with random values of ‘a’.
Closing a file
After writing is over we have to close the file
properly otherwise data won’t be saved inside the
file.
To close a file we have a task called $fclose.
For every $fopen task there should be a $fclose task.
Syntax:
$fclose(<file_handle>);
Ex: $fclose(t1);
Example
module tb_add(); //TestBench code start
reg [15:0] a;
reg [15:0] b;
wire [16:0] c;
initial
begin
t1=$fopen("xyz.txt");
t2=$fopen("abc.txt");
t3=$fopen("iam.txt");
begin
a = $random;
$fdisplay(t1,"a",a);
b = $random;
$fdisplay(t2,"b",b);
$fdisplay(t3,"c",c);
end
$fclose(t1);
$fclose(t2);
$fclose(t3);
End
end module
Initializing Memories
In verilog we can read some data from a file and
load to a specific memory.
Syntax:
$readmemb(“file_name”,<memory_name>);
$readmemb(“file_name”,<memory_name>,<start
_addr>);
$readmemb(“file_name”,<memory_name>,<start
_addr>,<end_addr>);
Initializing Memories Example
initial
begin
$readmemb(“init.txt”,memory); // read file which contains
binary values and store into memory
end
endmodule
Note:
Here init.txt contains the intialization data.
Addresses are specified in the file with @<address>.
Data is separated by white spaces from each other.
Initializing Memories Example
Example for writing initialization data file
----------------------------------
@0002//hexadecimal address
11111111 00000000//two data
01010101 10101010//next two data
-----------------------------------
It means from address location 0002, data are
available for initialization.
Different Types of Test Benches
1. Direct Test Bench
2. Randomization based Test Bench
3. Task Based Test Bench
4. File Based Test Bench
5. Self-Checking Test Bench
Direct Testbench or Linear
Testbench
initial
begin
# 10 wr = 0; address = 100 ; data = 10;
# 10 address = 101 ; data = 11;
# 10 address = 102 ; data = 12;
# 10 address = 103 ; data = 13;
# 10 address = 104 ; data = 14;
end
Randomization based Test Bench
initial
Begin
#10; wr = 0;
#10; addr = $random; data =
$random;
end
Task Based Testbench
task write (input reg[2:0] address,input reg[7:0]
data_in);
begin
@(posedge clk);
wr =0;
address = $random;
data_in = $random;
end
endtask
task read (input reg[2:0]
address,output reg[7:0]
data_in);
begin
@(posedge clk);
wr =1;
address = $random;
data_in = $random;
end
endtask
• Task calling
initial begin
repeat(10) begin
write($random,$random);
read($random,data_in);
end
end
File Based Testbench
initial begin
#10; rst = 0;
file1 = $fopen("mem_ram.txt"); // file opening
repeat(3) begin
wr = 0;
#10; address = $random;
#10; data_in = $random;
#100; wr = 1;
$fdisplay(file1,"address=%0h,data_in=%0h,wr =%0b",address,data_in,wr);
end
$readmemb("file1",ram);
$fclose(file1);
end
endmodule
Self- Checking TestBench
module dec_tb;
reg [2:0]a;
wire [7:0] y;
dec_dut uut (.a(a),.y(y));
initial
begin
memory [0] = 00000001;
memory [1] = 00000010;
memory [2] = 00000100;
memory [3] = 00001000;
memory [4] = 00010000;
memory [5] = 00100000;
memory [6] = 01000000;
memory [7] = 10000000;
end
initial
begin
repeat(16)
begin
#10; a= $random;
end
end
always @(y)
begin
if (memory[a] == y )
$display("test case passed for a=%b,y=%b",a,y);
else
$display("test case passed for a=%b,y=%b",a,y);
end
endmodule
THANK YOU