MOSFET

Channel Length Modulation

• The inversion layer charge QI • We can approximate the inversion
represents the total mobile electron layer charge at the drain end by QI at
charge on the surface and its x=L=0 (even though this is not quite
expression at the source end of the true)
channel is: • When VDS=VDSAT, the channel is
• QI at x=0=-Cox(VGS-VT0) and the pinched off at the drain end.
inversion layer charge at the drain • Further increase of the drain-to-
end of the channel is expressed as: QI source voltage (VDS>VDSAT) results in
at x=L=-Cox(VGS-VT0-VDS) even a larger pinched-off portion of
• At the edge of saturation when the the channel.
drain-to-source voltage reaches • The effective channel length is
saturation (VDS=VDSAT=VGS-VT0) the reduced to: L’=L-L where L is the
inversion layer charge at the drain length of the channel where QI=0.
end becomes zero. • The pinch-off point moves from the
drain end of the channel towards the
source end with increasing VDS.
 Channel Length Modulation
• For L’<x<L the channel voltage is • The effective channel length for
Vc at x=L’=VDSAT. the MOSFET operating in
• The electrons traveling from saturation is now L’ and the
source to drain traverse the above equation accounts for the
inverted channel segment of actual shortening of the channel.
length L’ and then they are • Shortening of the channel is also
injected into the depletion region known as channel length
of length L that separates the modulation.
pinch-off point from the drain • If L’ is replaced by L in the
edge. equation we can show that the
• The gradual channel computed saturation current using
approximation is valid in this L’ is greater than the new IDSAT
region and is given by: computed using L.
IDSAT=(nCox)/2(W/L’)[VGS-VT0]2
 Channel Length Modulation
• We must modify the equation for • Let 1-L1-VDS, with  being
saturation current so that it an empirical model parameter
reflects the dependency on VDS. called the channel length
Note that the saturation current modulation coefficient.
will increase with increasing VDS • Assume that VDS<<1 then the
since L’ decreases with increasing
saturation
C W
current becomes:
VDS. I DSAT  n ox
VGS  VT 0 2 1  VDS 
  2 L
 1 C W
I DSAT   n ox VGS  VT 0 2
 1  L  2 L • The above equation can be used
 L 
with sufficient confidence for
• The first term of the equation most first order hand calculations
accounts for the channel length
modulation effect.
L  VDS  VDSAT
 The Threshold Voltage
• Any gate-to-source voltage less than • Increasing the gate-to-source voltage
VT0 is not sufficient to establish an above and beyond VT0 will not affect
inversion layer. the surface potential and the depletion
• The MOSFET conducts no current region depth.
between its source and drain • There are 4 physical properties that
terminals unless VGS is greater than affect the threshold voltage namely (i)
VT0. the work function difference between
the gate and the channel, (ii) the gate
Oxide (SiO2) voltage component to change the
P-type Semiconductor (Si)
Metal (Al) surface potential, (iii) the gate voltage
Ec component to offset the depletion
Ei
region charge and (iv) the voltage
F
2F
F
EFp component to offset the fixed charges
qVT0
Ev in the gate oxide and in the silicon
oxide interface.
 The Threshold Voltage
• The work function difference • The depletion region charge
(gate-to-channel) reflects the built in density at surface inversion (S =
potential of the MOS structure -F) is QB0=-(2qNASi|-2F|)-1/2
which consists of the p-type • Assuming that the substrate is
substrate, the thin silicon dioxide biased at a different voltage level
layer and the gate electrode. than the source (at ground) then
• GC = F(substrate) –M if the the depletion region charge
gate material is metal density can be expressed as a
(Aluminum) function of the source-to-body
• If polysilicon is the gate material: voltage VSB: QB=-(2qNASi|-2F|+
GC = F(substrate) – F (gate) VSB)-1/2
• An externally applied voltage • The third component offsets the
must be changed to achieve depletion region charge and is
surface inversion i.e. to change equal to –QB/Cox (Cox=ox/tox).
the surface potential by -2F.
The Threshold Voltage
• The gate voltage that is necessary
to offset to the fixed positive
charge density Qox (at the
interface between the gate oxide
and the silicon substrate) is
–Qox/Cox.
• Combining all the voltage
components we can determine the
threshold voltage. For zero
substrate bias VT0 is given by:
VT0=GC-2F-QB0/Cox-Qox/Cox

• Thus determine the expression for

nonzero substrate bias.
 Body effect
• The most general form of the
threshold voltage is: VT=GC-
2F-Qox/Cox-QB/Cox VT VT 0      2 F  VSB  2 F 
• VT=VT0-(QB-QB0)/Cox

• (QB-QB0)/Cox=((2qNASi)-1/2)
/Cox*((|-2F+VSB|)-1/2-(|2F|)-1/2)
2qN A Si

C ox
• This becomes the most
general expression of the
threshold voltage with the
parameter gamma being:
 The Threshold Voltage
• Gamma is called the substrate- • Further differences:
bias or the body effect coefficient. – The substrate bias coefficient  is
• The general expression for the positive for nMOS and negative
threshold voltage can be used for for pMOS.
both the n-channel and p-channel – The substrate bias voltage VSB is
devices. positive in nMOS but negative
for pMOS.
• The differences are as follows:
• Typically the threshold voltage of
– Substrate Fermi potential F is
negative in nMOS but positive
an enhancement mode n-type
for pMOS. MOSFET is a positive quantity
– The depletion region charge
while that of a p-type MOSFET is
densities QB0 and QB are negative
negative.
for nMOS but positive for pMOS
 Sub-Threshold Conduction

• Ideally at VGS < VT, ID = 0. • What type of digital applications can

• The MOS device is partially benefit from this ultra low power
conducting for gate voltages below design approach?
the threshold voltage.
• This is termed sub-threshold or weak
inversion conduction.
• In most digital applications the
presence of sub-threshold current is
undesirable. Why?
• ….most digital applications …. Does
this mean some digital applications
can tolerate sub-threshold currents?
• A Sub-threshold digital circuit
manages to satisfy the ultra-low
power requirement. How?
 Subthreshold Conduction
• Below cut off current does not abruptly
become zero
Vgs  Vt Vds

nvT vT
I ds  I ds 0 e (1  e )

• Falls off exponentially I ds 0   v e 2 1. 8

T

• Useful in low power CMOS VLSI design

 Junction Leakage
• Conduction even
VD
when transistor is in vT
I D  I S (e  1)
cut-off
• Substrate to diffusion
junctions are reverse
biased
• However reverse
biased diodes do
conduct leakage
current
 Leakge Current
• When the junction bias voltage is
significantly more than the thermal voltage
(~26mV @room temperature) the leakage
current is –Is
• Junction leakage limits storage time in on-
chip memory elements
– Requires refreshing dynamic nodes
 Tunneling effects
• Ideal MOS model
– High input impedence
– No static current flow through the gate terminal
• Quantum mechanical effect
– Carriers “tunnel” through insulating barriers with finite
probability
– Insulating barrier has to be very thin for appreciable
current
• Current gate oxide thickness ~10-15Å
– Single atomic layer of silicon ~3Å
 Tunneling current
• Current technology nodes
– Tunneling current as significant as junction leakage
and sub-threshold conduction
• Technique to reduce tunneling current
– Use high-K materials in the gate oxide layer
• High dielectric constant makes high gate
capacitance
– Reduces the need to reduce the oxide thickness
– Silicon Nitride is a good candidate for such materials
 Temperature Effects
• Effect on Mobility T 
 k

• Carrier mobility  (T )   (Tr ) 

 Tr 
decreases with
temperature
• kµ is a parameter
usually in the range
1.2-2.0
 Temperature effects
• Threshold voltage
– Vt decreases linearly with increase in
temperature

• Junction leakage also increases with

increase in temperature
• All combined results in decrease of On
current and increase of Off current
 Temperature Issues
• Circuit performance is therefore generally worse at high
temperatures
• Conversely cooling can enable better performance
• Cooling techniques
– Convection
• Natural
• Fans
• Heat sinks
– Active cooling
• Water cooling
• Liquid nitrogen
• Cost of methods have to be justified
 Non-Ideal I-V Effects (Summary)
• Miniaturization has led to modern • The current IDS is lower than
devices having nonideal expected at high VDS.
characteristics • There are several sources of
• The saturation current increases leakage that result in current flow
less than quadratically with when the transistor is expected to
increasing VGS. be OFF.
• Velocity saturation and mobility • The source and drain diffusion
degradation are two of the effects regions are form reverse biased
that cause the non quadratic diodes which experience junction
current increase with VGS. leakage into the substrate or well.
• When carrier velocity ceases to • The current into the gate IG is
increase linearly with field ideal zero, however as gate oxide
strength we have velocity thickness is reduced electrons
saturation. tunnel through the gate, causing
some current.