0% found this document useful (0 votes)
4 views12 pages

Vlsi Design Engineer

The document presents an internship seminar on VLSI design, focusing on the development of a 4-bit Up/Down counter using Verilog and UVM for verification. It highlights the tools used, including EDA Playground and OpenROAD, and discusses the learning outcomes and career opportunities in the VLSI domain. The conclusion emphasizes the practical experience gained in the VLSI design flow and the application of industry-standard tools.

Uploaded by

leomary418
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
4 views12 pages

Vlsi Design Engineer

The document presents an internship seminar on VLSI design, focusing on the development of a 4-bit Up/Down counter using Verilog and UVM for verification. It highlights the tools used, including EDA Playground and OpenROAD, and discusses the learning outcomes and career opportunities in the VLSI domain. The conclusion emphasizes the practical experience gained in the VLSI design flow and the application of industry-standard tools.

Uploaded by

leomary418
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 12

Presentation Overview

⚬INTRODUCTION
⚬PROJECT
⚬LEARNING OUTCOMES
⚬CARRER OPPORTUNITIES
⚬FUTURE SCOPE
⚬CONCLUSION

03/06/2025 Internship Seminar Presentation 1


Introduction
VLSI (Very Large-Scale Integration)
• VLSI refers to the process of integrating millions (or billions) of transistors onto a single
silicon chip.

• It is the foundation of modern electronics, enabling the development of microprocessors,


memory chips, FPGAs, and SoCs (System on Chips).

• The VLSI design flow includes RTL design, functional verification, synthesis, physical
design, and layout generation.

• Used in applications such as mobile devices, IoT, AI processors, and communication


systems.

03/06/2025 Internship Seminar Presentation 2


TOOLS EXPOSED
1.EDA Playground
• Cloud-based platform for simulating Verilog/SystemVerilog code.
• Integrated simulators and waveform viewer (EPWave).
2. Ubuntu Environment
• Preferred OS for VLSI tool compatibility and performance.
• Used open-source tools like Yosys, Icarus Verilog, and GTKWave.
3. Aldec Riviera-PRO
• Industry-standard simulator for functional verification.
• Used for UVM testbench simulation and waveform analysis.
4. OpenROAD
• Open-source tool for complete RTL to GDS-II flow.
• Performed synthesis, placement, routing, and layout generation.
5. UVM Framework
• Enabled reusable and scalable testbench architecture.
• Supported constrained-random verification and functional coverage.
03/06/2025 Internship Seminar Presentation 3
PROJECT
Design of a 4-bit Up/Down counter using Verilog/System Verilog/VHDL
• Designed a 4-bit synchronous counter that counts up or down based on a control
signal.
• Implemented using Verilog HDL, verified using UVM, and layout generated using
OpenROAD.
i_rst i_up_down Previous Count New Count

• Inputs: i_clk, i_rst, i_up_down


1 X X 0000

0 1 0000 0001
• Output: o_count[3:0]
0 1 0001 0010

0 0 0010 0001

0 0 0001 0000

03/06/2025 Internship Seminar Presentation 4


PROJECT
// Code your design here
`timescale 1ns / 1ps
module up_down_counter #(
parameter WIDTH = 4 // Default 4-bit counter
)(
input wire i_clk, // Clock signal
input wire i_rst, // Active-high reset
input wire i_up_down, // Up/Down control (1 = Up, 0
= Down)
output reg [WIDTH-1:0] o_count // 4-bit counter output
);

always @(posedge i_clk) begin


if (i_rst)
o_count <= 0; // Reset counter to 0
else if (i_up_down)
o_count <= o_count + 1; // Count up
else
o_count <= o_count - 1; // Count down
end
endmodule
03/06/2025 Internship Seminar Presentation 5
PROJECT
EVALUATION CRITERIA FOR
BLOCK-LEVEL VERIFICATION IN
UVM

• This waveform validates the correct


operation of my 4-bit counter.
• Using UVM, I applied both up and
down counting sequences, observed
clean state transitions, and verified
functionality using assertions and a
scoreboard.
• The simulation passed with expected
results, confirming the correctness of
the design
03/06/2025 Internship Seminar Presentation 6
PROJECT
GENERATE GDS USING OPEN ROAD TOOL
In this section, the layout of the RTL code has been generated using the OpenROAD
software tool. Technology/Platform utilized: nangate45

03/06/2025 Internship Seminar Presentation 7


PROJECT
GENERATED GDS
• GDS-II layout view of your 4-bit
Up/Down Counter, generated using the
OpenROAD tool.
• The image above is the final layout (GDS-
II view) of the 4-bit Up/Down Counter,
showing standard cell placement, metal
routing for signals, and I/O pin
connections.
• This GDS layout was generated using the
OpenROAD tool and follows the
Nangate45 technology. It meets timing,
power, and area constraints and is ready
for fabrication.
03/06/2025 Internship Seminar Presentation 8
Learning from Internship
• Deep understanding of Verilog and RTL design.
• Hands-on experience with UVM architecture and verification techniques.
• Gained exposure to OpenROAD flow: synthesis to GDS-II.
• Improved debugging using waveform tools and assertions.
• Practical experience in timing, power, and area analysis.

03/06/2025 Internship Seminar Presentation 9


Career Opportunities in VLSI Domain
1. RTL Design Engineer
• Role: Write and debug Verilog/SystemVerilog code for digital logic blocks.
• Skills: Verilog, FSM design, synthesis, timing constraints.
2. Verification Engineer
• Role: Verify functionality of RTL designs using testbenches.
• Skills: SystemVerilog, UVM, assertions (SVA), code & functional coverage.
3. Physical Design Engineer
• Role: Convert synthesized netlist to layout (floorplanning → routing → GDS).
• Skills: OpenROAD, Cadence Innovus, clock tree synthesis, timing closure.
4. ASIC Design Engineer
• Role: Full custom or semi-custom chip development.
• Focus: High performance and power-optimized ICs.

03/06/2025 Internship Seminar Presentation 10


Future Scope
• Extend design to 8-bit/16-bit counters.
• Add low-power design techniques for mobile applications.
• Integration into larger systems like timers, ALUs, or controllers.
• Explore DFT and post-layout validation.
• Move towards ASIC tape-out using professional PDKs.

03/06/2025 Internship Seminar Presentation 11


Conclusion
• The internship has been an enriching experience that bridged the gap
between academic knowledge and practical industry application.
• Through the project on the 4-bit Up/Down Counter, I gained hands-on
experience in the entire VLSI design flow—from RTL coding using
Verilog, functional verification using UVM, to physical implementation
using OpenROAD.
• This opportunity not only enhanced my technical proficiency in digital
design and verification but also exposed me to industry-standard tools and
best practices. It strengthened my problem-solving abilities, debugging
skills, and understanding of key VLSI concepts such as timing closure,
area optimization, and power analysis.

03/06/2025 Internship Seminar Presentation 12

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy