Date:

Quiz for Chapter 4 The Processor

Name: Course:
olutions in !"# $. [6 points] For the MIPS datapath shown below, several lines are mar ed with !"#$ For ea%h one:

Des%ribe in words the ne&ative %onse'uen%e o( %uttin& this line relative to the wor in&, unmodi(ied pro%essor$ Provide a snippet o( %ode that will (ail Provide a snippet o( %ode that will still wor

)*+ Cannot write to re&ister (ile$ ,his means that -.t/pe and an/ instru%tion with write ba% to re&ister (ile will (ail$ 0n e1ample o( %ode snippet that would (ail is:
add $s1, $s2, $s3

0n e1ample o( a %ode snippet that will not (ail is:

Name: )2+ Forwardin& o( the (irst operand (ails$ 0n e1ample o( %ode snippet that would (ail is:
add $s1, $t0, $t1 add $s1, $s1, $s1

0n e1ample o( %ode snippet that will not (ail is:

)3+ 4umpin& to a bran%h tar&et does not wor $ 51ample o( %ode that (ails:
addi $s1, $zero, 2 addi $s2, $zero, 2 beq $s1, $s2, exit

Code that will still wor :

%. [3 points] Consider the (ollowin& assembl/ lan&ua&e

%ode:
0! 1! 2! 3! %! .! /! 9! <! "## )*+ "## 0#1 0#1 )61 "7# +3: "7# $% & $1 ' $0( $, & $3 - $%( $% & $. ' $/( $2 & 2324$3 ' 1005( $2 & 2324$2 ' 05( 2324$% ' 1005 & $2( $2 & $2 8 $1( $, && $1, 6ar;et( $, & $, 8 $1(

Consider a pipeline with (orwardin&, ha6ard dete%tion, and * dela/ slot (or bran%hes$ ,he pipeline is the t/pi%al 7.sta&e IF, ID, 5", M5M, 89 MIPS desi&n$ For the above %ode, %omplete the pipeline dia&ram below )instru%tions on the le(t, %/%les on top+ (or the %ode$ Insert the %hara%ters IF, ID, 5", M5M, 89 (or ea%h instru%tion in the bo1es$ 0ssume that there two levels o( b/passin&, that the se%ond hal( o( the de%ode sta&e per(orms a read o( sour%e re&isters, and that the (irst hal( o( the write.ba% sta&e writes to the re&ister (ile$ :abel all data stalls )Draw an " in the bo1+$ :abel all data (orwards that the (orwardin& unit dete%ts )arrow between the sta&es handin& o(( the data and the sta&es re%eivin& the data+$ 8hat is the (inal e1e%ution time o( the %ode;

Quiz for Chapter 4 The Processor Page 2 of 30

Name:

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

I0

I1

I2

I3

I4

I5

I6

I7

I8

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

I0

IF

!"

#! #

$%

I1

IF

!"

#! #

$%

I2

IF

!"

#! #

$%

Quiz for Chapter 4 The Processor Page 3 of 30

Name:
I3 IF I !" #! # $%

I4

IF

"

!"

#! #

$%

I5

IF

"

!"

#! #

$%

I6

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IF

!"

#! #

$%

I7

IF

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#! #

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I8

IF

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,he (inal e1e%ution time o( the %ode is *3 %/%les$

below are a series o( optimi6ation te%hni'ues implemented in a %ompiler or a pro%essor pipeline desi&ned to redu%e or eliminate stalls due to these ha6ards$ For ea%h o( the (ollowin& optimi6ation te%hni'ues, state whi%h pipeline ha6ards it addresses and how it addresses it$ Some optimi6ation te%hni'ues ma/ address more than one ha6ard, so be sure to in%lude e1planations (or all addressed ha6ards$ )a+ 9ran%h Predi%tion

It addresses %ontrol ha6ards b/ &uessin& the out%ome o( a bran%h instru%tion and then spe%ulativel/ e1e%utes the instru%tions on one side o( the bran%h to eep the pipeline movin&$ Predi%tions %an be made in hardware or in so(tware b/ the %ompiler$ )b+ Instru%tion S%hedulin& It addresses stru%tural ha6ards and data ha6ards$ It addresses data ha6ards b/ either movin& instru%tions that are not dependent on an instru%tion, sa/ 0, be(ore some instru%tions that depend on 0 and thus avoidin& the stall that would have o%%urred otherwise$ It addresses stru%tural ha6ards b/ ma in& sure instru%tions that use (un%tional units that have limited number o( instan%es are be s%heduled (ar apart (rom ea%h other and there is no unne%essar/ stall due to this$ It %an be done in hardware )supers%alar pro%essor+ or stati%all/ b/ the %ompiler )%+ dela/ slots It addresses %ontrol ha6ards$ It helps to avoid a stall that would result due bran%h tar&et identi(i%ation durin& the de%ode sta&e b/ s%hedulin& the e1e%ution o( some other instru%tion whi%h an/wa/ has to e1e%ute irrespe%tive o( the bran%h %ondition$

Quiz for Chapter 4 The Processor Page 4 of 30

Name: )d+ in%reasin& availabilit/ o( (un%tional units )0:<s, adders et%+ It helps to avoid stru%tural ha6ards$ It is possible to run multiple instru%tions o( the same t/pe at the same time i( we have repli%ated (un%tional units )e+ %a%hes It addresses data ha6ards$ In parti%ular, %a%hes help to redu%e memor/ laten%/ and hen%e redu%e the load.use laten%/ whi%h in turn redu%e the stall duration and improves e1e%ution time )b/ maintainin& pipeline stead/ state+$
'. [*= points] ,his is a three.part 'uestion about %riti%al path %al%ulation$ Consider a simple sin&le.

%/%le implementation o( MIPS IS0$ ,he operation times (or the ma>or (un%tional %omponents (or this ma%hine are as (ollows:
Component &'( &**er &'( Co)tro+ ()it ,hifter Co)tro+ ()it-./# ,ig)-zero e0te)*er 211 #(" #e2or3 4rea*-5rite6 4i)structio) or *ata6 PC .egister 4rea* actio)6 PC .egister 45rite actio)6 .egister fi+e 4rea* actio)6 .egister fi+e 45rite actio)6 'ogic 41 or 2ore +e7e+s of gates6 (atency 10 )s 8 )s 2 )s 3 )s 4 )s 3 )s 2 )s 15 )s 1 )s 1 )s 7 )s 5 )s 1 )s

Quiz for Chapter 4 The Processor Page 5 of 30

Name: 9elow is a %op/ o( the MIPS sin&le.%/%le datapath desi&n$ In this implementation the %lo% %/%le is determined b/ the lon&est possible path in the ma%hine$ ,he %riti%al paths (or the di((erent instru%tion t/pes that need to be %onsidered are: -.(ormat, :oad.word, and store.word$ 0ll instru%tions have the same instru%tion (et%h and de%ode steps$ ,he basi% re&ister trans(er o( the instru%tions are:
=etch>#ecode! nstr?ction @- 2324AB5( $-type! $4rd5 @- $4rs5 op $4rt5( AB @- AB ' %( load! $4rt5 @- #2324 $4rs5 ' si;next(offset)5( AB @- AB '%( store! #2324 $4rs5 ' si;next(offset)5 @- $4$t5( AB @- AB '%(

)Part *+

In the table below, indi%ate the %omponents that determine the %riti%al path (or the respe%tive instru%tion, in the order that the %riti%al path o%%urs$ I( a %omponent is used, but not part o( the %riti%al path o( the instru%tion )ie happens in parallel with another %omponent+, it should not be in the table$ ,he re&ister (ile is used (or readin& and (or writin&? it will appear twi%e (or some instru%tions$ 0ll instru%tion be&in b/ readin& the PC re&ister with a laten%/ o( 2ns$

,nstruction -ardware "lements .sed /y ,nstruction Type #u0&'( .1For2at .ea* I)structio) Co)tro+ .ea &'( * PC #e2or3 co)tro+ .ea* I)structio) Co)tro+ .ea* &'( #u0&'( 'oa* .eg co)tro+ PC #e2or3 .ea* I)structio) Co)tro+ .ea* &'( #u0ALU ,tore .egs co)tro+ PC #e2or3

#u0

Mux

Write regs

ata #u0 #e2or3 ata #e2or3

Mux

Write Sign regs extend

)Part /+
Quiz for Chapter 4 The Processor Page 6 of 30

Name: Pla%e the laten%ies o( the %omponents that /ou have de%ided (or the %riti%al path o( ea%h instru%tion in the table below$ Compute the sum o( ea%h o( the %omponent laten%ies (or ea%h instru%tion$
,nstruction Type -ardware (atencies 0or !espective 1 )s 15 4 )s 7 )s 2 )s )s 1 )s 15 4 )s 7 )s 2 )s )s 1 )s 15 4 )s 7 )s 2 )s )s "lements 2 ns 10 )s 2 ns 2 ns 10 )s 10 )s Total 2 )s 2 ns 5 ns 5 ns 3 ns

.1For2at 'oa* ,tore

15 )s 2 )s 2 ns 15 )s

<se the total laten%/ %olumn to derive the (ollowin& %riti%al path in(ormation: @iven the data path laten%ies above, whi%h instru%tion determines the overall ma%hine %riti%al path )laten%/+; 8hat will be the resultant %lo% %/%le time o( the ma%hine based on the %riti%al path instru%tion; 8hat (re'uen%/ will the ma%hine run;

,he load instru%tion determines the overall ma%hine %riti%al path laten%/ sin%e it has the ma1imum laten%/$ ,he %riti%al path (or the load instru%tion is PC A InstmemA -ead-e&sA Mu1 A 0:< ADadaMemAMu1A8rite-e&s B * A*7ACA2A*=A*7A2A7 B 7C ns ,he %lo% %/%le time should be lon& enou&h to permit the %riti%al path instru%tion to %omplete$ So it should be at least 7C ns ,he (re'uen%/ o( the ma%hine would be )*D7C+ ns B *C$7 ME6

Quiz for Chapter 4 The Processor Page 7 of 30

Name:

Quiz for Chapter 4 The Processor Page 8 of 30