Aim:

The aim of this project is to design a 3-bit even parity generator that can detect a one-bit error in a message and draw the CMOS layout in L- dit! which can then be simulated using "S"#C $

Abstract:
%n even parity bit generator generates an output of & if the number of '(s in the input se)uence is even and ' if the number of '(s in the input se)uence is odd$ The chec*er circuit gives an output of & if there is no error in the parity bit generated$ Thus it basically chec*s to see if the parity bit generator is error free or not$

Schematic:
The design procedure is made simple by writing the truth table for the circuit$ Truth table: Message X Y Z & & & & & ' & ' & & ' ' ' & & ' & ' ' ' & ' ' ' Even parity bit P & ' ' & ' & & ' Checker bit C & & & & & & & &

The circuit can now be derived by drawing the +-map for the output$

'

,rom this the minimal output e)uation is generator circuit is shown in ,igure '$

P = X Y Z + X Y Z + XYZ + X Y Z = X Y Z

This function can be implemented using e-clusive-or gates$ The schematic of the parity

Figure : Parity bit generat!r

Similarly

the

chec*er

circuit

can

be

designed

using

.O/

gates!

where

C = X Y Z P and the circuit is shown in ,igure 0$

Figure ": Checker circuit 1ow the parity bit generator and the chec*er circuit can be combined into one circuit for simplicity$ The final schematic of the circuit is shown in ,igure 3$

Figure #: C!mbine$ schematic !% b!th parity bit generat!r an$ checker circuit The final layout consists of four .O/ gates! which can be designed! in L- 2#T using the CMOS technology$ The basic building bloc*s in CMOS technology are MOS, T(s$ % MOS, T is a metal o-ide semiconductor field effect transistor$ The advantages of MOS, T over 34T(s are! they are smaller in si5e and the drain and source terminals are interchangeable$ This provides the designers with area minimi5ation on the chip$

S!%t&are use$:
'$ L- 2#T student version for drawing the layouts$ 0$ "S"#C for simulating the layouts$

'asic buil$ing bl!cks:

MOS, T(s are the basic building bloc*s$ There are three main components to a CMOS transistor$ The Source and 2rain can be interchanged at the silicon level and occasionally at the device level$ These are the main current carrying terminals$ The 6ate is separated from the Composite 7Silicon8 by a thin layer of SiO0! which acts as an insulator or dielectric$ #n the CMOS world you can create a Capacitor by shorting the Source and 2rain together calling that one terminal! and using the 6ate for the other terminal$ The difference between an 1MOS and a "MOS device depends on the type of 9 LL 7base8 the transistor is sitting in$The layout of a p-channel MOS, T drawn in Ldit is shown in ,igure :$ Layout of a MOS, T using L- dit is very straightforward$ %n n-channel device is constructed by creating an n; region ndiff defined by n$i%% ( )ACT*+E, %12 )-SE.ECT, % P/.Y over n$i%% creates the transistor$ The drawing steps for creating the n, T are as follows$ '$ Construct an ACT*+E bo-<polygon$ 0$ Surround ACT*+E with -SE.ECT$ The intersection of the two is n$i%%$ 3$ Create a P/.Y bo- that crosses completely over ndiff and e-tends beyond the ACT*+E area$ This creates the gate$ The actual drawing se)uence is not important$ =owever! all design rules should be obeyed$ ,igure : shows the layout of an nMOS, T structure$ errors in the layout design$ ach layer is drawn se)uentially obeying all the design rules and a 2/C is performed to chec* if there are any

Figure 0: nM/SFET ,igure > shows that nMOS, T is constructed rules$ without violating any design

Figure 1: 23C %ile %!r Figure 0 ,igure ? is the -traction definition file for the layout in ,igure :$

Figure 4: E5tract $e%initi!n %ile %!r lay!ut in Figure 0

>

% p-channel MOS, T follows the same basic order! e-cept that the n-well must be defined$ The steps are@ '$ Create an -6E.. region for the pMOS, T$ 0$ Construct an ACT*+E bo-<polygon for the transistor$ 3$ Surround ACT*+E with PSE.ECT$ The intersection of the two is pdiff$ :$ 2raw a P/.Y bo- over pdiff for the gate$ >$ "rovide an ACT*+E and -SE.ECT bo- within -6E.. for the n-well contact 7to A228 1ote that the n; contact formed in step > is needed to bias the n-well to the power supply voltage$ ,igure B shows the layout of a pMOS, T$ 2esign is constructed se)uentially by performing 2/C at each stage$

Figure 7: pM/SFET ,igure C shows the 2/C file for a pMOS, T$ %ll design rules are obeyed$

Figure 8: 23C %ile %!r Figure 7

,igure D shows the e-traction definition file for the layout in ,igure B$

Figure 9: E5tract $e%initi!n %ile %!r lay!ut in Figure 7 The definition files are e-tracted using the morbn0&$e-t file! which gives the information about the transistors and the corresponding nodes and parasitic capacitances$ This is used as a netlist in the "S"#C to generate the output waveform$

Pr!ce$ure:
%ny layout in L- dit can be drawn using these two transistors$ #n this project! four .O/ gates are needed which can be built from the basic transistors$ #t is important to understand the schematic of an .O/ gate$ % simple .O/ gate can be built using two inverters and two transmission gates$

CMOS Inverter:
The schematic of a CMOS inverter circuit is shown in ,igure '&$ #t consists of a p-, T and an n-, T connected bac* in the form of a complimentary pair$ The gates of the two transistors are connected to the input pulse and the inverted output pulse is obtained at the point where the source of the p-, T is connected to the drain of the n-, T$ 9hen the

input pulse is at & level! the p-, T turns O1 and the 2C voltage A 22 is observed at the output$ 9hen the input is at =#6= level! the n-, T turns O1 and the ground voltage & is observed at the output$

Figure :: CM/S *nverter The layout of an inverter in L- dit is shown in ,igure ''$ A22 "MOS

A#1

AOET

ASS Figure

1MOS : *nverter lay!ut

The $S"C file is e-tracted from this layout! which is shown in ,igure '0$ This file indicates that there are two transistors in the layout i$e$! M' and MC$ The line M' '' 3 '& "MOS indicates the nodes for the p-MOS, T in the order 2rain 6ate Source$ 3y observing the node numbers for both the transistors we can say that node 3 is the

common gate where the input pulse is to be given and node '& is the common point where output is obtained$ Aoltage A22 is given at node '' and A SS is given at node D$ 3y using this information a $C#/ file can be created wherein the values for these voltages are specified at corresponding nodes$

Figure ": ;SPC %ile %!r inverter The $cir file for an inverter is shown in ,igure '3$

Figure #: ;C*3 %ile %!r an inverter The lines A22 '' & 2C > and A612 D & 2C & indicate the voltages between the starting node and ending node and 2C specifies the type of voltage given$ The general format of these lines can be written as Node_ name starting_node ending_node voltage_type value The ne-t line in the $cir file indicates the pulse voltage given at the input$ The general format for this type of input is Node_ name starting_node ending_node PULSE (low_value high_value td tr t tp !" =ere td is the time delay! t r is rise time! tf is fall time! tp is the pulse width and T is the time period of the pulse$ L-edit consists of a file SC1%$S"C which defines the dot model parameters for the transistors$ This file has to be included in the $cir file$ Lastly! #!$%N &ns &'ns indicates the type of simulation i$e$! in this case it is the transient analysis$ The general format for this is #!$%N step_si(e simulation_time ,inally the #P$)*E line specifies the output probe in the layout$ This file is compiled in the "S"#C %F2$ The input and the output pulses are observed by running the probe in "S"#C $ The "S"#C simulation of the inverter is shown in ,igure ':$

Figure 0: PSP*CE simulati!n !% an inverter

'&

Transmission gate:
% transmission gate consists of a "MOS and an 1MOS connected in a way that input is transmitted in one condition and bloc*ed in other condition$ The schematic of a transmission gate is shown in ,igure '>$

Figure 1: Transmissi!n gate schematic The operation of a transmission gate is as follows@ when S is LO9! both "MOS and 1MOS are O,, and the input % is not transmitted to the other end$ 9hen S is =#6=! both "MOS and 1MOS are O1 allowing % to pass through the gate$ ,igure '? shows the layout of a transmission gate in L- dit$ S(

S Figure 4: .<E$it lay!ut !% transmissi!n gate

''

The e-traction and simulation steps are the same for every layout and thus are repeated for the transmission gate$ The $cir file and the "S"#C simulation of the transmission gate are shown in ,igures 'B and 'C respectively$

Figure 7: ;cir %ile %!r transmissi!n gate

Figure 8: PSP*CE simulati!n !% transmissi!n gate

'0

XOR gate using inverters and transmission gates:

The .O/ gate consists of two inverters and two transmission gates$ The schematic of .O/ gate is shown in ,igure 'D$

Figure 9: Schematic !% X/3 gate The layout of .O/ gate in L- dit is drawn by creating the basic cells$ The transistors are used as instances in drawing the layouts of inverter and transmission gates$ This feature is available in L- dit in the cell menu$ The cells are then flattened$ 1ow by using the inverter and transmission gate as instances the .O/ layout is completed$ ,igure 0& shows the layout of .O/ gate in L- dit$ Two inverters are used since we need both %( and 3( in the .O/ function$ The $C#/ file in ,igure 0' shows that there are C transistors in the .O/ gate$ The output of an .O/ gate is & when both the inputs are same$ This can be observed in the "S"#C simulation waveforms obtained for this layout$ The waveforms are shown in ,igure 00$

'3

3 %

% .O/ 3

Figure ":: .ay!ut !% X/3 gate in .<E$it

Figure " : ;C*3 %ile %!r X/3 lay!ut

':

Figure "": PSP*CE simulati!n !% X/3 lay!ut

C!mplete lay!ut !% the parity bit generat!r an$ checker circuit:

The layout of a parity bit generator<chec*er circuit consists of four .O/ gates$ Thus! .O/ cell is created which is used as instance to build the complete layout$ ach .O/ gate consists of C transistors! therefore the complete layout consists of 30 transistors$ The limitation of "S"#C student version software is that it cannot simulate more than '& transistors$ Thus the complete layout cannot be simulated with this version$ The e-tracted file for the layout shows that there are 30 transistors in the layout$ ,igures 03 and 0: show the L- dit layout and the e-tracted file for the project$

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Figure "#: .<E$it lay!ut !% parity bit generat!r=checker

G Circuit -tracted by Tanner /esearchHs L- dit A>$'3 < -tract A0$&? I G T23 ,ile C@J"%/#TK! Cell Cell&! -tract 2efinition ,ile C@JMO/310&$e-t I C'B ''D & 3'$0D',, C'C ''0 & 3'$0D',, C'D '&> & 3'$0D',, C0& DD & 3'$0D',, C3B '03 & 3&$3&3,, C3C '00 & 3&$3&3,, C3D '0' & 3&$3&3,, C:& '0& & 3&$3&3,, C:' ''C & ':$&?>,, C:0 ''? & ::$&C,, C:3 ''> & 0B$&>B,, C:: ''3 & '?3$:B3,, C:> ''' & ':$&?>,, C:? '&D & :C$3B0,, C:B '&C & 0B$&>B,, C:C '&? & 0&$DD?,, C:D '&: & ':$&?>,, C>& '&0 & ?&$??C,, C>' '&' & 0B$&>B,, C>0 DC & ':$&?>,, C>3 D? & 0B$&>B,, C>: D: & 0&$DD?,, M' ''D '&D ''C : "MOS LL0E 9L':E M0 ''3 '&D ''? B "MOS LL0E 9L'3E M3 ''> ''C ''? '' "MOS LL0E 9L'3E M: ''D ''3 ''> '> "MOS LL0E 9L':E M> ''0 '&0 ''' 'D "MOS LL0E 9L':E

'?

M? '&? '&0 '&D 00 "MOS LL0E 9L'3E MB '&C ''' '&D 0? "MOS LL0E 9L'3E MC ''0 '&? '&C 3& "MOS LL0E 9L':E MD '&> '&? '&: 33 "MOS LL0E 9L':E M'& ''3 '&? '&0 3? "MOS LL0E 9L'3E M'' '&' '&: '&0 :& "MOS LL0E 9L'3E M'0 '&> ''3 '&' :: "MOS LL0E 9L':E M'3 DD :B DC :C "MOS LL0E 9L':E M': D: :B ''3 >' "MOS LL0E 9L'3E M'> D? DC ''3 >> "MOS LL0E 9L'3E M'? DD D: D? >D "MOS LL0E 9L':E M>B '03 '&D ''C D3 1MOS LL0E 9L'3E M>C ''> '&D ''? D3 1MOS LL0E 9L'3E M>D ''3 ''C ''? D3 1MOS LL0E 9L'3E M?& '03 ''3 ''> D3 1MOS LL0E 9L'3E M?' '00 '&0 ''' D3 1MOS LL0E 9L'3E M?0 '&C '&0 '&D D3 1MOS LL0E 9L'3E M?3 '&? ''' '&D D3 1MOS LL0E 9L'3E M?: '00 '&? '&C D3 1MOS LL0E 9L'3E M?> '0' '&? '&: D3 1MOS LL0E 9L'3E M?? '&' '&? '&0 D3 1MOS LL0E 9L'3E M?B ''3 '&: '&0 D3 1MOS LL0E 9L'3E M?C '0' ''3 '&' D3 1MOS LL0E 9L'3E M?D '0& :B DC D3 1MOS LL0E 9L'3E MB& D? :B ''3 D3 1MOS LL0E 9L'3E MB' D: DC ''3 D3 1MOS LL0E 9L'3E MB0 '0& D: D? D3 1MOS LL0E 9L'3E $MO2 L 1MOS 1MOS L A LL0 L2L&$0>&&&&E TO.L:'B$&&&&&C -'& ; 1SE3L?$'&C?'D ;': ATOL&$C0>&&C +"L:$D'D&&& -&> 6%MM%L&$'B0 ; "=#L&$? EOL>D: E ."L?$?C00B> -&0 EC/#TL>&&& ; 2 LT%L>$&C3&C AM%.L?>>:B$3 .4L&$0>&&&&E L%M32%L?$?3?'DB -&3 ; 1,SL'$DC ;'' 1 ,,L' 1SSL'$&&&&&& ;'& T"6L'$&&&&&& ; /S=L30$B:&&&& C62OL3$'&>3:> -'& C6SOL3$'&>3:> -'& C63OL3$C:C>3& -'& ; C4LD$:D:D&& -&> M4L&$C:B&DD C4S9L:$:'&'&& -'& M4S9L&$33:&?& "3L&$C&&&&& $MO2 L "MOS "MOS L A LL0 L2L&$00B03?E TO.L:'B$&&&&&C -'& ; 1SE3L'$&>?'0: ;'? ATOL-&$D3B&:C +"L'$B3'&&& -&> 6%MM%L&$B'> ; "=#L&$? EOL0&D E ."L&$033C3' EC/#TL:B>&D$D ; 2 LT%L'$&B'BD AM%.L'&&&&& .4L&$0>&&&&E L%M32%L:$3D':0C -&0 ; 1,SL3$0B ;'' 1 ,,L'$&&' 1SSL'$&&&&&& ;'& T"6L-'$&&&&&& ; /S=LB0$D?&&&& C62OL0$C00>C> -'& C6SOL0$C00>C> -'& C63OL>$0D03B> -'& ; C4L3$00:0&& -&: M4L&$>C:D>? C4S9L0$DBD'&& -'& M4S9L&$3'&C&B "3L&$C&&&&& $T/%1 0ns 0&ns $"/O3 $ 12

Figure "0: ;C*3 %ile %!r the parity bit generat!r=checker

Applicati!n !% parity bit generat!r circuit:

"arity bit generator is used in digital communications where the messages are transmitted in the form of '(s and &(s$ #n communications! a message has to be transmitted between two points without any loss or errors$ This is done by chec*ing the message bits at the

'B

transmitter end and the receiver end$ % parity bit is generated at the transmitting end and is transmitted along with the message bits through the transmission channel$ %t the receiving end the parity bit is again generated and is chec*ed against the parity bit generated at the transmitter$ #f both are the same then the message is error free else the message is different from the transmitted message$ 1ote that this method only helps in detecting a one-bit error in message se)uence but it does not correct the message$ This is one of the many error detection methods used in digital communications$

3e%erences:
'$ "hysical 2esign of CMOS #ntegrated circuits using L- dit by 4ohn "$Eyemura$ 0$Circuit 2esign for CMOS ALS# by 4ohn "$Eyemura$ 3$http@<<users$ece$gatech$edu<Mrdanse< C 0&3&<slides< C 0&3&FChapter&?F0pp$pdf

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