1.

A 1-to-8 demultiplexer with data input Din, address input S0, S1, S2 (with S0 as the LSB) and
Y 0 to Y 7 as the eight demultiplexed outputs, is to be designed using two 2-to-4 decoders
(with enable input E̅ and address input A0 and A1) as shown in the figure. Din, S0, S1 and S2
are to be connected to P, Q, R and S but not necessarily in this order. The respective
input connections to P, Q, R and S terminals should be

a. S2, Din, S0, S1 b. S1, Din, S0, S2

c. Din, S0, S1, S2 d. Din, S2, S0, S1
2. Consider the circuit shown in the figure.
 The Boolean expression F implemented by the circuit is
a. X̅ Y̅ Z̅ + X Y + Y̅ Z b. X̅ Y Z̅ + X Z + Y̅ Z
c. X̅ Y Z̅ + X Y + Y̅ Z d. X̅ Y̅ Z̅ + X Z + Y̅ Z
3. How is a JK flip-flop made to toggle?
a. J = 0, K = 0 b. J = 1, K = 0
c. J = 0, K = 1 d. J = 1, K = 1
4. How many flip-flops are in 7475 IC?
a. 1 b. 2
c. 8 d. 4
5. How many flip-flops are required to produce a divide-by-128-device?
a. 1 b. 4
c. 6 d. 7
6. Counter is used for measuring ……….
a. voltage b. current
c. power d. frequency
7. How many NOT gates are required to design the RS flip-flop?
a. 1 b. 2
c. 3 d. 4
8. Which of the following IC is demultiplexer IC?
a. IC-7482 b. IC-7442
c. IC-74147 d. IC-74154
9. Number of data input in a multiplexer is
a. n b. 2n
c. 2n-1 d. n2
10. Which device is used as a frequency devider?
a. counter b. flip-flop
c. register d. all of these
11. The group register that store the binary information is called
a. memory b. shift-register
c. encoder d. decoder
12. The basic building block of a counter is
a. AND gate b. flip-flop
c. NOR gate d. NAND gate
13. How many flip-flops are required to build a binary counter circuit to count from 0 to
1023?
a. 6 b. 10
c. 24 d. 12
14. In flip-flop clock is present but in latch clock is
a. Always present b. always absent
c. may be present/absent d. none of the above
15. The invalid state of a NOR latch occurs when
a. S = 1, C = 0 b. S = 0, C = 1
c. S = 1, C = 1 d. S = 0, C = 0
16. The invalid state of a NAND latch occurs when
b. S = 1, C = 0 b. S = 0, C = 1
c. S = 1, C = 1 d. S = 0, C = 0
17. If a NAND latch has a 1 on the SET input and a 0 on the CLEAR input, then the SET input
goes to 0, the latch will be:
a. HIGH b. LOW
c. Invalid d. none of these
18. Counter is a
a. Combinational circuit b. sequential circuit
c. both (a) and (b) d. none of the above
19. Asynchronous counters are known as
a. Ripple counters b. decade counters
c. multiple clock counters d. modulus counters
20. An asynchronous counter differs from a synchronous counter in
a. The number of states in its sequence b. the method of clocking
c. the type of flip-flop used d. the value of the modulus
21. The modulus of a counter is
a. The number of flip-flops
 b. The actual number of times it recycles in a second
c. The number of times it recycles in a second
d. The maximum possible number of states
22. A 3-bit binary counter has a maximum modulus of
a. 3 b. 8
c. 6 d. 16
23. A 4-bit binary counter has a maximum modulus of
a. 16 b. 8
c. 32 d. 4
24. A modulus -12 counter must have
a. 12 flip-flop b. 4 flip-flop
c. 3 flip-flop d. synchronous clocking
25. Which one of the following is an example of counter with a truncated modulus?
a. Modulus 8 b. modulus 16
c. modulus 14 d. modulus 32
26. A 4-bit ripple counter consists of flip-flop that each have propagations delay form clock
to Q-output of 12 ns. For the counter to recycle form 1111 to 0000, it takes a total of
a. 12 ns b. 48 ns
c. 24 ns d. 36 ns
27. A BCD counter is an example of
a. A full-modulus counters b. a decade counter
c. a truncated modulus d. answers (a) and (c)
28. Which of the following is an invalid state in an 8421 BCD counter?
a. 1100 b. 0101
c. 0010 d. 1000
29. Three cascaded modulus-10 counters have an overall modulus of
a. 30 b. 1000
c. 100 d. 10000
30. A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5
counter, a modulus-8 counter, and two modulus-10 counters. The lowest output
frequency possible is
a. 10 kHz b. 5 kHz
 c. 2.5 kHz d. 25 kHz
31. A 4-bit binary up/down counter is in the binary state of zero. The next state in the
DOWN mode is
a. 0001 b. 1000
c. 1111 d. 1110
32. The terminal count of a modulus-13 binary counter is
a. 0000 b. 1101
c. 1111 d. 1100
33. Using an additional NOT gate, a JK flip-flop can be converted into
a. T flip-flop b. RS flip-flop
c. master slave flip-flop d. D flip-flop
34. A toggle flip-flop can be constructed using a JK flip-flop by connecting the
a. Toggle input to J and inverted form of toggle input to K b. toggle input to J
c. inverted form of toggle input to K d. none of the above
35. Half adder performs
a. Decimal addition operation for two decimal inputs
b. Binary addition operation for two-binary inputs
c. Decimal addition operation for two binary inputs
d. Binary addition operation for two-decimal inputs
36. Which logic circuit is used for addressing memory?
a. Full adder b. multiplexer
c. decoder d. direct memory access circuit
37. A flip-flop circuit can be used for
a. counting b. scaling
c. rectification d. demodulation
38. One bit full adder can be designed using
a. Two half adders and one OR gate b. two half adders
c. one Ex-OR and two NAND gates d. two Ex-OR and four NAND gates
39. 3 bits full adder contains
a. 3 combinational inputs b. 4 combinational inputs
c. 6 combinational inputs d. 8 combinational inputs
40. The simplified expression of full adder carry is
 a. C = xy + xz + yz b. C = xy + xz
c. C = xy + yz d. C = x + y + z
41. Shift registers are used for
a. shifting b. rotating
c. adding d. (a) and (b)
42. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first)
a. 1100 b. 0000
c. 0011 d. 1111
43. Enable inputs of the shift register is called as
b. load b. store
c. reset d. strobe
44. Shift register has IC number
a. 74195 b. 74123
c. 74124 d. 74154
45. A stage in a shift register consists of
a. A latch b. a byte of storage
c. a flip-flop d. four bits of storage
46. To serially shift a byte of data into a shift register, there must be
a. One clock pulse b. eight clock pulses
c. one load pulse d. one clock pulse for each 1 in the data
47. The group of bits 101101101 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state of 11100100. After two clock pulse, the register
contains.
a. 01011110 b. 1111001
c. 10110101 d. 00101101
48. With a 1 MHz clock frequency, eight bits can be serially entered into a shift register in
a. 80 μs b. 80 ms
c. 8 μs d. 10 μs
49. With a 1 MHz clock frequency, eight bits can be parallel entered into a shift register
 a. In 80 μs b. in the propagation delay time of eight flip-flops
c. in 1 μs d. in the propagation delay time of one flip-flop
50. A modulus-10 Johnson counter requires
a. Ten flip-flop b. five flip-flop
c. four flip-flop d. twelve flip-flop
51. A modulus-10 ring counter requires a minimum of
a. Ten flip-flops b. four flip-flops
c. five flip-flops d. twelve flip-flops
52. When an 8-bit serial in/serial out shift register is used for a 24 μs time delay, the clock
frequency must be
a. 41.67 kHz b. 125 kHz
c. 333 kHz d. 8 MHz
53. One example of the use of an SR flip-flop is
a. racer b. astable oscillator
c. binary storage register d. transition pulse generator
54. A type of shift register that requires access to the Q outputs of all stages is
a. Parallel in/serial out b. serial in/parallel out
c. serial in/serial out d. parallel in/parallel out
55. A decade counter is
a. Mode-3 counter b. mod-8 counter
c. mod-5 counter d. mod-10 counter
56. Decade counter counts pulses from
a. 0-9 b. 1-9
c. 0-11 d. 1-11
57. Asynchronous counter is also known as
a. Decade counter b. up-down counter
c. ripple counter d. johnson counter
58. The divide-by-60 counter in digital clock is implemented by using two cascading
counters:
a. Mod-6, mod-10 b. mod-50, mod-10
c. mod-10, mod-50 d. mod-50, mod-6
59. How many types of shift registers?
a. 1 b. 2
c. 3 d. 4
60. Decade counter consists of
a. One flip-flop and one NAND gate
b. Two flip-flops and two NAND gates
c. Four flip-flops and one NAND gate
d. None of the above
61. Bidirectional register is the part of
a. counter b. combinational circuit
c. logic gates d. shift register
62. Counter mainly used for
a. Convert A/D b. data transfer
c. count pulses d. none of these
63. SR flip-flops having
a. Two NAND gates b. two NOT gates
c. three AND gates d. three NOT gates
64. Master slave and edge-triggered is the type of
a. counters b. flip-flops
c. shift registers d. none of these
65. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is
HIGH is called ……….
a. Parity error checking b. ones catching
c. digital discrimination d. digital filtering
66. On a master-slave flip-flop, when is the master enabled?
a. When the gate is low b. when the gate is high
c. both (a) and (b) d. none of the above
67. How can the cross-coupled NAND flip-flop be made to have active-high SR inputs?
a. It can be done b. invert the Q outputs
c. invert the SR inputs d. none of the above
68. How can parallel data be taken out of a shift register simultaneously?
a. Use the Q output of the first FF b. use the Q output of the last FF
 c. tie all of the Q outputs together d. use the Q output of each FF
69. In a 6-bit Johnson counter sequence, there are total of how many states or bit patterns?
a. 2 b. 6
c. 12 d. 24
70. A modulus 12 ring counter requires a minimum of ………. Flip-flops.
a. 10 b. 12
c. 6 d. 2
71. A serial in/parallel out, 4-bit shift register initially contains all 1’s. The data nibble 0111 is
waiting to enter. After four clock pulses, the register contains ……….
a. 0000 b. 1111
c. 0111 d. 1000
72. A sequence of equally spaced timing pulses may be easily generated by which type of
counter circuit?
a. Ring shift b. clock
c. johnson d. binary
73. How many clock pulses will be required to completely load serially a 5-bit shift register?
a. 2 b. 3
c. 4 d. 5
74. Which of the following flip-flops is used as a latch?
a. J-K flip-flop b. S-C flip-flop
c. D flip-flop d. T flip-flop
75. A flip-flop which can have an uncertain output state is:
a. J-K flip-flop b. S-C flip-flop
c. D flip-flop d. T flip-flop
76. The purpose of a clock input to a flip-flop is to
a. Clear the device
b. Set the device
c. always cause the output to change the states
d. cause the output to assume a state dependent on the controlling (S-C, J-K or D) inputs
77. The minimum time for which the input signal has to be maintained at the input of flip-
flop is called ………. Of the flip-flop
a. Set-up time b. pulse interval time
 c. hold time d. pulse stability time (PST)
78. A feature that distinguished the J-K flip-flop from an S-C flip-flop is the
a. toggle condition b. preset input
c. type of clock d. clear input
79. A J-K flip-flop is in the toggle condition when
a. J = 1, K = 0 b. J = 1, K = 1
c. J = 0, K = 0 d. J = 0, K = 1
80. A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. The Q = output is,
a. Constantly LOW b. constantly HIGH
c. a 5 kHz square wave d. a 10 kHz square wave
81. For an edge-triggered D flip-flop,
a. A change in the state of the flip-flop can occur only at a clock pulse edge
b. The state the flip-flop goes to depends on the D input
c. The output follows the input at each clock pulse
d. All of these answers
82. A J-K flip-flop is a device to
a. Divide the frequency by 2
b. divide the frequency by 4
c. generate waveform of same frequency as that of the input
d. cannot be used for frequency division
83. The following is not a sequential circuit
a. J-K flip-flop b. counter
c. full-adder d. shift register
84. A toggle operation is used
a. Without a flip-flop b. with a flip-flop
c. with a gate circuit d. with a flip-flop and a gate circuit
85. How many flip-flop circuits are needed to divide by 16?
a. two b. four
c. eight d. sixteen
86. Which of the following statement regarding S-R flip-flop is wrong?
a. It consists of two cross-connected NOR gates
b. It forms the basis of more sophisticated memory element known as master-slave
flip-flop
c. It belongs to the family of static memories
 d. It is a non-volatile memory
87. J and K inputs of a negative edge-triggered flip-flop are tied to logic ‘1’ state. If the flip-
flop were clocked by a 100 KHz waveform, the Q-output will
a. Always be in logic ‘1’ state b. be a 50 KHz waveform
c. be a 100 KHz waveform d. be a 200 KHz waveform
88. There is a negative edge-triggered R-S flip-flop having active-LOW R and S inputs and
active-HIGH outputs. Identify the forbidden input entry.
a. R = 0, S = 0 b. R = 1, S = 1
c. R = 0, S = 1 d. R = 1, S = 0
89. In a positive edge-triggered clocked R-S flip-flop, Q-output is tied to R-input and Q̅-
output is tied to S-input. If the clock frequency is f, the Q-output frequency will be
a. f b. f/2
c. 2f d. None of these
90. Identify the flip-flop whose function table is given in the following figure.

PR Clr Clk J K Qn+1 Q̅n+1

1 0 × × × 1 0
0 1 × × × 0 1
1 1 × × × Unstable
0 0 ↑ 0 1 1 0
0 0 ↑ 1 0 0 1
0 0 ↑ 1 1 Qn Q̅n
0 0 ↑ 0 0 Toggle
a. Positive edge-triggered J-K flip-flop with active-HIGH J and K inputs and active-LOW
PRESET and CLEAR inputs
b. Positive edge-triggered J-K flip-flop with active-HIGH J and K inputs and active-HIGH
PRESET and CLEAR inputs
c. Positive edge-triggered J-K flip-flop with active-LOW J and K inputs and active-HIGH
PRESET and CLEAR inputs
d. Positive edge-triggered J-K flip-flop with active-LOW J and K inputs and active-LOW
PRESET and CLEAR inputs
91. A negative edge-triggered presettable clearable J-K flip-flop with active LOW J and K
inputs, active LOW PRESET and CLEAR inputs and active HIGH outputs has the following
 inputs at a certain time instant: J = 1, K = 0, PRESET = 0, CLEAR = 1. What would be the
logic status of output when clocked?
a. 0 b. 1
c. Indeterminate from given data d. Can be either ‘0’ or ‘1’
92. One of the following is not a synchronous input with reference to flip-flops.
a. J-input in a J-K flip-flop b. R-input in an R-S flip-flop
c. PRESET input in a J-K flip-flop d. D-input in a D-flip-flop
93. For one of the following conditions, clocked J-K flip-flop can be used as a divide-by-2
circuit when the input is applied at clock input.
a. J = K = 1 and flip-flop has active HIGH inputs
b. J = K = 0 and flip-flop has active HIGH inputs
c. J = K = 1 and flip-flop has active LOW inputs
d. J = K = 1 and flip-flop should be a negative edge-triggered one
94. We have two negative edge-triggered J-K flip-flops with active LOW inputs. J and K inputs
of both the flip-flops are tied to logic ‘0’. The Q-output of first flip-flop feeds the clock
input of second flip-flop. What will be the logic status of Q 1 and Q2 at the end of five
cycles if the two flip-flops were cleared to logic ‘0’ before start?
a. Q1 = 0, Q2 = 0 b. Q1 = 0, Q2 = 1
c. Q1 = 1, Q2 = 0 d. Q1 = 1, Q2 = 1
95. A shift counter comprising of a cascaded arrangement of five flip-flops with inverse
feedback from output of MSB flip-flop to input of LSB flip-flop is a
a. Divide-by-32 counter b. Divide-by-10 counter
c. Divide-by-5 counter d. Five-bit shift register
96. A binary ripple counter is to be constructed using J-K flip-flops with each flip having a
propagation delay of 12 ns. The largest modulus counter that can be constructed using
these flip-flops and still operate up to a clock frequency of 10 MHz is
a. MOD-16 b. MOD-64
c. MOD-256 d. MOD-8