Subject- Digital Electronics

Course- B.Tech. CSE/ECE/IT III Sem.

NOTE:-
 Format for assignment-1 is attached below. Describe topics in 1500-1800 words with
facts and figures with references.

Assignment-1 Unit-III

1. One Bit Memory Cell

2. Concept of level triggering and edge triggering
3. The gated D Latch
4. Clocked S-R flip-flop
5. Characteristic equation of J-K Flip-flop
6. Toggle flip flop
7. Registers and its classification
8. Important applications of shift registers
9. Counters & its classifications
10. Moor & Mealy circuit

Assignment-2 Unit-III

Q1. Explain R-S Flip Flop with suitable diagram and truth table.

Q2. Explain J-K Flip Flop with suitable diagram and truth table.

Q3. Explain D and T Flip Flop with suitable diagram and truth table.

Q4. Convert SR Flip Flop to J-K, D and T flip flops.

Q5. Explain the different types of Shift Registers used in digital circuits.

Q6. Explain the different types of Synchronous and Asynchronous Counters used in digital circuits.

Q7. With a neat and clean diagram, explain the working operation of a 4-bit left shift register. Also, give its
truth table and timing diagram.

Q8. What is meant by Universal shift register? Explain.

Q9. Explain the working of 4-bit ripple counter using T flip-flop with suitable circuit diagram and timing
diagram.
Q10. Explain state diagram.

MCQs
1) The race around condition in J-K flip flop occurs when:
a) J=0; K=0
b) J=0; K=1
c) J=1; K=0
d) J=1; K=1
2) In a J-K flip flop output Qn is 1. It does not change when a clock pulse is applied. The possible combination of J n-Kn
would be;
a) X and 0
b) X and 1
c) 0 and X
d) 1 and X
3) Race around condition always arise in a:
a) Combinational circuit
b) Asynchronous circuit
c) Synchronous circuit
d) Digital circuit
4) The flip flops used in shift registers are:
a) S-R flip flop
b) J-K flip flop
c) Master slave
d) D-flip flop
5) The flip flops used in counters are generally:
a) S-R flip flop
b) Master slave
c) T-flip flop
d) J-K flip flop
6) A toggle function is generally obtained from a flip flop. The connection needed is;
a) J=K=1
b) J=0; K=1
c) J=1; K=0
d) J=0; K=0
7) Which of the following is correct for a gated D-type flip flop?
a) The Q output is either set or reset as soon as D input goes HIGH or LOW.
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time.
d) The output toggles if one of the inputs is held HIGH.
8) When both inputs of a J-K flip flop cycle is 0, the output will:
a) Be invalid
b) Not change
c) Change
d) Toggle
9) A basic S-R flip flop can be constructed by cross-coupling which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
10) If both inputs of an S-R NAND latch are low, what will happen to the output?
a) The output wil become unpredictable
b) The output will be toggle
c) The output will reset
d) The change will occur in the output
11) What of the following describes the operation of a positive edge-triggered D-type flip-flop?
 a) If both inputs are high, the output will toggle
b) The output will follow the input on the leading edge of clock
c) When both the inputs are low, an invalid state exists
d) None of these
12) Race-around condition occurs in:
a) S-R flip flop
b) D flip flop
c) J-K flip flop
d) It has only a single output
13) Which of these circuit requires clock input to drive the circuit?
a) Synchronous circuit
b) Asynchronous circuit
c) Combinational circuit
d) Logic families
14) Which of the following is level-triggered?
a) Flip-flops
b) Latches
c) Adders
d) Multiplexer
15) Which of the following is edge-triggered?
a) Flip-flops
b) Latches
c) Adders
d) Multiplexer
16) Which of the following are memory devices?
a) Flip-flops
b) Latches
c) Adders
d) Multiplexer
17) The type of logic circuit in which output depends not on the present value of input but also on the past history of inputs
is:
a) Sequential logic
b) Combinational logic
c) DTL
d) A/D convertors
18) The output of the S-R flip flop is surely 1 when:
a) S=0, R=0
b) S=1, R=0
c) S=0, R=1
d) S=1, R=1
19) Total number of output states of N-Bit ring counter is:
a) N-1
b) N
c) 2N
d) 2N-1
20) Total number of output states of N-Bit Johnson counter is:
a) N-1
b) N
c) 2N
d) 2N-1
21) The output of the S-R flip flop is surely 1 when:
a) S=0, R=0
b) S=1, R=0
c) S=0, R=1
d) S=1, R=1
22) How many flip-flops are required to make MOD-16 binary counter?
a) 3
b) 4
 c) 5
d) 6
23) A MOD-16 ripple counter is holding the count 10012. What will be the count be after 31 clock pulses?
a) 10002
b) 10102
c) 10112
d) 11012
24) The terminal count of a modulus-11 binary counter is:
a) 1010
b) 1000
c) 1001
d) 1100
25) Synchronous counter eliminate the problem of delays encounter with asynchronous counter because the:
a) Input clock pulses are applied only to the first and last stage
b) Input clock pulses are applied only to the last stage
c) Input clock pulses are not used to activate any of the counter stages
d) Input clock pulses are applied simultaneous to each stage
26) When two counters are cascaded, the overall modulus number equal to:
a) Sum of their individual MOD numbers.
b) Product of their individual MOD numbers.
c) Log of their individual MOD numbers.
d) Reciprocal of their individual MOD numbers.
27) Which segments of a seven segment display would be required to be active to display the decimal digit 2?
a) a, b, d, e and g
b) a, b, c, d and g
c) a, c, d, f and g
d) a, b, c, d, e and f
28) A BCD counter is a:
a) Binary counter
b) Full-modulus counter
c) Decade counter
d) Divide by 10 counter
29) How many flip flops are required to construct a decade counter?
a) 10
b) 8
c) 5
d) 4
30) To operate correctly, starting a ring counter requires:
a) Clearing one flip flop and presetting others
b) Clearing all the flip flops
c) Presetting one flip flop and clearing all the others
d) Presetting all the modes
31) To operate correctly, starting a johnson counter requires:
a) Clearing one flip flop and presetting others
b) Clearing all the flip flops
c) Presetting one flip flop and clearing all the others
d) Presetting all the modes
32) How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
33) A 5-bit asynchronous binary counter is made of 5 flip flops, each with 12 ns propagation delay. The total propagation
delay is:
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
34) Three cascaded modulus-5 counter have an overall modulus of:
a) 5
b) 25
c) 125
d) 600

35) The final output of a modulus-8 counter occurs one time for every:
a) 8 clock pulses
b) 16 clock pulses
c) 24 clock pulses
d) 32 clock pulses
36) The terminal count of a 3 bit binary counter in the DOWN mode is?
a) 000
b) 111
c) 101
d) 010
37) A 4 bit UP/DOWN binary counter is in the DOWN mode and the 1100 state. To what state does the counter go on the
next clock pulse?
a) 1101
b) 1011
c) 1111
d) 0000
38) A ripple counter speed is limited by the propagation delay of:
a) Each flip-flop
b) All flip flops and gates
c) The flip flops only with gates
d) Only circuit gates
39) A 4 bit registers require no of flip flops?
a) 1
b) 2
c) 3
d) 4
40) On the fifth clock pulse, a 4-bit Johnson counter has Q0=0, Q1=1, Q2=1, Q3=1. On the sixth clock pulse, the sequence
is:
a) Q0=1, Q1=0, Q2=0, Q3=0
b) Q0=1, Q1=1, Q2=1, Q3=0
c) Q0=0, Q1=0, Q2=1, Q3=1
d) Q0=0, Q1=0, Q2=0, Q3=1
41) The bit sequence 0010 is serially entered (right most bit first) into a 4 bit parallel out shift register that is initially cleared.
What are the Q outputs after two clock pulses?
a) 0000
b) 0010
c) 1000
d) 1111
42) How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first flip flop
b) Use the Q output of the last flip flop
c) Tie all the Q outputs together
d) Use the Q output of each flip flop
43) In a 6 bit Johnson counter, there are total of how many states?
a) 2
b) 6
c) 12
d) 24
44) A modulus-12 ring counter requires a minimum of?
a) 10 flip flops
b) 12 flip flops
c) 6 flip flops
 d) 2 flip flops
45) The group of bits 11001 is serially shifted into a 5 bit parallel output shift register with an initial state of 01110. After
three clock pulses, the register contains:
a) 01110
b) 00001
c) 00101
d) 00110
46) With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in:
a) 4 microsecond
b) 40 microsecond
c) 400 microsecond
d) 40 millisecond

47) If an 8 bit ring counter has an initial state of 10111110, what is the state after the fourth clock pulse?
a) 11101011
b) 00010111
c) 11110000
d) 00000000
48) How many clock pulses will be required to completely load serially a 5 bit shift register?
a) 2
b) 3
c) 4
d) 5
49) How is a strobe signal used when serially loading a shift register?
a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Q’s are used
d) To determine the flip flops that will be used

50) What is the difference between ring shift register and Johnson shift register?
a) There is no difference.
b) A ring is faster
c) The feedback is reversed
d) Johnson is faster