20.

Assuming that all flip-flops are in reset condition initially, the count
sequence observed at QA in the circuit shown is

(a) 0010111…

(b) 0001011…

© 0101111…

(d) 0110100…

Ans:d

21. The full-scale output of a digital to analog converter is 20 mA. If the

resolution is 80µA, then the minimum number of bits required and
percentage resolution are:

(a) 0.8

(b) 0.07

© 3.9

(d) 0.39

Ans d.

23. A MOD-16 ripple counter using J-K flip-flop has a current state 1001. What
will the state be after 31 clock pulses?

(a) 1001

(b) 1010

© 1000

(d) 1111

Ans c

24. A specific counter is using five S-R flip-flops. So what is the maximum
number of states possible?

(a) 4

(b) 16

© 32

(d) 64
Ans c

25. What is the maximum delay that can occur if four flip-flops are
connected as a ripple counter and each flip-flop has propagation delays of
tPHL = 22 ns and tPLH = 15 ns?

(a) 15 ns

(b) 22 ns

© 60 ns

(d) 88 ns

Ans d

26. The logic gates shown in the given figure works as:

(a) Decoder
(b)Binary to EXCESS-3 converter D3 D2 D1 D0

© priority encoder

(c) Binary to gray converter

Ans c

27. Which of the circuits in figure (a to d) is the sum-of-products?

(a) a

(b) b

©c

(d)D

Ans d

28. The device shown here is most likely ?

(a) Comparator

(b) Multiplexer

© Inverter

d.demultiplexer
Ans d

29. In a combinational circuit, the output at any time depends only on the
_______ at that time.

(a) Voltage

(b) Intermediate values

© Input values

(e) Clock pulses

Ans c

30. If the two numbers include a sign bit in the highest order position, the bit
conditions of interest are the sign of the result, a zero indication and
___________

(a) An underflow condition

(f) (b) A neutral condition

(g)© An overflow condition
(h)(d) One indication

Ans c

31. A sequence of equally spaced timing pulses may be easily generated by

which type of counter circuit?

(a) Ring counter

(b) Clock

© Johnson
(d) Binary.

Ans A

32. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is
HIGH. The nibble 1011 is waiting to be entered on the serial data-input line.
After three clock pulses, the shift register is storing ________

(a) 1101

(b) 0111

© 0001

(d) 1110

Ans b

34. In a 3-bit asynchronous down counter, at the first negative transition

of the clock, the counter content becomes ____________

(a) 000

(b) 111

© 101

(d) 010

Ans b

35. In JK flip flop same input, i.e. at a particular time or during a clock
pulse, the output will oscillate back and forth between 0 and 1. At the end
of the clock pulse the value of output Q is uncertain. The situation is
referred to as?

(a) Conversion condition

(b) Race around condition

© Lock out state

(d) Forbidden State

Ans b

36. Which of the following flip-flops is free from race around condition?

(a) All of the above

(b) T flip-flop

© SR flip-flop

(d) Master slave JK flip-flop

Ans d

37. What type of logic circuit is represented by the figure shown below?

(a) XOR

(b) XNOR

© AND

(d) XAND

Ans B

38. For realisation of JK flip-flop from SR flip-flop, the input J and K will be
given as ___________

(a) External inputs to S and R

(b) Internal inputs to S and R

© External inputs to combinational circuit

(d) Internal inputs to combinational circuit

Ans A

39. The only difference between a combinational circuit and a flip-flop is

that _____________

(a) The flip-flop requires previous state

(b) The flip-flop requires next state

© The flip-flop requires a clock pulse

(d) The flip-flop depends on the past as well as present states

Ans c

40. For a 4 bit MOD-16 ripple counter using J-K flip-flop, the propagation
delay of each flip flop is 50ns. What is the maximum clock frequency can
be used?

(a) 10 MHz

(b) 20 MHz

© 5 MHz

(d) 40 MHz

Ans c

41. How many 3 to 8 line decoders are required for a 1 of 32 decoder?

(a)1

(b)2

©4

(d)8

Ans c

42. Which of the following is correct for a gated D-type flip-flop?

(a) The output toggles if one of the inputs is held HIGH

(b)Only one of the inputs can be HIGH at a time

©The output complement follows the input when enabled

(d)Q output follows the input D when the enable is HIGH

Ans d

43. Whose operations are more faster among the following?

(a) Combinational circuits

(b) Sequential circuits

 © Latches

(d) Flip-flops

Ans a

44. As the number of flip flops are increased, the total propagation delay
of __________

(a) Ripple counter increases but that of synchronous counter remains the
same

(b) Both ripple and synchronous counters increase

© Both ripple and synchronous counters remain the same

(d) Ripple counter remains the same but that of synchronous counter
increases

Ans a

45. An asynchronous binary up counter, made from a series of leading

edge-triggered flip-flops, can be changed to a down counter by ________

(a) Taking the output on the other side of the flip-flops (instead of Q)

(b) Clocking of each succeeding flip-flop from the other side (instead of Q)

© Changing the flip-flops to trailing edge triggering

(d) All of the Mentioned

Ans d

46. A 4-bit binary up counter has an input clock frequency of 20 kHz. The
frequency of the most significant bit is ________

(a) 1.25 kHz

(b) 2.50 kHz

© 160 kHz

(d) 320 kHz

Ans a
47. How many address bits are required to select memory location in the
Memory decoder?

(a) 4 KB

(b) 8 KB

© 12 KB

(d) 16 KB

Ans c

48. How many 16K * 4 RAMs are required to achieve a memory with a
capacity of 64K and a word length of 8 bits?

(a) 2

(b) 4

©6

(d) 8

Ans D

49. The complex programmable logic device contains several PLD blocks and
__________

(a) A language compiler

(b) AND/OR arrays

© Global interconnection matrix

(d) Field-programmable switches

Ans c

50. The difference between a PAL & a PLA is ____________

(a) PALs and PLAs are the same thing

(b) The PLA has a programmable OR plane and a programmable AND plane,
while the PAL only has a programmable AND plane

© The PAL has a programmable OR plane and a programmable AND plane,

while the PLA only has a programmable AND plane

(d) The PAL has more possible product terms than the PLA
Ans b

51) What is a digital-to-analog converter?

It stores digital data on the computer.

It converts alternating current (AC) into direct current (DC).

It converts electrical power into mechanical power.

It takes the digital data from an audio CD and converts it to a useful form.

Ans d

52) Which number system has a base 16

Hexadecimal

Octal

Binary

Decimal

Ans a

53) The following hexadecimal number (1E.43)16 is equivalent to

(36.506)8

(36.206)8

(35.506)8

(35.206)8

Ans b

54. At which frequency the digital data can be applied to a gate?

Run-time frequency

Propagation Frequency

Operating frequency

AC frequency

Ans c

55. What are the three output conditions of 3- state buffer?

High Impedance, 0, float

Negative, positive, 0

1, Low Impedance, float

High, Low, float

Ans d

56) What is the actual meaning of the parallel load of a shift register?

All flip-flops are set with data.

It means a parallel shifting of data.

All flip-flops are present with data.

Each flip flop is loaded with data simultaneously.

Ans c

57. The primary difference between a counter and a register is

A counter has the capability to store n bit of information whereas a register

has one bit.

A register counts data.

A register has no specific sequence of states.

A counter has no particular sequence of states.

Ans c
58. What is the radix of the octal number system?

10

16

Ans c

59.A register can be defined as

.The group of transistors for storing n- a bit of information

.The group of transistors for storing two bits of information

The group of flip-flops for storing n bit of information

The group of flip-flops for storing binary information.

Ans d

60. What is the binary subtraction of 101001 – 010110 =?

010011

100110

011001

010010

Ans a