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    Experiment No1 Opk

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    Om Prakash
    The document provides an introduction to the Xilinx ISE design tools. It describes the basic Verilog design flow which includes creating Verilog files, compiling and implementing the design, simulating the design, assigning I/O pins, downloading the bitstream to an FPGA device, and testing the design on the FPGA board. The document then provides step-by-step instructions for creating a simple design in ISE using Verilog, simulating the design, creating a user constraints file to assign I/O pins, implementing the design, and downloading the bitstream to the Spartan-3 FPGA starter kit board.

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    Download as DOCX, PDF, TXT or read online from Scribd

    Experiment No1 Opk

    Uploaded by

    Om Prakash
    51 views15 pages
    The document provides an introduction to the Xilinx ISE design tools. It describes the basic Verilog design flow which includes creating Verilog files, compiling and implementing the design, simulating the design, assigning I/O pins, downloading the bitstream to an FPGA device, and testing the design on the FPGA board. The document then provides step-by-step instructions for creating a simple design in ISE using Verilog, simulating the design, creating a user constraints file to assign I/O pins, implementing the design, and downloading the bitstream to the Spartan-3 FPGA starter kit board.

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    INTRODUCTION TO XILINX ISE TOOL

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    The document provides an introduction to the Xilinx ISE design tools. It describes the basic Verilog design flow which includes creating Verilog files, compiling and implementing the design, simulating the design, assigning I/O pins, downloading the bitstream to an FPGA device, and testing the design on the FPGA board. The document then provides step-by-step instructions for creating a simple design in ISE using Verilog, simulating the design, creating a user constraints file to assign I/O pins, implementing the design, and downloading the bitstream to the Spartan-3 FPGA starter kit board.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    51 views15 pages

    Experiment No1 Opk

    Uploaded by

    Om Prakash
    The document provides an introduction to the Xilinx ISE design tools. It describes the basic Verilog design flow which includes creating Verilog files, compiling and implementing the design, simulating the design, assigning I/O pins, downloading the bitstream to an FPGA device, and testing the design on the FPGA board. The document then provides step-by-step instructions for creating a simple design in ISE using Verilog, simulating the design, creating a user constraints file to assign I/O pins, implementing the design, and downloading the bitstream to the Spartan-3 FPGA starter kit board.

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    © All Rights Reserved
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    You are on page 1of 15

    EXPERIMENT NO.

    01
    INTRODUCTION TO XILINX ISE TOOL
    Introduction
    Xilinx Tools is a suite of software tools used for the design of digital circuits implemented
    using Xilinx Field Programmable Gate Array (FPGA) or Complex Programmable Logic
    Device (CPLD). The design procedure consists of (a) design entry, (b) synthesis and
    implementation of the design, (c) functional simulation and (d) testing and verification.
    Digital designs can be entered in various ways using the above CAD tools: using a schematic
    entry tool, using a hardware description language (HDL) Verilog or VHDL or a
    combination of both. In this lab we will only use the design flow that involves the use of
    Verilog HDL.
    The CAD tools enable you to design combinational and sequential circuits starting with
    Verilog HDL design specifications. The steps of this design procedure are listed below:
    1. Create Verilog design input file(s) using template driven editor.
    2. Compile and implement the Verilog design file(s).
    3. Create the test-vectors and simulate the design (functional simulation) without using a
    PLD (FPGA or CPLD).
    4. Assign input/output pins to implement the design on a target device.
    5. Download bit stream to an FPGA or CPLD device.
    6. Test design on FPGA/CPLD device
    A Verilog input file in the Xilinx software environment consists of the following segments:
    Header: module name, list of input and output ports.
    Declarations: input and output ports, registers and wires.
    Logic Descriptions: equations, state machines and logic functions.
    End: endmodule
    All your designs for this lab must be specified in the above Verilog input format.
    Getting Started
    To start ISE, double-click the desktop icon,

    or start ISE from the Start menu by selecting:


    Start All Programs Xilinx ISE 13.1 Project Navigator Note:
    Your start-up path is set during the installation process and may differ from the one above.
    Create a New Project
    Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
    demo board.
    To create a new project:
    1. Select File > New Project... The New Project Wizard appears.

    2. Type try in the Project Name field.


    3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is
    created automatically.
    4. Verify that HDL is selected from the Top-Level Source Type list as shown in Figure 1

    Figure 1- The New Project Wizard


    5. Click Next to move to the device properties page.
    6. Fill in the properties in the table as shown in Figure 2:
    Product Category: All
    Family: Spartan3
    Device: XC3S400
    Package: TQ144
    Speed Grade: -5
    Top-Level Source Type: HDL
    Synthesis Tool: XST (VHDL/Verilog)
    Simulator: ISE Simulator (VHDL/Verilog)
    Preferred Language: Verilog (or VHDL)
    Verify that Enable Enhanced Design Summary is selected. Leave the default values in
    the remaining fields.

    Figure 2- The New Project Wizard


    7. Click Next, then Finish. Right click on xc3s400-5tq144 and select New Source as shown
    in figure 3.

    Figure 3-ISE Project Navigator


    8. Select Verilog module as shown in Figure 4.

    Figure 4- The New Source Wizard


    9. Give file name try as shown in figure 5. Click Next.

    Figure 5- The New Source Wizard

    10. Enter inputs and outputs as shown in figure 6. Click Next and then Finish.

    Figure 6- The New Source Wizard


    11. Window will appear as shown in Figure 7. Write your logic inside Module.

    Figure 7- Xilinx ISE


    12. Save your program. Click on Synthesize-XST and Check syntax as shown in Figure
    8.

    Figure 8-ISE Project Navigator


    13. If there is no error in program, following message will appear:
    Process "Check Syntax" completed successfully
    14. Select Behavioral Simulation from View icon as shown in figure 9.
    15. Click on ISim Simulator under process icon and double click on Simulate
    behavioral Model. You will get an object window as shown in figure 10.

    Figure 9- ISE Project Navigator

    Figure 10- ISim

    16. Select input a and right click and select Force Constant and put binary value in
    Force to Value as shown in figure 11. Click OK. Repeat the same for all the
    inputs.

    Figure 11-ISim
    17. Select Simulation and click on run as shown in figure 12.

    Figure 12-ISim

    18. Behavior of the circuit will be shown in the waveform window in figure 13.

    Figure 13- ISim


    Preparing and downloading bitstream file for the Spartan3 FPGA Kit
    A bitstream file needs to be prepared for each design and downloaded onto the Spartan 3
    board. This is done as follows:
    User Constraint File:
    In order to test the design in the Spartan 3 board, the inputs need to be connected to
    the switches/buttons on the board and the outputs need to be connected to the onboard
    LEDs.
    To create the constraint file, ensure that the implementation button is selected and
    your verilog module is highlighted as shown in Figure 14.

    Figure 14- ISE Project Navigator

    In the processes window, expand User Constraints and double click on I/OPin
    Planning (Plan Ahead) Post Synthesis as shown in Figure 15.

    Figure 15- ISE Project Navigator

    Answer Yes when asked if you want to create the UCF file. This will create the
    constraint file but also open the Plan Ahead application. Wait for the Plan Ahead to
    fully open as shown in Figure 16.

    Figure 16-try

    In the I/O Port window, expand All ports and then expand Scalar ports and enter the
    pin numbers in site column for inputs and output as shown in Figure 17. Pin number
    is shown below:
    NET "a" LOC = P74; Input port DIP SWITCH is connected to FRC1.
    NET "b" LOC = P76; Input port DIP SWITCH is connected to FRC1
    NET "c" LOC = P100; Output port LEDS is connected to FRC3

    Figure 17- I/O Ports

    Go to File and click on Save Design. Close the Plan Ahead window.
    You will now see the .ucf file in your hierarchy. Double click it to edit the file as
    shown in Figure 18.

    Figure 18- ISE Project Navigator

    Double-click the Implement Design process in the Processes tab as shown in Figure
    19. Notice that after Implementation is complete, the Implementation processes have
    a green check mark next to them indicating that they completed successfully without
    Errors or Warnings.

    Figure 19- ISE Project Navigator


    DOWNLOAD DESIGN TO THE BOARD
    This is the last step in the design verification process. This section provides simple
    instructions for downloading the try design to the Kit board.
    1. Connect the 5V DC power cable to the power input on the board.
    2. Connect the download cable between the PC and Board.
    3. Select Implementation from the View icon.
    4. Select try in the Sources window.
    5. In the Process window, double-click the Configure Target Device process.
    6. Warning window opens during this process. Click OK as shown in Figure 20.

    Figure 20- ISE Project Navigator

    7. ISE iMPACT window opens. Double click on Boundary Scan . Keep the cursor on
    Boundary Scan window and right click. Click on Initialize chain as shown in Figure
    21.

    Figure 21-ISE iMPACT

    8. The Assign New Configuration File dialog box appears. Click on Bypass as shown
    in Figure 22.

    Figure 22- Assign New Configuration File

    9. Again Assign New Configuration File dialog box appears. select the try.bit file and
    click Open as shown in Figure 23.

    Figure 23- Assign New Configuration File

    10. Device Programming Properties dialog box appears. select Device 2 file and click
    OK as shown in Figure 24.

    Figure 24- Device Programming Properties

    11. Right-click on the xc3s400 device image highlighted in green color, and select
    Program as shown in Figure 25.

    Figure 25-ISE iMPACT

    12. After successfully downloading the program in the kit the massage will appear
    Program Successful as shown in Figure 26.

    Figure 26-ISE iMPACT

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