Department Of Electronics & Telecomm.

Analog and Digital IC- Design and Applications

INDEX
Sr.
No.

Name Of Experiment

Page
No.

Inverting & Non-Inverting Amplifier

Instrumentation Amplifier

Regenerative comparator (Schmitt Trigger).

3-bit R-2R ladder Digital to Analog converter

11

Astable multivibrator using IC555-timer

14

Second order low pass active filter

18

DOS

Sign

VHDL-Experiments using Xilinx ISE 9.2i & Spartan-3 FPGA Family

7

2:1 multiplexer

21

4:1 multiplexer using conditional signal

assignment

23

2:1 multiplexer ( 4-bit bus input ) using

conditional signal assignment

25

10

4:1 multiplexer ( 4-bit bus input ) using

hierarchical approach

27

11

4-bit addition using ripple carry adder

31

12

1011 sequence detector

33

13

111 sequence detector

35

14

4-bit Up down Counter

37

15

4-bit ring counter with asynchronous load &

clear

38

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EXPERIMENT NO - 1

DATE :

Aim: - To design & implement inverting and non-inverting amplifier circuit

using IC741.
Apparatus: - CRO (20MHz), Function Generator (0-1MHz), Bread-Board, DMM
DC Power supply (0-30V dual) & (0-15v), Connecting wires,
CRO Probes etc.
Components: - Semiconductor devices LM741 (Op-Amp), Resistors
Circuit diagram:1] Inverting Amplifier-

1] Non-Inverting Amplifier-

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Theory:- The utility of an op-amp can be greatly increased by providing

negative feedback. The output in this case is not driven into saturation &
circuit behaves in a linear manner.
In order to understand the operating of these circuits, we make two realistic
simplifying assumptions.
1] The current drawn by either of the input terminals is negligible.
2] The differential input voltage between non-inverting & inverting input
terminals is essentially zero.
In case of inverting amplifier we can obtain closed loop gain as follows
Since current flowing through
 &
 is same, we can write

















 180  
 0

In case of non-inverting amplifier we can obtain closed loop gain as follows

Since current flowing through
 &
 is same, we can write
   










1




 0  
 0
If in non inverting amplifier
  0 (short circuit) &
  (Open circuit)
then this circuit act as a buffer with 
 1. Only non inverting amplifier
circuit is suitable to act as a buffer.

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Design:-

Result:Inverting Amplifier

Non- Inverting Amplifier

Sr. no.
Input

Output

Gain

Input

Output

Gain

1
2
3
4

Conclusion:- Op-amp can be used as an amplifier in both inverting & noninverting. Op-amp can be used to amplify 0Hz signal i.e. DC voltage.

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EXPERIMENT NO - 2

DATE :

Aim:- Design & implement Instrumentation amplifier.

Apparatus: - CRO (20MHz), Function Generator (0-1MHz), Bread-Board,
DMM, DC Power supply (0-30V dual) & (0-15v), Connecting wires,
CRO Probes etc.

Components: - Semiconductor devices LM324/LM741 (3nos.) , Resistors

Circuit Diagram:-

Theory:- An ideal difference amplifier amplifies only the difference between

two signals; it rejects any common signal to the two input terminals. It is
difficult to obtain high input impedance & a high gain in difference amplifier
with reasonable resistor values. One solution is to insert a voltage follower
between each source & the corresponding input. However disadvantage of this
design is that the gain of the amplifier cant easily be changed. We would need
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to change two resistance values & still maintain equal ratios between
 /
 &

 /
 .

Optimally we would like to be able to change the gain by changing only a

single resistance value, the circuit called an Instrumentation Amplifier that
allows this flexibility. In this circuit two non-inverting amplifiers,  and  are

used as input stage, & a difference amplifier  as second stage.

The voltages at the inverting terminals of the voltage followers are equal
to the input voltages. The current in resistor
 is then
 

  



The current in resistor
 is also  , and output voltages of op-amp 

and  are respectively ,

    
  1 





  



 

    
  1 





  



 

And

Therefore output of difference amplifier is given as

 


   

 

Substituting values of  &  in the above equation, we get

 


2

1 
    





Since the input signal voltages are applied directly to the non-inverting
terminals of

 and  input impedance is very large, ideally infinite, which

is one desirable characteristic of instrumentation amplifier. Also, the

differential gain is a function of resistor
 , which can easily be varied by using
potentiometer, thus providing a variable amplifier gain with adjustment of only
one resistance.
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Design:-

Result:Sr.
No.





#$% &'%

100()) & 1*+, -%..

0 012

Conclusion:-

" 


   

0 012
#$% &'%

100()) & 1*+, -%..

Instrumentation amplifier is a difference amplifier, in

which the output is the function of only one resistor, i.e. gain can be changed
easily. Also input impedance remains ideally infinite.

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EXPERIMENT NO - 3

DATE :

Aim: - To design & implement regenerative comparator (Schmitt Trigger)

circuit using IC741.

Apparatus: - CRO (20MHz), Function Generator (0-1MHz), Bread-Board, DMM

DC Power supply (0-30V dual), Connecting wires, CRO Probes etc.

Components: - Semiconductor devices LM741 (Op-Amp), Resistors.

Circuit Diagram:-

Theory:- If positive feedback is added to comparator circuit, gain can be

increased greatly. Consequently, the transfer curve of comparator becomes
more close to ideal curve. If the loop gain 34
is adjusted to unity, then gain

with feedback 56 becomes infinite. This results in abrupt (zero rise time)
transition between extreme values of output voltage. In practical circuits,
however, it may not be possible to maintain loop-gain exactly equal to unity
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for long time because of supply voltage & temperature variations. So a value
greater than unity is chosen. This also gives an output waveform virtually
discontinuous at the comparison voltage, which leads to hysteresis or backlash.
Figure shows such a regenerative comparator also known as Schmitt Trigger.
The input voltage is applied to inverting ( - ) input terminal & feed-back voltage
to non-inverting (+) input terminal. The input voltage  triggers the output 
every time it exceeds certain voltage level. These voltage levels are called
upper threshold voltage 789  & lower threshold voltage 
89 . The
hysteresis width is the difference between these two threshold voltages i.e.
789   
89 . These voltages are calculated as follows

Suppose the output   :;< . Therefore voltage at (+) terminal can be

given by using superposition
789 

=>

:;<


? ? ? 1

 

 


Suppose the output   :;< . Therefore voltage at (+) terminal can be

given by using superposition

89 

=>

:;<


? ? ? 2

 

 


Input voltage must be lesser than 

89 in order to cause  to switch from

:;< to :;< . The regenerative transition takes place as shown in figure &
output returns from :;< to :;< almost instantaneously. Hysteresis width

@ can be written as

@  789  
89 

2
 :;<
? ? ? 3

 


Hysteresis width is independent of => . The resistor
 is chosen equal to

 ||
 to compensate for the input bias current. A non-inverting Schmitt

trigger is obtained if  & => are interchanged.
If => is chosen as zero volt then

789   
89 
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 :;<
? ? ? 4

 

Page 9

If an input sinusoid of frequency -  1/D is applied to such a comparator, the

symmetrical square wave is obtained at the output.

Design:Given |789 |  |
89 |  1.5, |:;< |  15, =>  0
Assume
  1*

Select input signal frequency 300Hz to 600Hz and amplitude must be such that
it crosses 789 & 
89 .

Result:Observed values of
789 

89 
:;< 
:;< 
Conclusion:Schmitt Trigger is a comparator with positive feedback. A Schmitt trigger
converts slowly varying waveforms into square wave. In Schmitt trigger, the
input voltage triggers the output every time it exceeds certain voltage levels
called upper threshold & lower threshold voltages.

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EXPERIMENT NO - 4

DATE :

Aim:- Design & implement R-2R ladder Digital to Analog converter using
op-amp IC741.

Apparatus: - DC Power supply (0-30V dual), Reference DC Voltage,

Bread-Board, Connecting wires, DMM etc.

Components: - Semiconductor devices LM741 (Op-Amp), Resistors

Circuit Diagram:-

Theory:- Most of the real-world physical quantities such as voltage, current,

temperature, pressure & time etc. are available in analog form. Even though an
analog signal represents a real physical parameter with accuracy, it is difficult
to process, store or transmit the analog signal without introducing
considerable error because of noise. Therefore for processing, transmission &
storage purposes, it is often convenient to express these variables in digital
form.

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A D/A converter in its simplest form use an op-amp & either binaryweighted resistor or R & 2R resistor as shown in figure. Wide range of resistor
is required in binary-weighted type DAC. This can be avoided by using R-2R
ladder DAC where only two values of resistors are required. It is well suited for
integrated circuit realization. The typical values or R ranges from 2.5K to
10K.
Consider a 3-bit DAC as shown in figure, where 2 FGH, 2 , 2 JGH
corresponds to binary inputs. Therefore voltage at point c can easily be
calculated for different binary input conditions. Since resistive network is
linear circuit, therefore for analysis purpose, we can select only four digital
data inputs i.e. 000, 100, 010, 001. Output voltage for other input conditions
can be calculated by using superposition theorem as shown in figure.
The output voltage equation can written in different ways as,
  =>: K%L('M %.N'M%$O P- $)NO Q$'RS K'O' T2 , 2 , 2 U
Where =>: V R%#PMNOP$ P- 2W
=>: 

=>
2X

$ V $ QO 2W and => V R%-R%%$L% PMO'Y% N#%K -PR R%)R%#%$O$Y Z1Z

Maximum output voltage of DAC will be for 111 = =>: [ 7 PMO# for 3-bit

DAC.

In general output voltage for circuit used can be written as

2 2 2
 
  =>  
2
4
8
Here 2 , 2 , 2 are Z1] PR Z0Z .

1 V R%-R%%$L% PMO'Y%, 0 V ,%RP PMO'Y% YRPN$K

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Design:-

Observation Table:DIGITAL
INPUTES

Decimal
Equivalent

2

2

2

Output
Voltage

Result:- Resolution of 3-bit DAC with reference voltage +8volt is -1volt.

Conclusion:- R-2R ladder type DAC requires only two values of resistors. DAC
using discrete components is not suitable for higher resolution e.g. 8-bit DAC
etc.

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EXPERIMENT NO - 5

DATE :

Aim:- Design & implement astable multivibrator using IC555-timer.

Apparatus: - Bread-Board, DC Power supply 0-30V, Connecting wires, DMM,

CRO-20MHz etc.

Components: - LM555-timer, Resistors, capacitors etc.

Circuit Diagram:-

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Theory:The 555 timer is a highly stable device for generating accurate time delay or
oscillation. The 555 timer can be used with supply voltage in the range of +5V
to +18V & can drive load upto 200mA. Three 5K internal resistors act as
voltage divider, providing bias voltage of (2/3) Vcc to upper comparator & (1/3)
Vcc to lower comparator. It is possible to vary time, by applying a modulation
voltage to the control voltage input terminal (pin 5), when not in use, it is
recommended by manufacturers that a capacitor (0.01F) be connected
between control voltage terminal & ground to by-pass noise or ripple from
supply.

The reset input (pin 4) provides a mechanism to reset the flip-flop in a manner
which overrides the effect of any instruction coming from flip-flop. This
overriding reset is effective when the reset input is less than about 0.4V. When
not in use it is connected to Vcc.

Circuit diagram shows IC555 connected in astable mode. When power supply is
connected, the external timing capacitor C charges towards Vcc with a time
constant 
^ 
_ W. During this time pin3 is high(Vcc).

When capacitor voltage equals (slightly greater than) 2/3LL the upper

comparator triggers the flip-flop so that `a  1. This in turn makes transistor

` on and capacitor C starts discharging towards ground through
_ and `

with a time constant
_ W current also flows into transistor ` through
^ .

Resistor
^ &
_ must be large enough to limit this current & prevent damage

of ` .

During discharge as voltage across reaches to (slightly less than) 1/3LL, the
lower comparator is triggered which turns `a  0 & voltage across capacitor C

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clamps to 1/3LL. The capacitor C is thus charged & discharged between

2/3LL and 1/3LL.

The transient voltage across capacitor in general can be given by

b<       % c<d
Therefore time O taken by capacitor to charge from 1/3bb OP 2/3bb is
O  0.693
^ 
_ W
Also time O taken by capacitor to discharge from 2/3bb OP 1/3bb is
O  0.693
_ W
Therefore total time,
D  O  O  0.693
^  2
_ W
& hence frequency of multivibrator

-

1.45
1

+,
D 
^  2
_ W

Duty cycle can be given as

2% 

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O

^ 
_

i 100.
D
^  2
_

Page 16

Design:-

Result:a) Frequency of square waveform =

b) Peak value of output voltage =
c) Duty-cycle of square waveform =
d) Minimum & maximum voltage across W 
Conclusion:- IC555 timer can produce very accurate & stable time delays, from
microseconds to hours.

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EXPERIMENT NO - 6

DATE :

Aim:- Design & implement second order low pass active filter circuit using
PSpice software
Schematic:-

Theory:A frequency selective electric circuit that passes electric signals of specified
band of frequencies & attenuates the signals of frequencies outside the band
is called an electric filter. In active filters along with passive components
active component like op-amp is used.
Active filters are typically specified by the voltage transfer function,

+# 
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 #
 #
Page 18

+jk  |+jk|% lmn

under steady condition

where |+jk| is magnitude or gain function & ok is phase function.

A stop band response having a 40dB/dec roll-off is obtained with secondorder low-pass filter as shown in figure.
The high cutoff frequency -@ is determined by
 , W ,
 '$K W as follows
-@ 

2pq
 W
 W

For a second-order low-pass Butterworth response, the gain magnitude

equation is


r r

q1  -/-@ 
&s%R%   1 

dt
du

V pass band gain of the filter

-  Frequency of input signal (Hz)

-@  High cutoff frequency of filter (Hz)

Design Steps:Expect having twice roll-off rate in the stop band, the frequency response of
the second-order low-pass filter is identical to that of first-order type.
1] Choose a value for high cutoff frequency
2] To simplify design calculation set
 
 
and W  W  W.
3] Assuming C (e.g. v 1wx) Calculate the value of R.

4] For Butterworth response damping constant of second-order system must

be 0.707.
Select
  0.586
 . assume
 v 100y.

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Design:-

Frequency (Hz)

Vo(p-p) (volts)

Gain (dB)

100
200
300
400
500
700
1K
2K
3K
4K
5K
7K
10k
20k
30k

Result:Cutoff Frequency =

Hz

Roll-off =

dB/dec

Conclusion:- The roll-off rate increases with order of filter. In active filters gain
greater than unity is possible.

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Experiment No-7

Date:

Aim:- Write a VHDL entity to describe a 2:1 multiplexer, synthesize a circuit from the code &
verify its functional correctness.
VHDL Code:library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2 is
Port ( a,b,s : in STD_LOGIC;
f : out STD_LOGIC);
end;
architecture struct of mux2 is
begin
--f<=(a and s)or (not s and b); -- structural description
f<= a when s = '1' else b; -- conditional assignment
end;

RTL Schematic

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Technology Schematic

LUT3_E4

Simulation Result

Experiment No-8

Date:

Aim:- Write a VHDL entity to describe a 4:1 multiplexer using conditional signal assignment,
synthesize a circuit from the code & verify its functional correctness.

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4 is
Port ( a, b, c, d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR(1 downto 0);
f : out STD_LOGIC);
end ;
architecture conditional of mux4 is
begin
f <= a when s = "00" else
b when s = "01" else
c when s = "10" else
d;
end;

RTL Schematic

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Technology Schematic

Simulation Result

Experiment No-9

Date:

Aim:- Write a VHDL entity to describe a 2:1 multiplexer ( 4-bit bus input ) using conditional
signal assignment, synthesize a circuit from the code & verify its functional correctness.

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux2_bus is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
f : out STD_LOGIC_VECTOR (3 downto 0));
end;
architecture Behavioral of mux2_bus is
begin
f<= a when s = '1' else b; -- conditional assignment
end;

RTL Schematic

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Technology Schematic

Simulation Result

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Experiment No-10

Date:

Aim:- Write a VHDL entity to describe a 4:1 multiplexer ( 4-bit bus input ) using hierarchical
approach, synthesize a circuit from the code & verify its functional correctness.
Use 2:1 mux designed in previous example (mux2_bus) as a component.

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_bus is
Port ( d0, d1, d2, d3 : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux4_bus;
architecture hierarchy of mux4_bus is
component mux2_bus port (a,b : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC;
f : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal low, high : STD_LOGIC_VECTOR (3 downto 0);
begin
lowmux
: mux2_bus port map (d0, d1, s(0), low);
highmux
: mux2_bus port map (d2, d3, s(0), high);
finalmux
: mux2_bus port map (low, high, s(1), y);
end hierarchy;

RTL Schematic

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Simulation Result

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Technology Schematic

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Another way of describing mux4:1 without using hierarchy technique. Only change in RTL
schematic no change in technology schematic.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4_bus is
Port ( d0, d1, d2, d3 : in STD_LOGIC_VECTOR (3 downto 0);
s : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC_VECTOR (3 downto 0));
end mux4_bus;
architecture hierarchy of mux4_bus is
begin
y <= d3 when s = "00" else
d2 when s = "01" else
d1 when s = "10" else
d0 ;
end hierarchy;

RTL Schematic

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Date:

Experiment No-11

Aim:- Write a VHDL entity to perform 4-bit addition using ripple carry adder & verify its
functional correctness.
Q(3)

P(3)

Full Adder
(fulladder.vhd)
F3

Y(4)

Q(2)

c3

Y(3)

P(2)

Full Adder
(fulladder.vhd)
F2

Y(2)

Q(1)

c2

P(1)

Full Adder
(fulladder.vhd)
F1

Y(1)

Q(0)

c1

P(0)

Half Adder
(hafadder.vh
d)

Y(0)

VHDl Code
-- hafadder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hafadder is
Port ( a,b : in STD_LOGIC;
y,c : out STD_LOGIC);
end hafadder;
architecture str of hafadder is
begin
y <= a xor b;
c <= a and b;
end str;
-- fulladder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
Port ( x,y,cin : in STD_LOGIC;
f,cout : out STD_LOGIC);
end fulladder;
architecture str of fulladder is
signal w1,w2: STD_LOGIC;
begin
w1 <= x xor y;
w2 <= x and y;
f <= cin xor w1;
cout <= (cin and w1) or w2;
end str;
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-- four_bit_adder.vhd (TOP Module)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_bit_adder is
Port ( P, Q : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC_VECTOR (4 downto 0) );
end four_bit_adder;
architecture hierarchy of four_bit_adder is
component hafadder port(
a, b : in STD_LOGIC;
y, c : out STD_LOGIC);
end component;
component fulladder port(
x, y, cin : in STD_LOGIC;
f, cout : out STD_LOGIC);
end component;
signal c1,c2,c3 : std_logic;
begin
H1: hafadder
F1: fulladder
F2: fulladder
F3: fulladder
end hierarchy;

port map(P(0),Q(0),Y(0),c1);
port map(P(1),Q(1),c1,Y(1),c2);
port map(P(2),Q(2),c2,Y(2),c3);
port map(P(3),Q(3),c3,Y(3),Y(4));

Simulation Result

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Experiment No-12

Date:

Aim :- Write & simulate VHDL code for 1011 sequence detector.

State Diagram:-

VHDL Code:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity example is
Port ( clk, rst : in STD_LOGIC;
A : in STD_LOGIC;
f : out STD_LOGIC);
end example;
architecture Behavioral of example is
type statetype is (s1,s2,s3,s4,s5);
signal state,nextstate:statetype ;
begin
-- state register
Process (clk,rst)
begin
if rst='1' then state <= s1;
else if clk'event and clk='1' then state <= nextstate; end if;
end if;
end process;
--next state logic
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Process (state,A)
begin
case state is
when s1=> if A='1' then nextstate <= s2;
elsif A='0' then nextstate <= s1;end if;
when s2=> if A='1' then nextstate <= s2;
elsif A='0' then nextstate <= s3;end if;
when s3=> if A='1' then nextstate <= s4;
elsif A='0' then nextstate <= s1;end if;
when s4=> if A='1' then nextstate <= s5;
elsif A='0' then nextstate <= s3;end if;
when s5=> if A='1' then nextstate <= s2;
elsif A='0' then nextstate <= s3;end if;
when others => nextstate <= s1;
end case;
end process;
-- output logic
f<='1' when state = s5 else '0';
end Behavioral;

Simulation Result

Experiment No-13

Date:

Aim:- Write & simulate VHDL code for 111 sequence detector
State Diagram:-

VHDL Code:library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity asd is
Port ( clk,rst : in STD_LOGIC;
A : in STD_LOGIC;
f : out STD_LOGIC);
end asd;
architecture Behavioral of asd is
type statetype is (s1,s2,s3,s4);
signal state,nextstate:statetype ;
begin
-- state register
Process (clk,rst)
begin
if rst='1' then state <= s1;
else if clk'event and clk='1' then state <= nextstate;end if;
end if;
end process;

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--next state logic

process (state,A)
begin
case state is
when s1=> if A='1' then nextstate <= s2;
elsif A='0' then nextstate <= s1;end if;
when s2=> if A='1' then nextstate <= s3;
elsif A='0' then nextstate <= s1;end if;
when s3=> if A='1' then nextstate <= s4;
elsif A='0' then nextstate <= s1;end if;
when s4=> if A='1' then nextstate <= s4;
elsif A='0' then nextstate <= s1;end if;
when others => nextstate <= s1;
end case;
end process;
-- output logic
f<='1' when state = s4 else '0';
'0'
end Behavioral;

Simulation Result

Experiment No-14
Aim :- Write VHDL code for 4
4-bit Up down Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;

Simulation Result

Date:

Experiment No-15

Date:

Aim :- Write VHDL code for 4

4-bit
bit ring counter with asynchronous load & clear
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter is
Port ( clk,clr,load : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (3 downto 0);
q : out STD_LOGIC_VECTOR (3 downto 0));
end ring_counter;
architecture Behavioral of ring_counter is
signal temp : std_logic_vector (3 downto 0);
begin
process(clr,clk,load)
begin
if clr='0' then temp <= "0000";
elsif load = '1' then temp <=a;
elsif clk'event and clk='1' then
temp <= temp(2 downto 0)& temp(3);
end if;
end process;
q<=temp;
end Behavioral;
Simulation Result

library
library <LIB_NAME>;
use <LIB_NAME>.<PACKAGE_NAME>.all
use IEEE.math_complex.all;
use IEEE.math_real.all;
use IEEE.numeric_bit.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_unsigned.all;
Commonly used
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Operators
Arithmetic
--The following are the arithmetic operators as defined by the VHDL language.
+ ---- Addition
- ---- Subtraction
* ---- Multiplication
/ ---- Divide
mod ---- Modulus
** ---- Power Operator (i.e. 2**8 returns 256)
Bitwise
--The following operators can be used on two single bits to produce a single bit
--output or two equivelent sized bused signals where the operations are performed
--on each bit of the bus. In the case of the Invert, only one signal or bus is
--provided and the operation occurs on each bit of the signal.
NOT ---- Invert a single-bit signal or each bit in a bus
AND ---- AND two single bits or each bit between two buses
OR ---- OR two single bits or each bit between two buses
XOR ---- XOR two single bits or each bit between two buses
XNOR ---- XNOR two single bits or each bit between two buses
Concatenate
--The following operators either concatenates several bits into a bus or replicate
--a bit or combination of bits multiple times.
a & b & c ---- Concatenate a, b and c into a bus
Logical
--The following logical operators are used in conditional TRUE/FALSE statements
--such as an if statement in order to specify the condition fo the operation.
NOT ---- Not True
AND ---- Both Inputs True
OR ---- Either Input True
= ---- Inputs Equal
/= ---- Inputs Not Equal
< ---- Less-than
<= ---- Less-than or Equal
> ---- Greater-than
>= ---- Greater-than or Equal

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--The IEEE.numeric_std library will need to be acessed for functions given below
Rotate Left
<signed_sig> rol <shift_amount_in_integer>;
<unsigned_sig> rol <shift_amount_in_integer>;
Rotate Right
<signed_sig> ror <shift_amount_in_integer>;
<unsigned_sig> ror <shift_amount_in_integer>;
Shift Left Arithmetic
<signed_sig> sla <shift_amount_in_integer>;
<unsigned_sig> sla <shift_amount_in_integer>;
Shift Left Logical
<signed_sig> sll <shift_amount_in_integer>;
<unsigned_sig> sll <shift_amount_in_integer>;
Shift Right Arithmetic
<signed_sig> sra <shift_amount_in_integer>;
<unsigned_sig> sra <shift_amount_in_integer>;
Shift Right Logical
<signed_sig> srl <shift_amount_in_integer>;
<unsigned_sig> srl <shift_amount_in_integer>;
Operator end
Ports
Input
<port_name> : in std_logic_vector(15 downto 0);
<port_name> : in std_logic;
Output
<port_name> : out std_logic_vector(3 downto 0);
<port_name> : out std_logic;
Bidirectional
<port_name> : inout std_logic_vector(7 downto 0);
<port_name> : inout std_logic;
Predefined types
STD_LOGIC
--'U','X','0','1','Z','W','L','H','-'
STD_LOGIC_VECTOR
--Natural Range of STD_LOGIC
BOOLEAN
--True or False
INTEGER
--32 or 64 bits
NATURAL
--Integers >= 0
POSITIVE
--Integers > 0
REAL
--Floating-point
BIT
--'0','1'
BIT_VECTOR(Natural) --Array of bits
CHARACTER
--7-bit ASCII
STRING(POSITIVE)
--Array of characters
TIME
--hr, min, sec, ms, us, ns, ps, fs
DELAY_LENGTH
--Time >= 0

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Finite State-machines (FSM)

There are several methods to code state-machines however following certain coding
styles ensures the synthesis tool FSM (Finite State-Machine) extraction algorithms properly
identify and optimize the state-machine as well as possibly improving the simulation, timing
and debug of the circuit.
The following examples are broken down into Mealy implementations.
The basic trade-offs for each implementation is explained below.
The general recommendation for the choice of state-machine depends on the target
architecture and specifics of the state-machine size and behavior however typically, Moore
style state-machines implement better for FPGAs and Mealy implement best for CPLDs.
Mealy vs. Moore Styles
There are two well known implementation styles for state-machines, Mealy and
Moore.
The main difference between Mealy and Moore styles is the Mealy state-machine
determines the output values based on both the current state as well as the inputs to the
state-machine where Moore determines its outputs solely on the state.
In general, Moore type of state-machines implement best in FPGAs due to the fact
that most often one-hot state-machines are the chosen encoding method and there is little
or no decode and thus logic necessary for output values. If a binary encoding is used, it is
possible that a more compact and sometimes faster state-machine can be built using the
Mealy method however this is not always true and not easy to determine without knowing
more specifics of the state-machine.
One-hot vs. Binary Encoding
There are several encoding methods for state-machine design however the two most
popular for FPGA or CPLD design are binary and one-hot.
For most FPGA architectures, one-hot is the better encoding method due the
abundance for FF resources and the lesser fan-in requirements for the next state-equation
(maps better into LUTs).
When targeting CPLDs, binary can many times work better due to the logic structure of the
CPLD and fewer register resources. In any case, most modern synthesis tools contain FSM
extraction algorithms that can identify state-machine code and choose the best encoding
method for the size, type and target architecture.
Even though this facility exists, many times it can be most advantageous to manually
code and control the best encoding scheme for the design to allow better control and
possibly ease debug of the implemented design. It is suggested to consult the synthesis
tool documentation for details about the state-machine extraction capabilities of the
synthesis tool you are using.
Safe vs. Fast
When coding a state-machine, there are two generally conflicting goals that must be
understood, safe vs. fast. A safe state-machine implementation refers to the case where if a
state-machine should get an unknown input or into an unknown state that it can recover
into a known state the next clock cycle and resume from recovery state. On the other hand,
if this requirement is discarded (no recovery state) many times the state-machine can be
implemeted with less logic and more speed than if state-machine recovery is necessary.
How to design a safe state-machine generally involves coding in a default state into the
state-machine next-state case clause and/or specifying to the synthesis tool to implement
the state-machine encoding in a "safe" mode. Again it is suggested to consult the synthesis
tool documentation for details about implementing a safe state-machine.
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