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    Swati CV+

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    neerajbakshi
    Himanshi is a VLSI verification engineer with experience in digital design and simulation tools like Questa Sim, ModelSim, and Virtuoso. She has a M.Tech in VLSI Design from KUK and designed a D flip flop using CMOS 180nm technology and an I2C bus using Verilog. Her technical skills include Verilog, SystemVerilog, digital design, FPGA programming, and she has worked on projects involving I2C protocol and ASIC/FPGA flows.

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    Swati CV+

    Uploaded by

    neerajbakshi
    58 views2 pages
    Himanshi is a VLSI verification engineer with experience in digital design and simulation tools like Questa Sim, ModelSim, and Virtuoso. She has a M.Tech in VLSI Design from KUK and designed a D flip flop using CMOS 180nm technology and an I2C bus using Verilog. Her technical skills include Verilog, SystemVerilog, digital design, FPGA programming, and she has worked on projects involving I2C protocol and ASIC/FPGA flows.

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    Himanshi is a VLSI verification engineer with experience in digital design and simulation tools like Questa Sim, ModelSim, and Virtuoso. She has a M.Tech in VLSI Design from KUK and designed a D flip flop using CMOS 180nm technology and an I2C bus using Verilog. Her technical skills include Verilog, SystemVerilog, digital design, FPGA programming, and she has worked on projects involving I2C protocol and ASIC/FPGA flows.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    58 views2 pages

    Swati CV+

    Uploaded by

    neerajbakshi
    Himanshi is a VLSI verification engineer with experience in digital design and simulation tools like Questa Sim, ModelSim, and Virtuoso. She has a M.Tech in VLSI Design from KUK and designed a D flip flop using CMOS 180nm technology and an I2C bus using Verilog. Her technical skills include Verilog, SystemVerilog, digital design, FPGA programming, and she has worked on projects involving I2C protocol and ASIC/FPGA flows.

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    of 2

    HIMANSHI

    Email:-vertexhima@gmail.com
    Mob: - +91-8105539750, Bangalore.

    EXPERIENCE: TECHNICALSKILLS:
    VLSI Verification Engineer Trainee VLSI Domain Skills

    Jan.2018 - Sep.2018, DKOP Labs Pvt. Ltd. Noida ❖ HDL: Verilog, TCL, Linux.
    ❖ Domain: ASIC/FPGA Design
    Roles and Responsibities:- flow, Digital IC Design.
    • Good knowledge of Digital Design. ❖ Knowledge: RTL Coding, Simulation,
    • Good hands on the tool Questa Sim and Model Sim. Synthesis.
    • Worked on Basys 2 Spartan 3E FPGA (Field Programmable ❖ Tool: Virtuoso, LT-Spice,
    Logic Array) board. Athena, Questa Sim, Modelsim,
    • Design and simulation of I2C Protocol. FPGA, Xilinx.
    ❖ Miscellaneous: C, C++.
    Previous Experience:-
    Electronics Engineer in Quality Department in Maffick TRAINING:
    Instruments Pvt. Ltd. (June 2014 - July 2015).
    ❖ Six weeks training in
    Roles and Responsibities:- BSNL, Ambala (May,
    • As Electronics Engineer my duties to instruct the whole 2012).
    production team. ❖ Six weeks training in
    • Give more ideas to increase production. ERDC, Ambala (May,
    • Audit some of TS (Temperature Sensors) to ensure the 2013).
    production is going well or not.
    • Some experiments done on TS for better result.

    EDUCATION:

    Degree Year of Exam University/Board Percentage


    M.Tech (VLSI Design) 2016-2018 KUK 6.70(CGPA)
    B.Tech (ECE) 2010-2014 KUK 65.92%
    th
    12 2009-2010 HBSE 68.20%
    10th 2007-2008 HBSE 70.60%
    .
    PROJECT TITLE:

    M.Tech (VLSI Design)-2017

    Design of D Flip Flop using CMOS. This D flip flop has been implemented using 180 nm
    Abstract
    Technology.

    Tools Virtuoso.
    M.Tech (VLSI Design)-2018

    I2C (Inter Integrated Circuit) Bus. The design is described using the Verilog hardware
    description language.I2C Bus provides the communication between system processor and
    peripheral devices. It is used to minimize system level hardware. The I2C Bus is a
    Abstract two wire serial protocol. Hence I2C Bus components can be interfaced by using only two
    lines. First one is serial data (SDA) line and second is serial clock (SCL) line. It is a very
    popular and powerful bus used for communication between a master or multiple
    masters and a single slave or multiple slave devices.

    Tools Modelsim.

    ADDITIONAL INFORMATION:

    Father’s Name: Mr. Mohan Das Dangi


    Date of Birth: 09-01-1993
    Gender: Female
    Marital Status: Single
    Major strengths: Easy Learner, Positive Attitude, Good listener, Punctual, Hardworking.

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