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Experiment No. 6

This document summarizes an experiment involving the implementation of various digital circuits in Verilog. The aim was to write Verilog programs for a full adder, full adder using structural modeling, 3:8 decoder, and 4-bit full adder using structural modeling. The code and modules for each circuit are provided, along with waveform and RTL views. The results confirm that a full adder, 4-bit full adder, and 3:8 decoder were successfully implemented in Verilog using structural and behavioral modeling.

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Hrishikesh Ugle
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68 views

Experiment No. 6

This document summarizes an experiment involving the implementation of various digital circuits in Verilog. The aim was to write Verilog programs for a full adder, full adder using structural modeling, 3:8 decoder, and 4-bit full adder using structural modeling. The code and modules for each circuit are provided, along with waveform and RTL views. The results confirm that a full adder, 4-bit full adder, and 3:8 decoder were successfully implemented in Verilog using structural and behavioral modeling.

Uploaded by

Hrishikesh Ugle
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment no.

6
Experiment Date: 7th Sept 2019 Submission Date: 7th Nov 2019

Aim :
1. To write a Verilog program for implementation of full adder.
2. To write a Verilog program for implementation of full adder using structural
style of modelling.
3. To write a Verilog program for implementation of 3:8 decoder.
4. To write a Verilog program for implementation of 4 bit full adder using
structural style of modelling.

Software Used :
Intel Quartus II

Code :

A. Full Adder
module adder (i1, i2, cin, s, cout);
input i1, i2, cin;
output s, cout;

assign s = i1 ^ i2 ^ cin;
assign cout = (i1 & i2) | (cin & i2) | (cin & i1);
endmodule

B. Full Adder (Structural)


module fulladder (x, y, cin, sum, cout);
input x, y, cin;
output sum, cout;
wire t1, t2, t3;

HA H1(x, y, t1, t2);


HA H2(t1, cin, sum, t3);
OR1 o1(t2, t3, cout);

endmodule

module HA (a,b,s,c);
input a,b;
output s,c;

assign s = a ^ b;
assign c = a & b;

endmodule

module OR1 (j, k, l);


input j,k;
output l;
assign l = j | k;
endmodule

C. Decoder
module danidecoder (i, o);
input [2:0] i;
output [7:0] o;

reg [7:0] o;
always @ (i)
begin
case (i)
3'b000 : o = 8'b00000001;
3'b001 : o = 8'b00000010;
3'b010 : o = 8'b00000100;
3'b011 : o = 8'b00001000;
3'b100 : o = 8'b00010000;
3'b101 : o = 8'b00100000;
3'b110 : o = 8'b01000000;
3'b111 : o = 8'b10000000;
endcase

2
end
endmodule
D. 4 Bit Full Adder
module fulldaniadder(m, n, Cin, Sum, Cout);
input [3:0] m,n;
input Cin;
output [3:0] Sum;
output Cout;
wire t1, t2, t3;
FA F1 (m[0], n[0], Cin, Sum[0], t1);
FA F2 (m[1], n[1], t1, Sum[1], t2);
FA F3 (m[2], n[2], t2, Sum[2], t3);
FA F4 (m[3], n[3], t3, Sum[3], Cout);
endmodule

module FA (x, y, cin, sum, cout);


input x, y, cin;
output sum, cout;
wire t1, t2, t3;
HA H1(x, y, t1, t2);
HA H2(t1, cin, sum, t3);
OR1 o1(t2, t3, cout);
endmodule

module HA (a,b,s,c);
input a,b;
output s,c;
assign s = a ^ b;
assign c = a & b;
endmodule

module OR1 (j, k, l);


input j,k;
output l;
assign l = j | k;
endmodule

3
Waveforms :

D. 4 Bit Full Adder

A. Full adder

4
RTL View :

A. Full adder

B. 4 Bit Full Adder

Results :
1. A Verilog program for a full adder using structural style of modelling was
implemented.
2. 4 bit full adder was implemented using 4 full adders by structural style of
modelling in VHDL.
3. A Verilog program for 3:8 decoder using behavioural style of modelling was
implemented.

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