® ADS

782
5 ADS7825
ADS
782
5

www.burr-brown.com/databook/ADS7825.html

4 Channel, 16-Bit Sampling CMOS A/D Converter

FEATURES DESCRIPTION
● 25µs max SAMPLING AND CONVERSION The ADS7825 can acquire and convert 16 bits to
● SINGLE +5V SUPPLY OPERATION within ±2.0 LSB in 25µs max while consuming only
50mW max. Laser-trimmed scaling resistors provide
● PIN-COMPATIBLE WITH 12-BIT ADS7824
the standard industrial ±10V input range and channel-
● PARALLEL AND SERIAL DATA OUTPUT to-channel matching of ±0.1%. The ADS7825 is a
● 28-PIN 0.3" PLASTIC DIP AND SOIC low-power 16-bit sampling A/D with a four channel
● ±2.0 LSB max INL input multiplexer, S/H, clock, reference, and a
parallel/serial microprocessor interface. It can be con-
● 50mW max POWER DISSIPATION
figured in a continuous conversion mode to sequen-
● 50µW POWER DOWN MODE tially digitize all four channels. The 28-pin ADS7825
● ±10V INPUT RANGE, FOUR CHANNEL is available in a plastic 0.3" DIP and in a SOIC, both
MULTIPLEXER fully specified for operation over the industrial –40°C
● CONTINUOUS CONVERSION MODE to +85°C range.

Continuous Conversion Channel

CONTC A0 A1
40kΩ R/C
AIN0 CS
Successive Approximation Register
Clock
and Control Logic
20kΩ 8kΩ PWRD

40kΩ
CDAC
AIN1

BUSY
20kΩ 8kΩ
Serial DATACLK
40kΩ
AIN2 Comparator Data
Out SDATA
or
20kΩ 8kΩ
Parallel
40kΩ
AIN3 Data 8
D7-D0
Out

20kΩ 8kΩ BYTE

Buffer Internal
CAP +2.5V Ref
6kΩ
REF

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

©
1996 Burr-Brown Corporation PDS-1304B
1 ADS7825
Printed in U.S.A. October, 1997
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, f S = 40kHz, VS1 = VS2 = VS = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.

ADS7825P, U ADS7825PB, UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻(1) Bits

ANALOG INPUT
Voltage Range ±10V ✻ V
Impedance Channel On or Off 45.7 ✻ kΩ
Capacitance 35 ✻ pF

THROUGHPUT SPEED
Conversion Time 20 ✻ µs
Acquisition Time 5 ✻ µs
Multiplexer Settling Time Includes Acquisition 5 ✻ µs
Complete Cycle (Acquire and Convert) 25 ✻ µs
Complete Cycle (Acquire and Convert) CONTC = +5V 40 ✻ µs
Throughput Rate 40 ✻ kHz
DC ACCURACY
Integral Linearity Error ±3 ±2 LSB(2)
No Missing Codes 15 16
Transition Noise(3) 0.8 ✻ LSB
Full Scale Error(4) Internal Reference ±0.5 ±0.25 %
Full Scale Error Drift Internal Reference ±7 ±5 ppm/°C
Full Scale Error(4) ±0.5 ±0.25 %
Full Scale Error Drift ±2 ✻ ppm/°C
Bipolar Zero Error ±10 ✻ mV
Bipolar Zero Error Drift ±2 ✻ ppm/°C
Channel-to-Channel Mismatch ±0.1 ±0.1 %
Power Supply Sensitivity +4.75 < VS < +5.25 ±8 ✻ LSB

AC ACCURACY
Spurious-Free Dynamic Range(5) fIN = 1kHz 90 ✻ dB
Total Harmonic Distortion fIN = 1kHz –90 ✻ dB
Signal-to-(Noise+Distortion) fIN = 1kHz 83 86 dB
Signal-to-Noise fIN = 1kHz 83 86 dB
Channel Separation(6) fIN = 1kHz 100 120 ✻ ✻ dB
–3dB Bandwidth 2 ✻ MHz
Useable Bandwidth(7) 90 ✻ kHz

SAMPLING DYNAMICS
Aperture Delay 40 ✻ ns
Transient Response(8) FS Step 5 ✻ µs
Overvoltage Recovery(9) 1 ✻ µs

REFERENCE
Internal Reference Voltage 2.48 2.5 2.52 ✻ ✻ ✻ V
Internal Reference Source Current 1 ✻ µA
(Must use external buffer)
External Reference Voltage Range 2.3 2.5 2.7 ✻ ✻ ✻ V
for Specified Linearity
External Reference Current Drain VREF = +2.5V 100 ✻ µA

DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 ✻ ✻ V
VIH +2.4 VS +0.3V ✻ ✻ V
IIL ±10 ✻ µA
IIH ±10 ✻ µA

DIGITAL OUTPUTS
Data Format Parallel in two bytes; Serial ✻
Data Coding Binary Two's Complement ✻
VOL ISINK = 1.6mA +0.4 ✻ V
VOH ISOURCE = 500µA +4 ✻ V
Leakage Current High-Z State, VOUT = 0V to VS ±5 ✻ µA
Output Capacitance High-Z State 15 ✻ pF

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS7825 2
SPECIFICATIONS (CONT)
ELECTRICAL
At TA = –40°C to +85°C, fS = 40kHz, VS1 = VS2 = V S = +5V ±5%, using external reference, CONTC = 0V, unless otherwise specified.

ADS7825P, U ADS7825PB, UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

DIGITAL TIMING
Bus Access Time PAR/SER = +5V 83 ✻ ns
Bus Relinquish Time PAR/SER = +5V 83 ✻ ns
Data Clock PAR/SER = 0V
Internal Clock (Output only when EXT/INT LOW 0.5 1.5 ✻ ✻ MHz
transmitting data)
External Clock EXT/INT HIGH 0.1 10 ✻ ✻ MHz
POWER SUPPLIES
VS1 = VS2 = VS +4.75 +5 +5.25 ✻ ✻ ✻ V
Power Dissipation fS = 40kHz 50 ✻ mW
PWRD HIGH 50 ✻ µW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻ ✻ °C
Storage –65 +150 ✻ ✻ °C
Thermal Resistance (θJA)
Plastic DIP 75 ✻ °C/W
SOIC 75 ✻ °C/W

NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 16-bit, ±10V input ADS7825, one LSB is 305µV. (3)
Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and
last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. (5) All specifications in dB are referred
to a full-scale ±10V input. (6) A full scale sinewave input on one channel will be attenuated by this amount on the other channels. (7) Useable Bandwidth defined as
Full-Scale input frequency at which Signal-to-(Noise+Distortion) degrades to 60dB, or 10 bits of accuracy. (8) The ADS7825 will accurately acquire any input step if given
a full acquisition period after the step. (9) Recovers to specified performance after 2 x FS input overvoltage, and normal acquisitions can begin.

PACKAGE/ORDERING INFORMATION
PACKAGE MINIMUM SIGNAL-
DRAWING TEMPERATURE MAXIMUM INTEGRAL TO-(NOISE + DISTORTION)
PRODUCT PACKAGE NUMBER(1) RANGE LINEARITY ERROR (LSB) RATIO (dB)

ADS7825P Plastic Dip 246 –40°C to +85°C ±3 83

ADS7825PB Plastic Dip 246 –40°C to +85°C ±2 86
ADS7825U SOIC 217 –40°C to +85°C ±3 83
ADS7825UB SOIC 217 –40°C to +85°C ±2 86

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION

Analog Inputs: AIN0, AIN1, AIN2, AIN3 .............................................. ±15V TOP VIEW DIP/SOIC
REF ................................... (AGND2 –0.3V) to (VS + 0.3V)
CAP ........................................ Indefinite Short to AGND2,
Momentary Short to VS AGND1 1 28 VS1
VS1 and VS2 to AGND2 ........................................................................... 7V
AIN0 2 27 VS2
VS1 to VS2 .......................................................................................... ±0.3V
Difference between AGND1, AGND2 and DGND ............................. ±0.3V AIN1 3 26 PWRD
Digital Inputs and Outputs .......................................... –0.3V to (VS + 0.3V)
Maximum Junction Temperature ..................................................... 150°C AIN2 4 25 CONTC
Internal Power Dissipation ............................................................. 825mW
Lead Temperature (soldering, 10s) ................................................ +300°C AIN3 5 24 BUSY
Maximum Input Current to Any Pin ................................................. 100mA
CAP 6 23 CS

REF 7 22 R/C
ADS7825
ELECTROSTATIC AGND2 8 21 BYTE

DISCHARGE SENSITIVITY TRI-STATE D7 9 20 PAR/SER

This integrated circuit can be damaged by ESD. Burr-Brown TRI-STATE D6 10 19 A0

recommends that all integrated circuits be handled with TRI-STATE D5 11 18 A1
appropriate precautions. Failure to observe proper handling
EXT/INT D4 12 17 D0 TAG
and installation procedures can cause damage.
SYNC D3 13 16 D1 SDATA
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits DGND 14 15 D2 DATACLK
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
®

3 ADS7825
PIN ASSIGNMENTS

PIN # NAME I/O DESCRIPTION

1 AGND1 Analog Ground. Used internally as ground reference point.
2 AIN0 Analog Input Channel 0. Full-scale input range is ±10V.
3 AIN 1 Analog Input Channel 1. Full-scale input range is ±10V.
4 AIN 2 Analog Input Channel 2. Full-scale input range is ±10V.
5 AIN 3 Analog Input Channel 3. Full-scale input range is ±10V.
6 CAP Internal Reference Output Buffer. 2.2µF Tantalum to ground.
7 REF Reference Input/Output. Outputs +2.5V nominal. If used externally, must be buffered to maintain ADS7825 accuracy.
Can also be driven by external system reference. In both cases, bypass to ground with a 2.2µF Tantalum capacitor.
8 AGND2 Analog Ground.
9 D7 O Parallel Data Bit 7 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
10 D6 O Parallel Data Bit 6 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
11 D5 O Parallel Data Bit 5 if PAR/SER HIGH; Tri-state if PAR/SER LOW. See Table I.
12 D4 I/O Parallel Data Bit 4 if PAR/SER HIGH; if PAR/SER LOW, a LOW level input here will transmit serial data on SDATA from
the previous conversion using the internal serial clock; a HIGH input here will transmit serial data using an external serial
clock input on DATACLK (D2). See Table I.
13 D3 O Parallel Data Bit 3 if PAR/SER HIGH; SYNC output if PAR/SER LOW. See Table I.
14 DGND Digital Ground.
15 D2 I/O Parallel Data Bit 2 if PAR/SER HIGH; if PAR/SER LOW, this will output the internal serial clock if EXT/INT (D4) is LOW;
will be an input for an external serial clock if EXT/INT (D4) is HIGH. See Table I.
16 D1 O Parallel Data Bit 1 if PAR/SER HIGH; SDATA serial data output if PAR/SER LOW. See Table I.
17 D0 I/O Parallel Data Bit 0 if PAR/SER HIGH; TAG data input if PAR/SER LOW. See Table I.
18 A1 I/O Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.
19 A0 I/O Channel Address. Input if CONTC LOW, output if CONTC HIGH. See Table I.
20 PAR/SER I Select Parallel or Serial Output. If HIGH, parallel data will be output on D0 thru D7. If LOW, serial data will be output on
SDATA. See Table I and Figure 1.
21 BYTE I Byte Select. Only used with parallel data, when PAR/SER HIGH. Determines which byte is available on D0 thru D7.
Changing BYTE with CS LOW and R/C HIGH will cause the data bus to change accordingly. LOW selects the 8 MSBs;
HIGH selects the 8 LSBs. See Figures 2 and 3
22 R/C I Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a
conversion. With CS LOW, a rising edge on R/C enables the output data bits if PAR/SER HIGH, or starts transmission
of serial data if PAR/SER LOW and EXT/INT HIGH.
23 CS I Chip Select. Internally OR'd with R/C. With CONTC LOW and R/C LOW, a falling edge on CS will initiate a conversion.
With R/C HIGH, a falling edge on CS will enable the output data bits if PAR/SER HIGH, or starts transmission of serial
data if PAR/SER LOW and EXT/INT HIGH.
24 BUSY O Busy Output. Falls when conversion is started; remains LOW until the conversion is completed and the data is latched
into the output register. In parallel output mode, output data will be valid when BUSY rises, so that the rising edge
can be used to latch the data.
25 CONTC I Continuous Conversion Input. If LOW, conversions will occur normally when initiated using CS and R/C; if HIGH,
acquisition and conversions will take place continually, cycling through all four input channels, as long as CS, R/C and
PWRD are LOW. See Table I. For serial mode only.
26 PWRD I Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the
previous conversion are maintained in the output register. In the continuous conversion mode, the multiplexer address
channel is reset to channel 0.
27 VS2 Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
28 VS1 Supply Input. Nominally +5V. Connect directly to pin 27.

ADS7825 4
TYPICAL PERFORMANCE CURVES
At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted.

FREQUENCY SPECTRUM CROSSTALK vs INPUT FREQUENCY

(8192 Point FFT; fIN = 1.02kHz, –0.5dB) (Active Channel Amplitude = –0.1dB)
0

Resulting Amplitude on Selected Channel (dB)

–60.0
–10
–20 –70.0
Adjacent Channels, Worst Pair
–30
–80.0
Amplitude (dB)

–40

(Input Grounded)
–50 –90.0 Adjacent Channels
–60
–100.0
–70 Non-Adjacent Channels
–80 –110.0
–90
–100 –120.0
–110 Measurement Limit
–130.0
–120
–130 –140.0
0 5 10 15 20 100 1k 10k 100k
Frequency (kHz) Active Channel Input Frequency (Hz)

ADJACENT CHANNEL CROSSTALK, WORST PAIR ADJACENT CHANNEL CROSSTALK, WORST PAIR
(8192 Point FFT; AIN3 = 1.02kHz, –0.1dB; AIN2 = AGND) (8192 Point FFT; AIN3 = 10.1kHz, –0.1dB; AIN2 = AGND )
0 0
–10 –10
–20 –20
–30 –30
Amplitude (dB)

Amplitude (dB)

–40 –40
–50 –50
–60 –60
–70 –70
–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
0 5 10 15 20 0 5 10 15 20
Frequency (kHz) Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) SIGNAL-TO-(NOISE + DISTORTION)

vs INPUT FREQUENCY (fIN = –0.1dB) vs INPUT FREQUENCY AND INPUT AMPLITUDE
100 100
90
90 0dB
80
80 –20dB
70
SINAD (dB)
SINAD (dB)

70 60

60 50

40
50 –60dB
30
40
20

30 10
100 1k 10k 100k 0 2 4 6 8 10 12 14 16 18 20
Input Signal Frequency (Hz) Input Signal Frequency (kHz)

5 ADS7825
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted.

A. C. PARAMETERS vs TEMPERATURE
(fIN = 1kHz, –0.1dB)
110 –110 3
2 All Codes INL

16-Bit LSBs
SFDR, SINARD, and SNR (dB)

105 –105 1
SFDR 0
–1
100 –100 –2

THD (dB)
–3
95 –95 0 8192 16384 24576 32768 40960 49152 57344 65535
SNR Decimal Code
THD
90 –90
3
85 –85 2 All Codes DNL

16-Bit LSBs
SINAD 1
0
80 –80
–1
–50 –25 0 25 50 75 100
–2
Temperature (°C) –3
0 8192 16384 24576 32768 40960 49152 57344 65535
Decimal Code

ENDPOINT ERRORS
2
POWER SUPPLY RIPPLE SENSITIVITY BPZ Error
mV From Ideal

INL/DNL DEGRADATION PER LSB OF P-P RIPPLE 1

1
0
Linearity Degradation (LSB/LSB)

–1
10–1
–2

10–2 0.2
INL
From Ideal
Percent

+FS Error
10–3 0

10–4 –0.2

DNL 0.2
10–5 –FS Error
From Ideal

101 102 103 104 105 106 107

Percent

0
Power Supply Ripple Frequency (Hz)

–0.2
–50 –25 0 25 50 75 100
Temperature (°C)
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE CONVERSION TIME vs TEMPERATURE
2.520 20.4

2.515

20.2
Internal Reference (V)

2.510
Conversion Time (µs)

2.505

2.500 20

2.495

2.490 19.8

2.485

2.480 19.6
–50 –25 0 25 50 75 100 –50 –25 0 25 50 75 100
Temperature (°C) Temperature (°C)

ADS7825 6
BASIC OPERATION
PARALLEL OUTPUT SERIAL OUTPUT
Figure 1a shows a basic circuit to operate the ADS7825 with Figure 1b shows a basic circuit to operate the ADS7825 with
parallel output (Channel 0 selected). Taking R/C (pin 22) serial output (Channel 0 selected). Taking R/C (pin 22)
LOW for 40ns (12µs max) will initiate a conversion. BUSY LOW for 40ns (12µs max) will initiate a conversion and
(pin 24) will go LOW and stay LOW until the conversion is output valid data from the previous conversion on SDATA
completed and the output register is updated. If BYTE (pin (pin 16) synchronized to 16 clock pulses output on
21) is LOW, the 8 most significant bits will be valid when DATACLK (pin 15). BUSY (pin 24) will go LOW and stay
pin 24 rises; if BYTE is HIGH, the 8 least significant bits LOW until the conversion is completed and the serial data
will be valid when BUSY rises. Data will be output in has been transmitted. Data will be output in Binary Two’s
Binary Two’s Complement format. BUSY going HIGH can Complement format, MSB first, and will be valid on both the
be used to latch the data. After the first byte has been read, rising and falling edges of the data clock. BUSY going
BYTE can be toggled allowing the remaining byte to be HIGH can be used to latch the data. All convert commands
read. All convert commands will be ignored while BUSY is will be ignored while BUSY is LOW.
LOW. The ADS7825 will begin tracking the input signal at the end
The ADS7825 will begin tracking the input signal at the end of the conversion. Allowing 25µs between convert com-
of the conversion. Allowing 25µs between convert com- mands assures accurate acquisition of a new signal.
mands assures accurate acquisition of a new signal.

Parallel Output

(a)
1 28
0.1µF 10µF
±10V 2 27 + + +5V

3 26

4 25
BUSY
5 24
Convert Pulse
+ 6 23
2.2µF R/C
+ 7 22
2.2µF ADS7825 BYTE
8 21
40ns min
9 20 +5V(1)

10 19

11 18

12 17

13 16

14 15

(b)
Serial Output
Pin 21 D15 D14 D13 D12 D11 D10 D9 D8
LOW
Pin 21 D7 D6 D5 D4 D3 D2 D1 D0 1 28
HIGH 0.1µF 10µF
NOTE: (1) PAR/SER = 5V
±10V 2 27 + + +5V

3 26

4 25

5 24 BUSY
Convert Pulse
+ 6 23
2.2µF
+ 7 22 R/C
2.2µF ADS7825
8 21
40ns min
(3)
NC(2) 9 20

NC(2) 10 19

NC(2) 11 18

EXT/INT 12 17

SYNC 13 16 SDATA

14 15 DATACLK(1)
NOTES: (1) DATACLK (pin 15) is an output when EXT/INT (pin 12) is LOW
and an input when EXT/INT is HIGH. (2) NC = no connection. (3) PAR/SER = 0V.

FIGURE 1. Basic Connection Diagram, (a) Parallel Output, (b) Serial Output.

7 ADS7825
STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) LOW for initiating a conversion. If, however, it is critical that CS or
a minimum of 40ns places the sample/hold of the ADS7825 R/C initiates conversion ‘n’, be sure the less critical input is
in the hold state and starts conversion ‘n’. BUSY (pin 24) LOW at least 10ns prior to the initiating input. If EXT/INT
will go LOW and stay LOW until conversion ‘n’ is com- (pin 12) is LOW when initiating conversion ‘n’, serial data
pleted and the internal output register has been updated. All from conversion ‘n – 1’ will be output on SDATA (pin 16)
new convert commands during BUSY LOW will be ignored. following the start of conversion ‘n’. See Internal Data
CS and/or R/C must go HIGH before BUSY goes HIGH or Clock in the Reading Data section.
a new conversion will be initiated without sufficient time to To reduce the number of control pins, CS can be tied LOW
acquire a new signal. using R/C to control the read and convert modes. This will
The ADS7825 will begin tracking the input signal at the end have no effect when using the internal data clock in the serial
of the conversion. Allowing 25µs between convert com- output mode. However, the parallel output and the serial
mands assures accurate acquisition of a new signal. Refer to output (only when using an external data clock) will be
Tables Ia and Ib for a summary of CS, R/C, and BUSY states affected whenever R/C goes HIGH. Refer to the Reading
and Figures 2 through 6 and Table II for timing information. Data section and Figures 2, 3, 5, and 6.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when

INPUTS OUTPUTS
CS R/C BYTE CONTC PWRD BUSY D7 D6 D5 D4 D3 D2 D1 D0 COMMENTS
1 X X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
X 0 X X X X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 1 0 X X X D15 D14 D13 D12 D11 D10 D9 D8 Results from last
(MSB) completed conversion.
0 1 1 X X X D7 D6 D5 D4 D3 D2 D1 D0 Results from last
(LSB) completed conversion.
0 1 X X X ↑ ↑↓ ↑↓ ↑↓ ↑↓ ↑↓ ↑↓ ↑↓ ↑↓ Data will change at the
end of a conversion.

TABLE Ia. Read Control for Parallel Data (PAR/SER = 5V.)

D4 D3 D2 D1 D0
CS R/C CONTC PWRD BUSY D7, D6, D5 EXT/INT SYNC DATACLK SDATA TAG

Input Input Input Input Output Output Input Output I/O Output Input COMMENTS
1 X X X 1 Hi-Z LOW LOW Output Hi-Z X
X 0 X X 1 Hi-Z LOW LOW Output Hi-Z X
0 ↓ 0 X 1 HI-Z LOW LOW Output Output X Starts transmission of data from previous
conversion on SDATA synchronized to 16
pulses output on DATACLK.
↓ 0 0 X 1 Hi-Z LOW LOW Output Output X Starts transmission of data from previous
conversion on SDATA synchronized to 16
pulses output on DATACLK.
0 1 0 X X Hi-Z HIGH LOW Input Output Input The level output on SDATA will be the level
input on TAG 16 DATACLK input cycles.
0 1 0 X ↑ Hi-Z HIGH LOW Input Output Input At the end of the conversion, when BUSY
rises, data from the conversion will be shifted
into the output registers. If DATACLK is HIGH,
valid data will be lost.
0 ↑ 0 X 1 Hi-Z HIGH LOW Input Output X Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
↓ 1 0 X 1 Hi-Z HIGH LOW Input Output X Initiates transmission of a HIGH pulse on
SYNC followed by data from last completed
conversion on SDATA synchronized to the
input on DATACLK.
0 0 1 0 ↓ Hi-Z LOW LOW Output Output X Starts transmission of data from previous
conversion on SDATA synchronized to 16
pulses output on DATACLK
↓ 1 X X X Hi-Z HIGH Output Input Output X SDATA becomes active. Inputs on DATACLK
shift out data.
0 ↑ X X X Hi-Z HIGH Output Input Output X SDATA becomes active. Inputs on DATACLK
shift out data.
↓ 0 1 X X Hi-Z LOW LOW Output Output X Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).
0 ↓ 1 X X Hi-Z LOW LOW Output Output X Restarts continuous conversion mode (n – 1 data
transmitted when BUSY is LOW).

TABLE Ib. Read Control for Serial Data (PAR/SER = 0V.)

ADS7825 8
 t1 t1

R/C

t3 t3
t4
BUSY t5

t6 t6
t7 t8

MODE Acquire Convert Acquire Convert

t12 t12
t11
t10
Parallel Previous Previous High Previous Low High Byte Low Byte High Byte
Hi-Z Not Valid Hi-Z
Data Bus High Byte Valid Byte Valid Byte Valid Valid Valid Valid
t2 t9
t9 t12 t12 t12 t12

BYTE

FIGURE 2. Conversion Timing with Parallel Output (CS LOW).

t21 t21 t21 t21 t21 t21

R/C

t1
CS

t3
t4
BUSY

t21 t21 t21 t21

BYTE

DATA
Hi-Z State High Byte Hi-Z State Low Byte Hi-Z State
BUS
t12 t9 t12 t9

FIGURE 3. Using CS to Control Conversion and Read Timing with Parallel Outputs.

t 7 + t8
CS or R/C(1)

t14

t13 1 2 3 15 16 1 2
DATACLK

t16

t15

SDATA MSB Valid Bit 14 Valid Bit 13 Valid Bit 1 Valid LSB Valid MSB Valid Bit 14 Valid
Hi-Z Hi-Z
t25
(Results from previous conversion.)

BUSY
t26

NOTE: (1) If controlling with CS, tie R/C LOW. If controlling with R/C, tie CS LOW.

FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG LOW).

9 ADS7825
 ®
t17

ADS7825
t18 t19
0 1 2 3 4 17 18

EXTERNAL
DATACLK

t1 t22
t20

CS

t21

R/C

t3 t21

10
BUSY
t23
SYNC

t17
t24

SDATA Bit 15 (MSB) Bit 14 Bit 1 Bit 0 (LSB) Tag 0

t27 t28

TAG Tag 0 Tag 1 Tag 2 Tag 15 Tag 16 Tag 17

FIGURE 5. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read After Conversion.
 t17
t18 t19

EXTERNAL
DATACLK

t22

CS

t21
t20

R/C

t1
t11

BUSY

t3 t23

11
SYNC
t17

SDATA Bit 15 (MSB) Bit 0 (LSB) Tag 0

t27 t24 t28

TAG Tag 0 Tag 1 Tag 16 Tag 17

ADS7825
FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT HIGH). Read During Conversion (Previous Conversion Results).

®
READING DATA after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
PARALLEL OUTPUT (pin 24) goes HIGH; this may result in reading invalid data.
To use the parallel output, tie PAR/SER (pin 20) HIGH. The Refer to Table II and Figures 2 and 3 for timing constraints.
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C SERIAL OUTPUT
will tri-state the parallel output. Valid conversion data can be
When PAR/SER (pin 20) is LOW, data can be clocked out
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
serially with the internal data clock or an external data clock.
BYTE (pin 21) is LOW, the 8 most significant bits will be
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
valid with the MSB on D7. When BYTE is HIGH, the 8 least
output and is always active regardless of the state of CS (pin
significant bits will be valid with the LSB on D0. BYTE can
23) and R/C (pin 22). The SDATA output is active when
be toggled to read both bytes within one conversion cycle.
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
Upon initial power up, the parallel output will contain condition. When EXT/INT is HIGH, DATACLK is an input.
indeterminate data. The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
PARALLEL OUTPUT (After a Conversion) the state of EXT/INT, SYNC (pin 13) is an output and always
After conversion ‘n’ is completed and the output registers active, while TAG (pin 17) is always an input.
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13 INTERNAL DATA CLOCK (During A Conversion)
and 15-17). BUSY going HIGH can be used to latch the To use the internal data clock, tie EXT/INT (pin 12) LOW.
data. Refer to Table II and Figures 2 and 3 for timing The combination of R/C (pin 22) and CS (pin 23) LOW will
constraints. initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7825 will output 16
PARALLEL OUTPUT (During a Conversion) bits of valid data, MSB first, from conversion ‘n – 1’ on
After conversion ‘n’ has been initiated, valid data from SDATA (pin 16), synchronized to 16 clock pulses output on
conversion ‘n – 1’ can be read and will be valid up to 12µs

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t1 Convert Pulse Width 0.04 12 µs
t2 Start of Conversion to New Data Valid 20 21 µs
t3 Start of Conversion to BUSY LOW 85 ns
t4 BUSY LOW 20 21 µs
t5 End of Conversion to BUSY HIGH 90 ns
t6 Aperture Delay 40 ns
t7 Conversion Time 20 21 µs
t8 Acquisition Time 4 5 µs
t7 + t8 Throughput Time 25 µs
t9 Bus Relinquish Time 10 83 ns
t10 Data Valid to BUSY HIGH 20 60 ns
t11 Start of Conversion to Previous Data Not Valid 12 20 µs
t12 Bus Access Time and BYTE Delay 83 ns
t13 Start of Conversion to DATACLK Delay 1.4 µs
t14 DATACLK Period 1.1 µs
t15 Data Valid to DATACLK HIGH 20 75 ns
t16 DATACLK LOW to Data Not Valid 400 600 ns
t17 External DATACLK Period 100 ns
t18 External DATACLK HIGH 50 ns
t19 External DATACLK LOW 40 ns
t20 CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock) 25 ns
t21 R/C to CS Setup Time 10 ns
t22 CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock) 25 ns
t23 DATACLK HIGH to SYNC HIGH 15 35 ns
t24 DATACLK HIGH to Valid Data 25 55 ns
t25 Start of Conversion to SDATA Active 83 ns
t26 End of Conversion to SDATA Tri-State 83 ns
t27 CS LOW and R/C HIGH to SDATA Active 83 ns
t28 CS HIGH or R/C LOW to SDATA Tri-State 83 ns
t29 BUSY HIGH to Address Valid 20 ns
t30 Address Valid to BUSY LOW 500 ns

TABLE II. Conversion, Data, and Address Timing. TA = –40°C to +85°C.

®

ADS7825 12
DATACLK (pin 15). The data will be valid on both the The first bit input on TAG will be valid on SDATA on the
rising and falling edges of the internal data clock. The rising 18th falling edge and the 19th rising edge of DATACLK; the
edge of BUSY (pin 24) can be used to latch the data. After second input bit will be valid on the 19th falling edge and the
the 16th clock pulse, DATACLK will remain LOW until the 20th rising edge, etc. With a continuous data clock, TAG
next conversion is initiated, while SDATA will go to what- data will be output on DATA until the internal output
ever logic level was input on TAG (pin 17) during the first registers are updated with the results from the next conver-
clock pulse. The SDATA output will tri-state when BUSY sion. Refer to Table II and Figure 5 for timing information.
returns HIGH. Refer to Table II and Figure 4 for timing
information. EXTERNAL DATA CLOCK (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
EXTERNAL DATA CLOCK conversion ’n-1’ can be read and will be valid up to 12µs
To use an external clock, tie EXT/INT (pin 12) HIGH. The after the start of conversion ‘n’. Do not attempt to clock out
external clock is not a conversion clock; it can only be used data from 12µs after the start of conversion ‘n’ until BUSY
as a data clock. To enable the output mode of the ADS7825, (pin 24) rises; this will result in data loss.
CS (pin 23) must be LOW and R/C (pin 22) must be HIGH. NOTE: For the best possible performance when using an
DATACLK must be HIGH for 20% to 70% of the total data external data clock, data should not be clocked out during a
clock period; the clock rate can be between DC and 10MHz. conversion. The switching noise of the asynchronous data clock
Serial data from conversion ‘n’ can be output on SDATA can cause digital feedthrough degrading the converter’s perfor-
(pin 16) after conversion ‘n’ is completed or during conver- mance. Refer to Table II and Figure 6 for timing information.
sion ‘n + 1’.
An obvious way to simplify control of the converter is to tie TAG FEATURE
CS LOW while using R/C to initiate conversions. While this
TAG (pin 17) inputs serial data synchronized to the external
is perfectly acceptable, there is a possible problem when
or internal data clock.
using an external data clock. At an indeterminate point from
12µs after the start of conversion ‘n’ until BUSY rises, the When using an external data clock, the serial bit stream input
internal logic will shift the results of conversion ‘n’ into the on TAG will follow the LSB output on SDATA (pin 16)
output register. If CS is LOW, R/C is HIGH and the external until the internal output register is updated with new conver-
clock is HIGH at this point, data will be lost. So, with CS sion results. See Table II and Figures 5 and 6.
LOW, either R/C and/or DATACLK must be LOW during The logic level input on TAG for the first rising edge of the
this period to avoid losing valid data. internal data clock will be valid on SDATA after all 16 bits
of valid data have been output.
EXTERNAL DATA CLOCK (After a Conversion)
After conversion ‘n’ is completed and the output registers MULTIPLEXER TIMING
have been updated, BUSY (pin 24) will go HIGH. With CS The four channel input multiplexer may be addressed manu-
LOW (pin 23) and R/C HIGH (pin 22), valid data from ally or placed in a continuous conversion mode where all
conversion ‘n’ will be output on SDATA (pin 16) synchro- four channels are sequentially addressed.
nized to the external data clock input on DATACLK (pin
15). Between 15 and 35ns following the rising edge of the CONTINUOUS CONVERSION MODE (CONTC = 5V)
first external data clock, the SYNC output pin will go HIGH
To place the ADS7825 in the continuous conversion mode,
for one full data clock period (100ns minimum). The MSB
CONTC (pin 25) must be tied HIGH. In this mode, acquisi-
will be valid between 25 and 55ns after the rising edge of the
tion and conversions will take place continually, cycling
second data clock. The LSB will be valid on the 17th falling
through all four channels as long as CS, R/C and PWRD are
edge and the 18th rising edge of the data clock. TAG (pin
LOW (See Table III). Whichever address was last loaded
17) will input a bit of data for every external clock pulse.

CONTC CS R/C BUSY PWRD A0 and A1 OPERATION

0 X X X X Inputs Initiating conversion n latches in the levels input on A0 and A1 to select the channel for
conversion 'n + 1'.
0 X X 0 0 Inputs Conversion in process. New convert commands ignored.
0 0 ↓ 1 0 Inputs Initiates conversion on channel selected at start of previous conversion.
0 ↓ 0 1 0 Inputs Initiates conversion on channel selected at start of previous conversion.
0 X X X 1 Inputs All analog functions powered down. Conversions in process or initiated will yield
meaningless data.
1 X X X X Outputs The end of conversion 'n' (when BUSY rises) increments the internal channel latches and
outputs the channel address for conversion 'n + 1' on A0 and A1.
1 X X 0 0 Outputs Conversion in process.
1 0 ↓ 1 0 Outputs Restarts continuous conversion process on next input channel.
1 ↓ 0 1 0 Outputs Restarts continuous conversion process on next input channel.
1 X X X 1 Outputs All analog functions powered down. Conversions in process or initiated will yield
meaningless data. Resets selected input channel for next conversion to AIN0.

TABLE III. Conversion Control.

®

13 ADS7825
into the A0 and A1 registers (pins 19 and 18, respectively) conversions will proceed through each higher channel, cy-
prior to CONTC being raised HIGH, becomes the first cling back to zero after Channel 3.
address in the sequential continuous conversion mode (e.g., If PWRD is held HIGH for a significant period of time, the
if Channel 1 was the last address selected then Channel 2 REF (pin 7) bypass capacitor may discharge (if the internal
will follow, then Channel 3, and so on). The A0 and A1 reference is being utilized) and the CAP (pin 6) bypass
address inputs become outputs when the device is in this capacitor will discharge (for both internal and external
mode. When BUSY rises at the end of a conversion, A0 and references). The continuous conversion mode should not be
A1 will output the address of the channel that will be enabled until the bypass capacitor(s) have recharged and
converted when BUSY goes LOW at the beginning of the stabilized (1ms for 2.2µF capacitors recommended). In
next conversion. Data will be valid for the previous channel addition, the continuous conversion mode should not be
when BUSY rises. See Table IVa and Figure 7 for channel enabled even with a short pulse on PWRD until the mini-
selection timing in continuous conversion mode. mum acquisition time has been met.
PWRD (pin 26) can be used to reset the multiplexer address
to zero. With the ADS7825 configured for no conversion, MANUAL CHANNEL SELECTION (CONTC= 0V)
PWRD can be taken HIGH for a minimum of 200ns. When
The channels of the ADS7825 can be selected manually by
PWRD returns LOW, the multiplexer address will be reset
using the A0 and A1 address pins (pins 19 and 18, respec-
to zero. When the continuous conversion mode is enabled,
tively). See Table IVb for the multiplexer truth table and
the first conversion will be done on channel 0. Subsequent
Figure 8 for channel selection timing.

ADS7825 TIMING AND CONTROL

DATA AVAILABLE CHANNEL TO BE OR
A1 A0 FROM CHANNEL BEING CONVERTED DESCRIPTION OF OPERATION
0 0 AIN3 AIN0
Channel being acquired or converted is output on these
0 1 AIN0 AIN1
address lines. Data is valid for the previous channel. These
1 0 AIN1 AIN2
lines are updated when BUSY rises.
1 1 AIN2 AIN3

TABLE IVa. A0 and A1 Outputs (CONTC HIGH).

CHANNEL SELECTED
A1 A0 WHEN BUSY GOES HIGH DESCRIPTION OF OPERATION
0 0 AIN0 Channel to be converted during conversion 'n + 1' is latched
0 1 AIN1 when conversion 'n' is initiated (BUSY goes LOW). The selected
1 0 AIN2 input starts being acquired as soon as conversion 'n' is done
1 1 AIN3 (BUSY goes HIGH).

TABLE IVb. A0 and A1 Inputs (CONTC LOW).

Conversion Currently in Progress:

BUSY n–2 n–1 n n+1 n+2 n+3 n+4

Channel Address for Conversion:

A0, A1 n–2 n–1 n n+1 n+2 n+3 n+4 n+5
(Output)
t29
Results from Conversion:
D7-D0 n–3 n–2 n–1 n n+1 n+2 n+3 n+4

FIGURE 7. Channel Addressing in Continuous Conversion Mode (CONTC HIGH, CS and R/C LOW).

R/C

Conversion Currently in Progress:

BUSY n–2 n–1 n n+1 n+2 n+3 n+4

Channel Address for Conversion:

A0, A1 n–1 n n+1 n+2 n+3 n+4 n+5
(Input)
t30
Results from Conversion:
D7-D0 n–3 n–2 n–1 n n+1 n+2 n+3 n+4

FIGURE 8. Channel Addressing in Normal Conversion Mode (CONTC and CS LOW).

®

ADS7825 14
CALIBRATION CDAC. Capacitor values larger than 2.2µF will have little
The ADS7825 has no internal provision for correcting the affect on improving performance.
individual bipolar zero error or full-scale error for each The output of the buffer is capable of driving up to 1mA of
individual channel. Instead, the bipolar zero error of each current to a DC load. Using an external buffer will allow the
channel is guaranteed to be below a level which is quite internal reference to be used for larger DC loads and AC
small for a 16-bit converter with a ±10V input range (slightly loads. Do not attempt to directly drive an AC load with the
more than ±32 LSBs). In addition, the channel errors should output voltage on CAP. This will cause performance degra-
match each other to within 16 LSBs. dation of the converter.
For the full-scale error, the circuit of Figure 9 can be used.
This will allow the reference to be adjusted such that the PWRD
full-scale error for any single channel can be set to zero. PWRD (pin 26) HIGH will power down all of the analog
Again, the close matching of the channels will ensure that circuitry including the reference. Data from the previous
the full-scale errors on the other channels will be small. conversion will be maintained in the internal registers and
can still be read. With PWRD HIGH, a convert command
yields meaningless data. When PWRD is returned LOW,
AIN2 adequate time must be provided in order for the capacitors
on REF (pin 7) and CAP (pin 6) to recharge. For 2.2µF
AIN3 capacitors, a minimum recharge/settling time of 1ms is
recommended before the conversion results should be con-
CAP
sidered valid.
+5V R1 +
2.2µF
1MΩ
P1
50kΩ +
REF LAYOUT
2.2µF
POWER
AGND2
The ADS7825 uses 90% of its power for the analog cir-
cuitry, and the converter should be considered an analog
FIGURE 9. Full Scale Trim. component. For optimum performance, tie both power pins
to the same +5V power supply and tie the analog and digital
grounds together.
REFERENCE The +5V power for the converter should be separate from
the +5V used for the system’s digital logic. Connecting VS1
The ADS7825 can operate with its internal 2.5V reference or
and VS2 (pins 28 and 27) directly to a digital supply can
an external reference. By applying an external reference to
reduce converter performance due to switching noise from
pin 7, the internal reference can be bypassed.
the digital logic. For best performance, the +5V supply can
be produced from whatever analog supply is used for the rest
REF of the analog signal conditioning. If +12V or +15V supplies
REF (pin 7) is an input for an external reference or the output are present, a simple +5V regulator can be used. Although it
for the internal 2.5V reference. A 2.2µF capacitor should be is not suggested, if the digital supply must be used to power
connected as close to the REF pin as possible. This capacitor the converter, be sure to properly filter the supply. Either
and the output resistance of REF create a low pass filter to using a filtered digital supply or a regulated analog supply,
bandlimit noise on the reference. Using a smaller value both VS1 and VS2 should be tied to the same +5V source.
capacitor will introduce more noise to the reference degrad-
ing the SNR and SINAD. The REF pin should not be used GROUNDING
to drive external AC or DC loads.
Three ground pins are present on the ADS7825. DGND is
The range for the external reference is 2.3V to 2.7V and the digital supply ground. AGND2 is the analog supply
determines the actual LSB size. Increasing the reference ground. AGND1 is the ground which all analog signals
voltage will increase the full scale range and the LSB size of internal to the A/D are referenced. AGND1 is more suscep-
the converter which can improve the SNR. tible to current induced voltage drops and must have the path
of least resistance back to the power supply.
CAP All the ground pins of the A/D should be tied to an analog
CAP (pin 6) is the output of the internal reference buffer. A ground plane, separated from the system’s digital logic
2.2µF capacitor should be placed as close to the CAP pin as ground, to achieve optimum performance. Both analog and
possible to provide optimum switching currents for the digital ground planes should be tied to the ‘system’ ground
CDAC throughout the conversion cycle. This capacitor also as near to the power supplies as possible. This helps to
provides compensation for the output of the buffer. Using a prevent dynamic digital ground currents from modulating
capacitor any smaller than 1µF can cause the output buffer the analog ground through a common impedance to power
to oscillate and may not have sufficient charge for the ground.

15 ADS7825
CROSSTALK SIGNAL CONDITIONING
The worst-case channel-to-channel crosstalk versus input The FET switches used for the sample hold on many CMOS
frequency is shown in the Typical Performance Curves A/D converters release a significant amount of charge injec-
section of this data sheet. With a full-scale 1kHz input tion which can cause the driving op amp to oscillate. The
signal, worst case crosstalk on the ADS7825 is better than amount of charge injection due to the sampling FET switch
–115dB. This should be adequate for even the most de- on the ADS7825 is approximately 5-10% of the amount on
manding applications. However, if crosstalk is a concern, similar ADCs with the charge redistribution DAC (CDAC)
the following items should be kept in mind: The worst case architecture. There is also a resistive front end which attenu-
crosstalk is generally from channel 3 to 2. In addition, ates any charge which is released. The end result is a
crosstalk from Channel 3 to any other channel is worse than minimal requirement for the drive capability on the signal
from those channels to Channel 3. The reason for this is that conditioning preceding the A/D. Any op amp sufficient for
Channel 3 is nearer to the reference on the ADS7825. This the signal in an application will be sufficient to drive the
allows two coupling modes: channel-to-channel and Chan- ADS7825.
nel 3 to the reference. In general, when crosstalk is a The resistive front end of the ADS7825 also provides a
concern, avoid placing signals with higher frequency com- guaranteed ±15V overvoltage protection. In most cases, this
ponents on Channel 3. eliminates the need for external overvoltage protection
The worst case crosstalk occurs from Channel 3 to Channel circuitry.
2 as shown in the Crosstalk vs Input Frequency graph in the
Typical Performance Curves section. Other adjacent chan- INTERMEDIATE LATCHES
nels are typically several dB better than this while non-
The ADS7825 does have tri-state outputs for the parallel
adjacent channels are typically 10dB better. If a particular
port, but intermediate latches should be used if the bus will
channel should be as immune as possible from crosstalk,
be active during conversions. If the bus is not active during
channel 0 would be the best channel for the signal and
conversions, the tri-state outputs can be used to isolate the
channel 1 should have the signal with the lowest frequency
A/D from other peripherals on the same bus.
content. If two signals are to have as little crosstalk as
possible, they should be placed on Channel 0 and Channel Intermediate latches are beneficial on any monolithic A/D
2 with lower frequency, less-sensitive inputs on the other converter. The ADS7825 has an internal LSB size of 38µV.
channels. Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
If crosstalk is a concern for all channels, keep in mind that the
substrate to the analog circuitry causing degradation of
crosstalk graph shows crosstalk between any two channels.
converter performance.
Total crosstalk to any given channel is the sum of the
crosstalk contributions from all the other channels. Since non- For an ADS7825 with proper layout, grounding, and bypass-
adjacent channels contribute very little, their contribution can ing, the effect can be a few LSBs of error. In some cases, this
generally be ignored. A good approximation for absolute error can be treated as an increase in converter noise and
worst case crosstalk would be to add 6dB to the highest curve simply averaged out. In others, the error may not be random
shown in the Crosstalk vs Input Frequency graph. and will produce an error in the conversion result, even with
averaging. Poor grounding, poor bypassing, and high-speed
digital signals will increase the magnitude of the errors—
possibly to many tens of LSBs.

ADS7825 16