Buf634 - 250-Ma High-Speed Buffer

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BUF634
SBOS030B – SEPTEMBER 2000 – REVISED MARCH 2019
BUF634 250-mA High-Speed Buffer

A newer version of this device is now available: BUF634A
1 Features 3 Description
1• A newer version of this device is now available: The BUF634 is a high speed, unity-gain open-loop
BUF634A buffer recommended for a wide range of applications.
The BUF634 can be used inside the feedback loop of
• High output current: 250 mA op amps to increase output current, eliminate thermal
• Slew rate: 2000 V/µs feedback, and improve capacitive load drive.
• Pin-selected bandwidth: 30 MHz to 180 MHz For low power applications, the BUF634 operates on
• Low quiescent current: 1.5 mA (30 MHz BW) 1.5-mA quiescent current with 250-mA output,
• Wide supply range: ±2.25 to ±18 V 2000-V/µs slew rate, and 30-MHz bandwidth.
Bandwidth can be adjusted from 30 MHz to 180 MHz
• Internal current limit by connecting a resistor between V– and the BW Pin.
• Thermal shutdown protection
Output circuitry is fully protected by internal current
• 8-pin PDIP, SOIC-8, 5-lead TO-220, 5-lead limit and thermal shut-down, making the device
DDPAK-TO-263 surface-mount rugged and easy to use.
2 Applications The BUF634 is available in a variety of packages to

suit mechanical and power dissipation requirements.
• Valve driver Types include 8-pin PDIP, SOIC-8 surface-mount, 5-
• Solenoid driver lead TO-220, and a 5-lead DDPAK-TO-263 surface-
• Op amp current booster mount plastic power package.
• Line driver The upgraded device, BUF634A offers a wider
• Headphone driver bandwidth (210 MHz) and a higher slew rate
(3750 V/µs) at 40% lower quiescent current. See the
• Video driver Device Comparison Table for a selection of unity-
• Motor driver gain, open-loop buffers from Texas Instruments.
• Test equipment
Device Information(1)
• ATE pin driver
PART
PACKAGE BODY SIZE (NOM)
NUMBER
SOIC (8) 3.91 mm × 4.90 mm
PDIP (8) 6.35 mm × 9.81 mm
BUF634
TO-220 (5) 8.51 mm × 10.16 mm
DDPAK/TO-263 (5) 8.42 mm × 10.16 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Boost the Output Current of any Operational Amplifier
1 2
OPA2810
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
BUF634
SBOS030B – SEPTEMBER 2000 – REVISED MARCH 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 1 9 Application and Implementation ........................ 12
3 Description ............................................................. 1 9.1 Application Information............................................ 12
4 Revision History..................................................... 2 9.2 Typical Application ................................................. 14
5 Device Comparison Table..................................... 3 10 Power Supply Recommendations ..................... 15
6 Pin Configuration and Functions ......................... 3 11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
7 Specifications......................................................... 4
11.2 Layout Example .................................................... 17
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings ............................................................ 4 12 Device and Documentation Support ................. 18
7.3 Recommended Operating Conditions....................... 4 12.1 Device Support .................................................... 18
7.4 Thermal Information .................................................. 4 12.2 Documentation Support ....................................... 18
7.5 Electrical Characteristics........................................... 5 12.3 Receiving Notification of Documentation Updates 18
7.6 Typical Characteristics .............................................. 7 12.4 Community Resources.......................................... 18
12.5 Trademarks ........................................................... 19
8 Detailed Description ............................................ 10
12.6 Electrostatic Discharge Caution ............................ 19
8.1 Overview ................................................................. 10
12.7 Glossary ................................................................ 19
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (November 2015) to Revision B Page
• Added discussion of BUF634A upgrade device to Features and Description sections ......................................................... 1
• Changed amplifier to OPA2810 and deleted table from Boost the Output Current of any Operational Amplifier figure........ 1
• Added Device Comparison Table .......................................................................................................................................... 3
Changes from Original (September 2000) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
2 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated
Product Folder Links: BUF634

BUF634
www.ti.com SBOS030B – SEPTEMBER 2000 – REVISED MARCH 2019
5 Device Comparison Table
IQ/CHANNEL SLEW RATE VOLTAGE NOISE

DEVICE VS± (V) BW (MHz) AMPLIFIER DESCRIPTION
(mA) (V/µs) (nV/√Hz)
BUF634A ±18 1.5 – 8.5 35 – 210 3750 3.4 Unity-gain, open-loop buffer
BUF634 ±18 1.5 – 15 30 – 180 2000 4 Unity-gain, open-loop buffer
Unity-gain, open-loop buffer with
LMH6321 ±18 11 110 1800 2.8
adjustable current limit
6 Pin Configuration and Functions
P and D Packages KC Package

8-Pin PDIP and SOIC 5-Pin TO-220
Top View Top View
BW 1 8 NC
NC 2 7 V+
VIN 3 G=1 6 VO
G=1
V– 4 5 NC
1 2 3 4 5
BW V– V+
VIN VO
KTT Package
5-Pin DDPAK/TO-263
Top View
G=1
1 2 3 4 5
BW V– V+
VIN VO
Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
8 PINS 5 PINS
BW 1 1 I Bandwidth adjust pin
NC 2, 5, 8 — – No internal connection
V+ 7 5 I Positive power supply
VIN 3 2 I Input
VO 6 4 O Output
V– 4 3 I Negative power supply
Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

BUF634
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage ±18 V
Input voltage ±VS
Output short-circuit (to ground) Continuous
Operating temperature –40 125 °C
Junction temperature 150 °C
Lead temperature (soldering, 10 s) 300 °C
Storage temperature, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings

VALUE UNIT
BUF634F in PDIP and SOIC Packages
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 V
BUF634F in SOIC-8 Package Only
V(ESD) Electrostatic discharge, Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000 V
BUF634F in TO-220 and DDPAK Packages
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
±2.25 ±15 ±18
Vs = (V+) - (V-) Supply voltage V
(4.5) (30) (36)
TA Operating temperature -40 +25 +85 °C
7.4 Thermal Information

BUF634
THERMAL METRIC (1) PDIP SOIC TO-220 DDPAK-TO-263 UNIT
8 PINS 8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 46.5 103.4 32.1 41.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.8 44.2 25.6 45 °C/W
RθJB Junction-to-board thermal resistance 23.8 44.5 18.3 24.8 °C/W
ψJT Junction-to-top characterization parameter 12 5.4 8.5 13.1 °C/W
ψJB Junction-to-board characterization parameter 23.6 43.8 17.7 23.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a 0.7 2.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

BUF634
7.5 Electrical Characteristics

at TA = +25°C (1), VS = ±15 V, specifications are for both low quiescent-current mode and wide-bandwidth mode (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Offset Voltage ±30 ±100 mV
Offset Voltage vs Temperature Specified Temperature Range ±100 µV/°C
Offset Voltage vs Power Supply VS = ±2.25 V (2) to ±18 V 0.1 1 mV/V
Low Quiescent
±0.5 ±2
Current Mode
Input Bias Current VIN = 0V µA
Wide Bandwidth
±5 ±20
Mode
Low Quiescent
80 || 8
Current Mode
Input Impedance RL = 100 Ω MΩ || pF
Wide Bandwidth
8 || 8
Mode
Noise Voltage f = 10 kHz 4 nV/√Hz
GAIN
RL = 1 kΩ, VO = ±10 V 0.95 0.99
Gain RL = 100 Ω, VO = ±10 V 0.85 0.93 V/V
RL = 67 Ω, VO = ±10 V 0.8 0.9
OUTPUT
Current Output, Continuous ±250 mA
Positive IO = 10 mA (V+) –2.1 (V+) –1.7
Negative IO = –10 mA (V–) +2.1 (V–) +1.8
Positive IO = 100 mA (V+) –3 (V+) –2.4
Voltage Output V
Negative IO = –100 mA (V–) +4 (V–) +3.5
Positive IO = 150 mA (V+) –4 (V+) –2.8
Negative IO = –150 mA (V–) +5 (V–) +4
Low Quiescent Current Mode ±350 ±550
Short-Circuit Current mA
Wide Bandwidth Mode ±400 ±550
DYNAMIC RESPONSE
Low Quiescent
30
Current Mode
RL = 1 kΩ
Wide Bandwidth
180
Mode
Bandwidth, –3dB MHz
Low Quiescent
20
Current Mode
RL = 100 Ω
Low Quiescent
160
Current Mode
Slew Rate 20 Vp-p, RL = 100 Ω 2000 V/µs
0.1% 200
Settling Time 20-V Step, RL = 100 Ω ns
1% 50
Low Quiescent
4%
3.58 MHz, VO = 0.7 V, Current Mode
Differential Gain
RL = 150 Ω Wide Bandwidth
0.4%
Mode
Low Quiescent
2.5
3.58 MHz, VO = 0.7 V, Current Mode
Differential Phase °
RL = 150 Ω Wide Bandwidth
0.1
Mode
(1) Tests are performed on high speed automatic test equipment, at approximately 25°C junction temperature. The power dissipation of this
product will cause some parameters to shift when warmed up. SeeTypical Characteristics for over-temperature performance.
(2) Limited output swing available at low supply voltage. See Output voltage specifications.

BUF634
Electrical Characteristics (continued)

at TA = +25°C(1), VS = ±15 V, specifications are for both low quiescent-current mode and wide-bandwidth mode (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
Specified Operating Voltage ±15 V
Operating Voltage Range ±2.25 (2) ±18 V
Low Quiescent
±1.5 ±2
Current Mode
IQ Quiescent Current IO = 0 mA
Wide Bandwidth
±15 ±20
Mode
TEMPERATURE RANGE
Specification –40 85 °C
Operating –40 125 °C
TJ Thermal Shutdown Temperature 175 °C

BUF634
7.6 Typical Characteristics

at TA = 25°C, VS = ±15 V (unless otherwise noted)
10 10
RL = 100Ω RL = 100Ω
RS = 50Ω 5 RS = 50Ω 5
Gain (dB)
VO = 10mV 0 VO = 10mV
Gain (dB)
0
Low IQ Wide BW
–5 –5
–10 –10
0 –15 0 Wide BW –15
–10 IQ = 15mA –10
Phase (°)
Phase (°)
–20 IQ = 9mA –20
IQ = 4mA TJ = –40°C
–30 –30 Low IQ
IQ = 2.5mA TJ = 25°C
–40 IQ = 1.5mA –40 TJ = 125°C
–50 –50
1M 10M 100M 1G 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Figure 1. Gain and Phase vs Frequency vs Quiescent Figure 2. Gain and Phase vs Frequency vs Temperature
Current
10 10
RL = 100Ω RS = 50Ω
VO = 10mV 5 VO = 10mV 5
Gain (dB)
Gain (dB)
0 0
Wide BW Wide BW
Low IQ –5 –5
Low IQ
–10 –10
0 –15 0 –15
–10 Wide BW –10
Wide BW
Phase (°)
Phase (°)
–20 –20
RS = 0Ω RL = 1kΩ
–30 Low IQ RS = 50Ω –30 Low IQ RL = 100Ω
–40 RS = 100Ω –40 RL = 50Ω
–50 –50
1M 10M 100M 1G 1M 10M 100M 1G
Figure 3. Gain and Phase vs Frequency vs Source Figure 4. Gain and Phase vs Frequency vs Load Resistance
Resistance
10 10
Low IQ Mode RL = 100Ω RL = 100Ω
RS = 50Ω 5 RS = 50Ω 5
Gain (dB)
Gain (dB)
VO = 10mV 0 VO = 10mV 0
–5 –5
Wide BW Mode
–10 –10
0 –15 0 –15
–10 –10
CL = 0pF CL = 0
Phase (°)
Phase (°)
–20 CL = 50pF –20 CL = 50pF

–30 CL = 200pF –30 CL = 200pF
CL = 1nF CL = 1nF
–40 –40
–50 –50
1M 10M 100M 1G 1M 10M 100M 1G
Figure 5. Gain and Phase vs Frequency vs Load Figure 6. Gain and Phase vs Frequency vs Load
Capacitance Capacitance

BUF634
Typical Characteristics (continued)

10 100
RL = 100Ω
RS = 50Ω 5 90
Gain (dB)
Power Supply Rejection (dB)

VO = 10mV 0 80
Wide BW Wide BW
Low IQ –5 70
–10 60
0 –15 50
–10 40
Wide BW
Phase (°)
VS = ±18V Low IQ
–20 30
Low IQ VS = ±12V
–30 VS = ±5V 20
–40 VS = ±2.25V 10
–50 0
1M 10M 100M 1G 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)
Figure 7. Gain and Phase vs Frequency vs Power Supply Figure 8. Power Supply Rejection vs Frequency
Voltage
20 500
+15V
18
450
16
15mA at R = 0
Quiescent Current (mA)
Limit Current (mA)

14 BW 400 Wide Bandwidth Mode
12 R
10 350
8 –15V Low IQ Mode
300
6
4
250
2 1.5mA at R = ∞
0 200
10 100 1k 10k –50 –25 0 25 50 75 100 125 150
Resistance (Ω) Junction Temperature (°C)
Figure 9. Quiescent Current vs Bandwidth Control Figure 10. Short-Circuit Current vs Temperature
Resistance
7 20
Cooling
6
Low IQ Mode
15 Thermal Shutdown
5
4
»10°C 10
3 »10°C
Wide BW Mode
2
5
1 Cooling
Thermal Shutdown
0 0
–50 –25 0 25 50 75 100 125 150 175 200 –50 –25 0 25 50 75 100 125 150 175 200
Junction Temperature (°C) Junction Temperature (°C)
Figure 11. Quiescent Current vs Temperature Figure 12. Quiescent Current vs Temperature

BUF634
Typical Characteristics (continued)

13 13
VIN = 13V VIN = 13V
12 12
Output Voltage Swing (V)

Output Voltage Swing (V)
11 11
10 VS = ±15V 10 VS = ±15V
–10 Low IQ Mode –10 Wide BW Mode
–11 –11
TJ = –40°C TJ = –40°C
–12 TJ = 25°C –12 TJ = 25°C
VIN = –13V TJ = 125°C VIN = –13V TJ = 125°C
–13 –13
0 50 100 150 200 250 300 0 50 100 150 200 250 300
|Output Current| (mA) |Output Current| (mA)
Figure 13. Output Voltage Swing vs Output Current Figure 14. Output Voltage Swing vs Output Current
3 12
TO-220 and DDPAK
Infinite Heat Sink
10 ΘJC = 6°C/W
Power Dissipation (W)

Power Dissipation (W)
2 TO-220 and DDPAK 8

8-Pin DIP Free Air
ΘJA = 100°C/W ΘJA = 65°C/W 6
TO-220 and DDPAK
Free Air
1 4 ΘJA = 65°C/W
SO-8 2
ΘJA = 150°C/W
0 0
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Ambient Temperature (°C) Ambient Temperature (°C)
Figure 15. Maximum Power Dissipation vs Temperature Figure 16. Maximum Power Dissipation vs Temperature
Input 100mV/div Input 100mV/div
Wide BW Wide BW
Mode Mode
Low IQ Low IQ
Mode Mode
20ns/div 20ns/div
RS = 50 Ω, RL = 100 Ω RS = 50 Ω, RL = 100 Ω
Figure 17. Small-Signal Response Figure 18. Large-Signal Response

BUF634
8 Detailed Description
8.1 Overview
The BUF634 device is a high speed, unity-gain open-loop buffer recommended for a wide range of applications.
The BUF634 device can be used inside the feedback loop of op amps to increase output current, eliminate
thermal feedback, and improve capacitive load drive.
For low power applications, the BUF634 device operates on 1.5-mA quiescent current with 250-mA output,
2000-V/µs slew rate, and 30-MHz bandwidth. Bandwidth can be adjusted from 30 MHz to 180 MHz by
connecting a resistor between V– and the BW Pin refer to Figure 9 and Figure 1. Output circuitry is fully
protected by internal current limit and thermal shut-down, making it rugged and easy to use.
See the Functional Block Diagram section for a simplified circuit diagram of the BUF634 showing its open-loop
complementary follower design.
8.2 Functional Block Diagram
V+
Thermal
Shutdown
VIN 200Ω VO
I1(1)
150Ω
4kΩ
BW V–
Signal path indicated in bold.

Note: (1) Stage currents are set by I1.

BUF634
8.3 Feature Description

8.3.1 Output Current
The BUF634 device can deliver up to ±250-mA continuous output current. Internal circuitry limits output current
to approximately ±350 mA; see Figure 10. For many applications, however, the continuous output current will be
limited by thermal effects.
The output voltage swing capability varies with junction temperature and output current (see Figure 14). Although
all four package types are tested for the same output performance using a high speed test, the higher junction
temperatures with the DIP and SO-8 package types often provide less output voltage swing. Junction
temperature is reduced in the DDPAK surface-mount power package because it is soldered directly to the circuit
board. The TO-220 package used with a good heat sink further reduces junction temperature, allowing maximum
possible output swing.
8.4 Device Functional Modes

The BUF634 is operational when the power-supply voltage is greater than 4.5 V (±2.25 V). The maximum power
supply voltage for the BUF634 is 36 V (±18 V). At low power supply conditions, such as ±2.25 V, the output
swing may be limited. Refer to Electrical Characteristics for additional information.

BUF634
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

Figure 19 shows the BUF634 device connected as an open-loop buffer. The source impedance and optional
input resistor, RS, influence frequency response: see Typical Characteristics. Power supplies should be bypassed
with capacitors connected close to the device pins. Capacitor values as low as 0.1 µF assure stable operation in
most applications, but high output current and fast output slewing can demand large current transients from the
power supplies. Solid tantalum 10-µF capacitors are recommended. High frequency open-loop applications may
benefit from special bypassing and layout considerations. See High Frequency Applications for more information.
V+
10µF
DIP/SO-8
Pinout shown
7
VIN RS
3 6
BUF634 VO
1 RL
4
10µF
Optional connection for
wide bandwidth — see text.
V–
Figure 19. Buffer Connections
9.1.1 High Frequency Applications

The excellent bandwidth and fast slew rate of the BUF634 device are useful in a variety of high frequency open-
loop applications. When operated open-loop, printed-circuit-board layout and bypassing technique can affect
dynamic performance.
For best results, use a ground plane-type circuit board layout and bypass the power supplies with 0.1-µF ceramic
chip capacitors at the device pins in parallel with solid tantalum 10-µF capacitors. Source resistance affects high-
frequency peaking, step-response overshoot and ringing. Best response is usually achieved with a series input
resistor of 25 Ω to 200 Ω, depending on the signal source. Response with some loads (especially capacitive) can
be improved with a resistor of 10 Ω to 150 Ω in series with the output.
Figure 20. High Performance Headphone Driver

BUF634
Application Information (continued)
+24V C(1) +
10kΩ 12V
–
+ pseudo
10µF BUF634 ground
C(1) +
10kΩ 12V
–
NOTE: (1) System bypass capacitors.
Figure 21. Pseudo-Ground Driver
VIN IO = ±200mA
±2V
OPA177 BUF634
Valve
10Ω
Figure 22. Current-Output Valve Driver
10kΩ
1kΩ 9kΩ 10kΩ
1/2 1/2
OPA2234 BUF634 Motor BUF634 OPA2234
VIN
±1V
±20V
at 250mA
Figure 23. Bridge-Connected Motor Driver

BUF634
9.2 Typical Application

9.2.1 Boosting Op Amp Output Current
The BUF634 device can be connected inside the feedback loop of most op amps to increase output current (see
Figure 24). When connected inside the feedback loop, the offset voltage of the BUF634 device and other errors
are corrected by the feedback of the op amp.
V+
OP AMP RECOMMENDATIONS
OPA177, OPA1013 Use Low I Q mode. G = 1 stable.
OPA111, OPA2111
C1(1) OPA121, OPA234 (1),
OPA130 (1)
VO
OPA BUF634 OPA27, OPA2107 Low I Q mode is stable. Increasing CL may cause
VIN
BW OPA602, OPA131 (1) excessive ringing or instability. Use Wide BW mode.
OPA627, OPA132 (1) Use Wide BW mode, C1 = 200pF. G = 1 stable.
NOTE: (1) C1 not required OPA637, OPA37 Use Wide BW mode. These op amps are not G = 1
Wide BW mode
for most common op amps. stable. Use in G > 4.
(if required)
Use with unity-gain stable V– NOTE: (1) Single, dual, and quad versions.
high speed op amps.
Figure 24. Boosting Op Amp Output Current
9.2.1.1 Design Requirements

• Boost the output current of an OPA627
• Operate from ±15V power supplies
• Operate from -40°C to +85°C
• Gain = 23.5 V/V
• Output current = ±250 mA
• Bandwidth greater than 100 kHz
9.2.1.2 Detailed Design Procedure

To assure that the composite amplifier remains stable, the phase shift of the BUF634 device must remain small
throughout the loop gain of the circuit. For a G=+1 op amp circuit, the BUF634 device must contribute little
additional phase shift (approximately 20° or less) at the unity-gain frequency of the op amp. Phase shift is
affected by various operating conditions that may affect stability of the op amp; see Typical Characteristics.
Most general-purpose or precision op amps remain unity-gain stable with the BUF634 device connected inside
the feedback loop as shown. Large capacitive loads may require the BUF634 device to be connected for wide
bandwidth for stable operation. High speed or fast-settling op amps generally require the wide bandwidth mode
to remain stable and to assure good dynamic performance. To check for stability with an op amp, look for
oscillations or excessive ringing on signal pulses with the intended load, and worst-case conditions that affect
phase response of the buffer. Connect the circuit as shown in Figure 24. Choose resistors to provide a voltage
gain of 23.5 V/V. Select the feedback resistor to be 2.7 kΩ. Choose the input resistor to be 120 Ω.

BUF634
Typical Application (continued)

9.2.1.3 Application Curve
40
Gain (db)
20
0
100 1k 10k 100k 1M
Frequency (Hz)
Figure 25. Frequency Response of Composite Amplifier
10 Power Supply Recommendations

The BUF634 is specified for operation from 4.5V to 36 V (±2.25 V to ±18 V). Many specifications apply from
–40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.
11 Layout
11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit. Bypass capacitors are
used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. For more detailed
information refer to Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 27
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

BUF634
Layout Guidelines (continued)

Power dissipated in the BUF634 device causes the junction temperature to rise. A thermal protection circuit in
the BUF634 device disables the output when the junction temperature reaches approximately 175°C. When the
thermal protection is activated, the output stage is disabled, allowing the device to cool. Quiescent current is
approximately 6 mA during thermal shutdown. When the junction temperature cools to approximately 165°C, the
output circuitry is again enabled. This can cause the protection circuit to cycle on and off with a period ranging
from a fraction of a second to several minutes or more, depending on package type, signal, load and thermal
environment.
The thermal protection circuit is designed to prevent damage during abnormal conditions. Any tendency to
activate the thermal protection circuit during normal operation is a sign of an inadequate heat sink or excessive
power dissipation for the package type.
The TO-220 package provides the best thermal performance. When the TO-220 is used with a properly sized
heat sink, output is not limited by thermal performance. See Application Bulletin AB-037 for details on heat sink
calculations. The DDPAK also has excellent thermal characteristics. Its mounting tab should be soldered to a
circuit board copper area for good heat dissipation. Figure 26 shows typical thermal resistance from junction to
ambient as a function of the copper area. The mounting tab of the TO-220 and DDPAK packages is electrically-
connected to the V– power supply.
The DIP and SO-8 surface-mount packages are excellent for applications requiring high output current with low
average power dissipation. To achieve the best possible thermal performance with the DIP or SO-8 packages,
solder the device directly to a circuit board. Because much of the heat is dissipated by conduction through the
package pins, sockets will degrade thermal performance. Use wide circuit board traces on all the device pins,
including pins that are not connected. With the DIP package, use traces on both sides of the printed circuit board
if possible.
THERMAL RESISTANCE vs
CIRCUIT BOARD COPPER AREA
60 Circuit Board Copper Area
Thermal Resistance, ΘJA (°C/W)
BUF634F
50 Surface Mount Package
1oz copper
40
30
20
BUF634F
10 Surface Mount Package
0 1 2 3 4 5
Copper Area (inches2)
Figure 26. Thermal Resistance vs Circuit Board Copper Area
11.1.1 Power Dissipation

Power dissipation depends on power supply voltage, signal, and load conditions. With DC signals, power
dissipation is equal to the product of output current times the voltage across the conducting output transistor,
VS – VO. Power dissipation can be minimized by using the lowest possible power supply voltage necessary to
assure the required output voltage swing.
For resistive loads, the maximum power dissipation occurs at a DC output voltage of one-half the power supply
voltage. Dissipation with AC signals is lower. Application Bulletin SBOS022 explains how to calculate or measure
power dissipation with unusual signals and loads.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature should be limited to 150°C, maximum. To estimate the
margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered.
The thermal protection should trigger more than 45°C above the maximum expected ambient condition of your
application.

BUF634
11.2 Layout Example
Optional: Use for

wide bandwidth
applications
Place all passive
components close to
the device to reduce
parasitic errors VS+
Run the input trace
as far away from BUF634 SOIC
BW NC 10 µF
the supply lines Package
as possible
NC V+ GND
RS
VIN VIN VO Output
Use low-ESR, ceramic

V± NC
bypass capacitor
10 µF
Use low-ESR, GND

VS±
ceramic bypass Ground (GND) plane on another layer
capacitor
Figure 27. BUF634 Layout Example

BUF634
12 Device and Documentation Support
12.1 Device Support

12.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.2 TI Precision Designs

The BUF634 is featured in several TI Precision Designs, available online at http://www.ti.com/. TI Precision
Designs are analog solutions created by TI’s precision analog applications experts and offer the theory of
operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and measured
performance of many useful circuits.
12.2 Documentation Support

12.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Circuit board layout techniques application report
• Texas Instruments, Combining an amplifier with the BUF634 application note
• Texas Instruments, Add current limit to the BUF634 application note
• Texas Instruments, Power amplifier stress and power handling limitations application note
• Texas Instruments, Shelf-Life Evaluation of Lead-Free Component Finishes application report
12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

BUF634
12.5 Trademarks
E2E is a trademark of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
BUF634F/500 NRND DDPAK/ KTT 5 500 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 BUF634F
TO-263
BUF634F/500E3 NRND DDPAK/ KTT 5 500 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BUF634F
TO-263
BUF634FKTTT NRND DDPAK/ KTT 5 250 RoHS & Green Call TI | SN Level-2-260C-1 YEAR -40 to 125 BUF634F
TO-263
BUF634FKTTTE3 NRND DDPAK/ KTT 5 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 BUF634F
TO-263
BUF634P NRND PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 BUF634P
BUF634PG4 NRND PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 BUF634P
BUF634T NRND TO-220 KC 5 49 RoHS & Green Call TI | SN N / A for Pkg Type -40 to 125 BUF634T
BUF634TG3 NRND TO-220 KC 5 49 RoHS & Green SN N / A for Pkg Type -40 to 125 BUF634T
BUF634U NRND SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 BUF
634U
BUF634U/2K5 NRND SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 BUF
634U
BUF634UE4 NRND SOIC D 8 75 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 BUF
634U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 20-Aug-2021
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
BUF634U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BUF634U/2K5 SOIC D 8 2500 367.0 367.0 35.0
TUBE

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
BUF634P P PDIP 8 50 506 13.97 11230 4.32
BUF634PG4 P PDIP 8 50 506 13.97 11230 4.32
BUF634T KC TO-220 5 49 546 31 11930 3.17
BUF634TG3 KC TO-220 5 49 546 31 11930 3.17
BUF634U D SOIC 8 75 506.6 8 3940 4.32
BUF634UE4 D SOIC 8 75 506.6 8 3940 4.32
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
KC0005A SCALE 0.850
TO-220 - 16.51 mm max height
TO-220
4.83
B
4.06
10.67 1.40 8.89
3.05 A 1.14
9.65 6.86
2.54
6.86
(6.275)
5.69
3.71-3.96 OPTIONAL 12.88
CHAMFER 10.08
16.51
2X (R1) MAX
OPTIONAL 9.25
7.67
(4.25) C
PIN 1 ID
(OPTIONAL)
NOTE 3
14.73
12.29
1 5
0.61
1.02
5X 0.30
0.64 3.05
0.25 C A B 2.03
4X 1.7
6.8
1 5
4215009/A 01/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Shape may vary per different assembly sites.
www.ti.com
EXAMPLE BOARD LAYOUT
KC0005A TO-220 - 16.51 mm max height
TO-220
4X (1.45)
PKG
0.07 MAX METAL 0.07 MAX

(1.45) TYP ALL AROUND
ALL AROUND
PKG
(2) 4X (2)
1 5
(R0.05) TYP SOLDER MASK FULL R
(1.7) TYP OPENING, TYP TYP
5X ( 1.2) (6.8)
LAND PATTERN
NON-SOLDER MASK DEFINED
SCALE:12X
4215009/A 01/2017
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2022, Texas Instruments Incorporated

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BUF634 250-mA High-Speed Buffer

2 Applications The BUF634 is available in a variety of packages to

Boost the Output Current of any Operational Amplifier

Changes from Revision A (November 2015) to Revision B Page

Changes from Original (September 2000) to Revision A Page

2 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

5 Device Comparison Table

IQ/CHANNEL SLEW RATE VOLTAGE NOISE

6 Pin Configuration and Functions

P and D Packages KC Package

Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

4 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

7.5 Electrical Characteristics

Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

Electrical Characteristics (continued)

6 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

7.6 Typical Characteristics

–20 CL = 50pF –20 CL = 50pF

Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

Typical Characteristics (continued)

Power Supply Rejection (dB)

Limit Current (mA)

Quiescent Current (mA)

8 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

Typical Characteristics (continued)

Output Voltage Swing (V)

Power Dissipation (W)

2 TO-220 and DDPAK 8

Input 100mV/div Input 100mV/div

Figure 17. Small-Signal Response Figure 18. Large-Signal Response

Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

8.2 Functional Block Diagram

Signal path indicated in bold.

10 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

8.3 Feature Description

8.4 Device Functional Modes

Copyright © 2000–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

9 Application and Implementation

9.1 Application Information

Figure 19. Buffer Connections

9.1.1 High Frequency Applications

Figure 20. High Performance Headphone Driver

12 Submit Documentation Feedback Copyright © 2000–2019, Texas Instruments Incorporated

Product Folder Links: BUF634

Application Information (continued)

NOTE: (1) System bypass capacitors.

Figure 21. Pseudo-Ground Driver

Figure 22. Current-Output Valve Driver

1kΩ 9kΩ 10kΩ