ABSTRACT

SURI, RAHUL. Device Design of Sub100nm Fullydepleted SilicononInsulator (SOI) Devices BasedonHighkEpitaxialBuriedOxide.(UnderthedirectionofDr.VeenaMisra). The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. TheeraofplanarbulkMOStransistor,however,isnearingitsend.TheperformanceofbulkMOS transistor is severely degraded by short channel effects in the sub65nm regime. In such a scenario,theSilicononInsulator(SOI)technologylookssettobecomethenextdriverofCMOS scaling. SOI has been proved capable of providing increased transistor speed, reduced power consumptionandenhanceddevicescalabilityasdemandedbythe65nmandbeyondtechnology generations.TheproblemsfacingSOIincludefabricationofthinsiliconandburiedoxide(BOX) filmsandhighmanufacturingcost. ThisthesisfocusesonanovelapproachtobuildingaSOIsubstratewhichusesanepitaxialoxide astemplatetogrowsiliconontop.ThenovelFloatingEpitaxySOIaimstoguaranteethinsilicon films and low manufacturing cost. This research work involves modeling ultrathin body fully depleted SOI devices from 60nm gate length down to 10nm gate length. The device uses metal/highk gatestack and strained silicon as attractive features for better device performance. Thegoalofthisworkistoreengineerthedevicestructureandalterdevicedesignparametersat everygatelengthsuchthatdeviceperformancemeetsthesemiconductorroadmapprojectionsin terms of offstate leakage current and ratio of drive current to leakage current as specified by InternationalTechnologyRoadmapforSemiconductors.(ITRS) Achallengetobetterdeviceperformanceisthehighpermittivityofcandidateepitaxialoxides.It iswellestablishedthathighpermittivityburiedoxidelayeraddsadditionalshortchanneleffects. Thismakesdevicedesignandcontrolofshortchanneleffectsmoredifficult.Themajorfindings of this thesis are that ultrathin body SOI devices based on Floating Epitaxy SOI meet ITRS projections down to 10nm gate length. Moreover, for sub15nm devices that require ultrathin BOX,highpermittivityofBOXdoesnthurtdeviceperformancebutimprovesitslightly.

 DeviceDesignofSub100nmFullydepletedSilicononInsulator(SOI) DevicesBasedonHighkEpitaxialBuriedOxide by Rahul Suri

A thesis submitted to the Graduate Faculty of North Carolina State University In partial fulfillment of the Requirements for the degree of Master of Science

Electrical Engineering Raleigh, North Carolina 2006

Approved By:

Dr. Carlton Osburn

Dr. Jon-Paul Maria

Dr. Veena Misra Chair of Advisory Committee

To

Mom,DadandBrother

ExcerptfromTheWonderYears:Becausethatnight,whenmyfatherletKarengoout,heletKaren go,andmaybethatshowithadtobe.......Childrenleave...andparentsstaybehind.Still,somethings aredeeperthantimeanddistance.Andyourfatherwillalwaysbeyourfather...Andhewillalways leavealightonforyou.

ii

BIOGRAPHY

RahulSuriwasborninNewDelhi,IndiainOctober1982.HereceivedhisBachelorofEngineering (B.E.)degreeinElectronicsandCommunicationfromNetajiSubhasInstituteofTechnology,India,in June2004.InAugust2004,hebeganhisgraduatestudiesinElectricalEngineeringatNorthCarolina StateUniversity.HisfocushasbeenonICFabricationandNanotechnology.InSummerof2005,he internedwithQimondaNA(formerlyInfineonTechnologiesNA),Cary,NCintheMemoryProduct Designgroup.HeworkedonthelayoutofDRAMchipin70nmtechnology.Whileworkingtowards his Masters degree, he worked on his thesis under the guidance of Dr. Veena Misra. He plans to continue his graduate studies towards earning the doctorate degree. His research interests include nanoscale device design, modeling and characterization. He is also interested in emerging, silicon andnonsiliconbasednanotechnologies.

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ACKNOWLEDGEMENTS

Aboveall,Ithankmyparentsforthemuchneededmotivationthroughoutthedurationofgraduate studies and particularly thesis work. It was their love and support that helped me maintain sanity duringstressfultimes.EverytimeIfeltIwaslosingtrack,theykindledstronghopeandbeliefinme thathelpedmetogetgoingwithpositiveapproachandenthusiasm. Isincerelythankmyadvisor,Dr.VeenaMisraforgivingmetheopportunitytoworkonthisthesis project and guiding me from time to time with useful suggestions. I am indebted to her for the knowledgethatshehasimpartedtomethroughacoupleofhercoursesFrontiersofNanoelectronics andPrinciplesofMOSTransistor,whichencouragedmetotakeupthisfieldseriouslyandIbelieve willformthefoundationofmycareer. IamgratefultoDr.CarltonOsburnforhavingtaughtthecoursesICTechnologyandFabricationand Semiconductor Characterization both of which built the fundamentals and strengthened my understandingofthisfield.ThetalksIhavehadwithhimhaveinspiredmeinwaysmorethanone.I thankhimforagreeingtobeonmythesiscommittee IwouldliketothankDr.JonPaulMariaforagreeingtobeonmythesiscommittee.Iwouldalsolike tothankDr.AngusKingon,DanLichtenwalnerandJenniferHydrickwhoworkedonthematerials issuesofthethesisprojectandgaveusefulfeedbackbasedonexperimentalresultsandencouraged metocomeupwithpositiveresults. IwouldliketothankmyfriendsVivekMehtaandPranavwithwhomIspentmostofmytime,for their support and encouragement. I thank Namrata for her understanding and supportive nature, DhavalParekhforhelpandsupport,DeepakforinspiringmetoworkhardandShoubhikDossfor sharingjovialtimesandseveralfoodsessions.SpecialthankstomyroommatesArun,VivekJayadev, Ajay and Nitin for making my stay memorable and for good southindian food. I also thank Ajit, KaushikandRaviforusefuldiscussions.FinallyIthank,Muktabh,Jay,NeilandTheVivekHakim forprovidingawesomeentertainmentduringtheperiodofthesiswriting.

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CONTENTS

ListofFigures..viii ListofTablesxi 1Introduction1

1.1SilicononInsulatorandCMOSScaling......................................................................................... 1 1.2SilicononInsulatorAdvantages..................................................................................................... 2 1.3SilicononInsulatorDevices ............................................................................................................ 3 1.4SilicononInsulatorFabrication ...................................................................................................... 5 1.4.1BondandEtchBack(BESOI) .............................................................................................. 5 1.4.2SeparationbyImplantationofOxygen(SIMOX)............................................................. 5 1.4.3UnibondorSmartCutTM ..................................................................................................... 6 1.5SilicononInsulatorChallenges....................................................................................................... 6 1.6References .......................................................................................................................................... 7

2 FloatingEpitaxySOI8
2.1MotivationforResearch................................................................................................................... 8 2.2FloatingEpitaxySOIANovelApproach ................................................................................... 9 2.3ChoiceofEpitaxialOxide .............................................................................................................. 10 2.4FloatingEpitaxySOIAdvantages ................................................................................................ 11 2.5ThesisGoal....................................................................................................................................... 11 2.6ThesisOrganization........................................................................................................................ 12 2.7References ........................................................................................................................................ 12

3 DeviceModelingonFloatingEpitaxySOI14
3.1Introduction ..................................................................................................................................... 14 3.2UTBDeviceStructure..................................................................................................................... 14 3.2.1SiliconBody......................................................................................................................... 14 3.2.2Buriedoxide ........................................................................................................................ 15 3.2.3SiliconSubstrate ................................................................................................................. 15 3.2.4Gatestack ............................................................................................................................. 16 3.3ModelingSetup ............................................................................................................................... 16 3.4Conclusion ....................................................................................................................................... 16

4 StrainedSiliconandDevicePerformance 17
4.1Needforstrainedsilicon................................................................................................................ 17 4.2StrainingtheSiChannel................................................................................................................. 18 4.2.1Processinducedstrain....................................................................................................... 18 4.2.2Substrateinducedstrain.................................................................................................... 18 4.2.3UniaxialVsBiaxialStrain.................................................................................................. 20

4.3MobilityEnhancement ................................................................................................................... 20 4.4StrainedSilicononInsulator......................................................................................................... 23 4.5ModelingStraininthiswork ........................................................................................................ 23 4.6SimulationResults .......................................................................................................................... 24 4.6.1SimulationSetup ................................................................................................................ 24 4.6.2StrainandDriveCurrent................................................................................................... 25 4.6.2StrainandLeakageCurrent .............................................................................................. 25 4.6.2StrainandThresholdVoltage ........................................................................................... 25 4.6.3StrainandDrainInducedbarrierLowering................................................................... 27 4.7Conclusion ....................................................................................................................................... 27 4.8References ........................................................................................................................................ 29

5InitialDeviceDesign30
5.1Introduction ..................................................................................................................................... 31 5.2SimulationSetup............................................................................................................................. 31 5.3SimulationResults .......................................................................................................................... 33 5.2.1TemplateThicknessEffect................................................................................................. 33 5.2.2ChannelLengthEffect ....................................................................................................... 40 5.2.3ITRSandDevicePerformance .......................................................................................... 40 5.4ConclusionandNext...................................................................................................................... 40

6GroundPlaneConcept44
6.1Introduction ..................................................................................................................................... 44 6.2GroundPlaneConcept................................................................................................................... 44 6.3GroundPlaneVsClassicalSOI ..................................................................................................... 46 6.4GroundPlaneSimulationSetup ................................................................................................... 49 6.5SimulationResults .......................................................................................................................... 49 6.5.1PotentialinBOXandsubstrate......................................................................................... 49 6.5.2TemplateThicknessEffect................................................................................................. 52 6.5.3ContinuousGroundplaneVsGroundplaneundergate............................................. 52 6.5.4GroundplaneDeviceandITRS ....................................................................................... 56 6.6ConclusionandNext...................................................................................................................... 56 6.7References ................................................................................................................... 58

7SuppressingShortChannelEffects59
7.1Introduction ..................................................................................................................................... 60 7.2SiliconChannelDopingEffect ...................................................................................................... 60 7.3SiliconFilmThicknessEffect......................................................................................................... 61 7.4BackgateBiasEffect....................................................................................................................... 63 7.5GateWorkfunctionEffect .............................................................................................................. 65 7.6SimulationSetupandResults ....................................................................................................... 67 7.6.1Varyingthesiliconfilmthickness .................................................................................... 67 7.6.2Varyingthebackgatebias ................................................................................................ 70 7.6.3Relationshipbetweensiliconfilmthicknessandbackgatebias ................................. 70 7.7Conclusion ....................................................................................................................................... 74 7.8References ........................................................................................................................................ 74

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8BuriedInsulatorEngineering75
8.1Introduction ..................................................................................................................................... 76 8.2BOXThicknessScaling................................................................................................................... 76 8.3BOXPermittivityScaling ............................................................................................................... 79 8.4PermittivityroleatthickandthinBOX ....................................................................................... 79 8.5DeviceSimulationofepiSOIdevice............................................................................................ 87 8.5.1VaryingTemplateThickness ............................................................................................ 87 8.6Conclusion ....................................................................................................................................... 89 8.7References ........................................................................................................................................ 89

9DeviceDesignOptimization90
9.1Introduction ..................................................................................................................................... 91 9.260nmGateLength........................................................................................................................... 91 9.345nmGateLength........................................................................................................................... 94 9.430nmGateLength........................................................................................................................... 96 9.525nmGateLength........................................................................................................................... 99 9.615nmGateLength......................................................................................................................... 104 9.710nmGateLength......................................................................................................................... 108 9.8MeetingITRSIon/IoffSpecification ........................................................................................... 113 9.9Conclusion ..................................................................................................................................... 115

10ConclusionandFutureWork116
10.1Conclusion ................................................................................................................................... 116 10.2FutureWork ................................................................................................................................ 117

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List of Figures
Figure11CrosssectionofanultrathinbodyfullydepletedSOIdevice....................................... 2 Figure12DifferentgateconfigurationsforSOIdevices................................................................... 4 Figure13CrosssectionofaFinFET ..................................................................................................... 4 Figure21CrosssectionofFloatingEpitaxySOIsubstrate................................................................ 9 Figure22Comparisonoflatticeparametermismatchtosiliconoveratemperaturerange....... 10 Figure31UTBSOIMOSFETbasedonFloatingEpitaxySOI.......................................................... 15 Figure41TEMmicrographof45nmptypeandntypeMOS ........................................................ 19 Figure42FormationofSiGealloyandgrowthofstrainedSiontop............................................. 19 Figure43MobilityenhancementratioforstrainedSinMOSFETs ............................................... 19 Figure44Straininducedconductionbandsplittinginsilicon ....................................................... 22 Figure45EnergyalignmentoftheSiconductionbandwithandwithoutthetensilestrain ..... 22 Figure46Simplifiedholevalencebandstructureforlongitudinalinplanedirection................ 22 Figure47IdVgcurvesforLg=25nmwithandwithoutstraininSichannel................................ 26 Figure48IdVgcurvesforLg=15nmwithandwithoutstraininSichannel................................ 26 Figure49IonandIoffVschannellengthfordevicewithandwithoutstraininSichannel....... 28 Figure410VtandDIBLversuschannellengthfordevicewithandwithoutstrain...................... 28 Figure51EpitaxialoxidebasedSOIdevice(eSOI) .......................................................................... 32 Figure52StandardSOIdeviceortheCoredevice......................................................................... 32 Figure53Lg=60nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................ 34 Figure54Lg=45nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................ 34 Figure55Lg=30nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................. 35 Figure56Lg=25nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................ 35 Figure57Lg=15nma)Ioffc)IonversusTemplateThicknessforcoreandnewdevice ............ 36 Figure58Lg=10nma)Ioffc)IonversusTemplateThicknessforcoreandnewdevice ............ 36 Figure59EquipotentialContoursin30nmepiSOIdevicewith5nmthicktemplate ................. 37 Figure510a)Vtb)Offstatecurrentandc)onstatecurrentversusTemplateThickness ............ 39 Figure511a)Vtb)Offstatecurrentandc)onstatecurrentversusChannelLength ................... 41 Figure512a)Ioffb)IoncomparisonwithITRSHighPerformanceLogicProjections.................. 42 Figure513ComparisonofdeviceIon/IoffratioandITRSHPLogicprojections ........................... 42 Figure61SchematicoffringingfieldsinSOIdevice........................................................................ 45 Figure62ElectrostaticPotentialContoursintheBOXandsubstrateofaSOIdevice ................ 45 Figure63GroundPlanestructures..................................................................................................... 45 Figure64Equipotentialcontoursina0.1mmlongdevicewithVg=0VandVd=1.5V............. 47 Figure65Verticalpotentialprofileinthemiddleofa80nmlongSOIMOSFET ....................... 48 Figure66KeyprocessingstepsofGroundPlaneformation........................................................... 48 Figure67a)Vtrolloffandb)DIBLfordevicewithandwithoutgroundplane ......................... 50 Figure68Simulatedverticalpotentialacrosscenterofsiliconbodyfor25nmlongdevice: ...... 50 Figure69Simulatedpotentialcontoursin25nmlongdevicewith5nmthicktemplate............. 51 Figure610Lg=60nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................. 53

viii

Figure611Lg=45nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................. 53 Figure612Lg=30nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................ 54 Figure613Lg=25nma)ThresholdVoltageb)Ioffc)IonversusTemplateThickness ................ 54 Figure614Lg=15nma)Ioffc)IonversusTemplateThicknessforcoreandnewdevice ............ 55 Figure615Lg=10nma)Ioffc)IonversusTemplateThicknessforcoreandnewdevice ............ 55 Figure616ComparisonofdeviceIoffvalueswithITRSHPLogicprojections.............................. 57 Figure617ComparisonofdeviceIon/IoffratioswithITRSHPLogicprojections ........................ 57 Figure71VtshiftVsTSifordifferentchanneldoping ..................................................................... 62 Figure72MEDICIpredictedTSiandchanneldopingrequirementsforFDSOICMOS.............. 62 Figure73Thresholdvoltagerollofffordifferentchanneldoping ............................................... 62 Figure74Thresholdvoltageversuschannellengthformildandstronghaloimplants............ 64 Figure75DIBLandsubthresholdswingVschannellengthfordifferentTSi .............................. 64 Figure76DependenceofVtandQMshiftinVtonTSi ................................................................... 64 Figure77TheoreticaldependenceofVtonbackgatevoltage ...................................................... 66 Figure78DependenceofVtonbackgatevoltage .......................................................................... 66 Figure79DIBLVsTSifordifferentbackgatevoltages.................................................................... 66 Figure710TSidependenceoftheoffstatecurrentof50nmUTBdevice....................................... 68 Figure711RatioofIon/Ioffpf50nmUTBdevicefordifferentTSiandMvalues ....................... 68 Figure712RatioofVt/VtversusTSiwithdifferentMvalues ...................................................... 68 Figure713DIBLVsLgfordifferentTSifordevicewithgroundplaneandwithout................... 69 Figure714VtrolloffforTSi=5nmand10nmfordevicewithgroundplaneandwithout ......... 69 Figure715VtrolloffforTSi=5nmand10nmfordevicewithgroundplaneandwithout.......... 69 Figure716SubVtSwingVsLgfordifferentTSifordevicewithandwithoutgroundplane. .... 69 Figure717IoffVsLgfordifferentTSifordevicewithgroundplane.............................................. 71 Figure718RatioIon/IoffVsLgfordifferentTSifordevicewithgroundplane ............................ 71 Figure719VtVsLgforgroundplanedevicewithTSi=7nmanddifferentVbg........................... 71 Figure720DIBLVsLgforgroundplanedevicewithTSi=7nmanddifferentVbg ...................... 71 Figure721SubVtSwingVsLgforgroundplanedevicewithTSi=7nmanddifferentVbg........ 72 Figure722IoffVsLgforgroundplanedevicewithTSi=7nmanddifferentVbg ......................... 72 Figure723RatioIon/IoffVsLgforgroundplanedevicewithTSi=7nmanddifferentVbg......... 72 Figure724ThresholdvoltageVsVbgforgroundplanedevicewithTSi=5nmand10nm .......... 73 Figure725SubVtSwingVsVbgforgroundplanedevicewithTSi=5nmand10nm................... 73 Figure726DIBLVsVbgforgroundplanedevicewithTSi=5nmand10nm................................. 73 Figure81Simulatedequipotentialcontoursingroundplanedevice,TBox=200nm................... 78 Figure82Simulatedequipotentialcontoursingroundplanedevice,TBox=10nm.................... 78 Figure83DIBLVsBOXthicknessforgroundplanedevicewithVbg=0.2Vand1V................. 81 Figure84DIBLVsBOXthicknessforgroundplaneandLDdevicewithVbg=0.2Vand1V.... 81 Figure85DIBLversusBOXthicknessfork=3.9andk=5.0,Lg=30nm,TSi=7nm,Wf=4.7eV ......... 82 Figure86ThresholdVoltageVsTBoxfork=3.9andk=5.0,Lg=30nm,TSi=7nm,Wf=4.7eV ......... 82 Figure87Electrostaticpotentialalongbody/BOXinterfaceatTBox=200nmand10nm.............. 84 Figure88ThresholdvoltageVsVbgforTBox=200nm,25nmand10nmfork=3.9andk=5.0 ...... 84 Figure89SubthresholdswingVsBOXthicknessforgroundplanedevice ................................. 86 Figure810IdVgcurvesforgroundplanedeviceforTbox=10nmand100nmatBOX ................ 86 Figure811DIBLVsLgfortwotemplatethicknessesfordevicewithgroundplane .................... 88 Figure812VtrolloffVsLgfordifferenttemplatethicknessesfordevicewithgroundplane ... 88 Figure813VtrolloffVsLgfor5nmand2nmtemplatethicknessesforgroundplanedevice ... 88

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Figure814SubVtSwingVsLgfordifferenttemplatethicknessesforgroundplanedevice...... 88 Figure91IdVgplotforLg=60nmfordifferenttemplatethicknesses. .......................................... 92 Figure92IdVgplotforLg=45nmfordifferenttemplatethicknesses. .......................................... 95 Figure93IdVgplotforLg=30nmfordifferenttemplatethicknesses. .......................................... 97 Figure94IdVgplotforLg=30nmfor5nmand4nmthicktemplate,Tbox=15nmand10nm....... 98 Figure95IdVgplotforLg=25nmfordifferenttemplatethicknesses. ........................................ 100 Figure96IdVgplotforLg=25nmfortwodevicedesignparametersandTSi=7nm ................. 102 Figure97IdVgplotforLg=25nmfor5nmand4nmthicktemplateatTbox=15nmand10nm. 103 Figure98IdVgplotforLg=15nmfordifferenttemplatethicknesses. ........................................ 105 Figure99IdVgplotforLg=15nmfor4nmthicktemplate,TSi=5nm,TBox=6nm,M=4.53eV. .. 107 Figure910IdVgplotforLg=15nmwithTSi=5nm,TBox=6nm,M=4.53eVandVbg=1V.............. 108 Figure911IdVgplotforLg=10nmfordifferenttemplatethicknesses ......................................... 109 Figure912IdVgplotforLg=10nmwithTSi=5nm,TBox=5nm,Vbg=0.4VandvariableM. ........ 111 Figure913ITRSexpectedandSimulatedIon/Ioffratioversuschannellength............................ 113 Figure914ITRSexpectedandSimulatedIon/Ioffratioversuschannellength............................ 114

List of Tables
Table91Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor60nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare1E8A/umand0.9mA/um ...................................................................... 93 Table92Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor45nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare3E8A/umand0.98mA/um .................................................................... 95 Table93Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor30nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare5E8A/umand1.09mA/um .................................................................... 97 Table94Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor25nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare1.7E7A/umand1.48mA/um .............................................................. 101 Table95Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor15nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare2.9E7A/umand2.03mA/um .............................................................. 105 Table96Vt,Ioff,Ion,SubthresholdswingandDIBLvaluesfor10nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIon specificationsare3.7E7A/umand2.18mA/um .............................................................. 110 Table97SummaryofdevicedesignparameterstomeetITRSHPLogicIon/Ioff specificationfordifferentchannellengths. ....................................................................... 114

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Chapter 1
Introduction
1.1 Silicon on Insulator and CMOS Scaling
The Integrated Circuit industry is driven by the continuously shrinking feature size of devices. In the last two decades, device feature size has decreased from 1m down to 90nm. Scaling the physical device dimensions (both lateral and transverse) has led to increased speed, higher packing density, and reduced cost per good device built. The era of planar bulk MOS transistor, however, is nearing its end. The performance of bulk MOS transistor is severely degraded by short channel effects in the sub-65nm regime. Most important of short channel effects include the threshold voltage roll-off problem and drain-induced barrier lowering (DIBL). The conventional MOSFET, thus, doesnt look promising to meet the requirements of 65nm and below technology nodes as specified by the International Technology Roadmap for Semiconductors (ITRS). In such a scenario, the Silicon-on-Insulator (SOI) technology looks set to become the next driver of CMOS scaling. SOI has been proved capable of providing increased transistor speed, reduced power consumption and enhanced device scalability as demanded by the next technology generations. Compared to similar circuits fabricated on bulk silicon wafers, CMOS circuits fabricated on SOI wafers can run at 20-35% higher switching speeds than bulk CMOS, or 2 to 4 times lower power requirements when operating at the same speed as bulk CMOS [1]. Research on SOI dates back to 1960s when these devices were used for military and space applications because of their immunity to radiationinduced ionization. Cost of manufacturing SOI wafers prevented their widespread growth and use. Today, however, the ever increasing demand for higher speed and lesser power consumption makes the inherent advantages of SOI, look all the more attractive. So much so that SOI has made its way into the semiconductor roadmap and the ultra thin body SOI transistor is projected to be into manufacturing mainstream by 2008. [2] According to France-based Soitec, which produces SOI wafers based on its patented Smart Cut technology, SOI currently represents some 3-4% of the total wafer market, and this is expected to rise to 10% by the end of the decade. [3] Almost all semiconductor companies have either switched to SOI or are considering it for current and future devices. While IBM, AMD, Sony Group and Toshiba have adopted SOI for the cell processor, Philips Semiconductors has been using SOI for high voltage ICs. Freescale and STMicroelectronics have also begun to use to use SOI wafers. Several device architectures based on SOI varying from single gate to multiple gate structures have evolved and are in the stage of being researched. These include ground-plane SOI, Double-gate SOI, FINFET and so on. The

Moores law that drives scaling will continue to live on once the SOI technology hits the manufacturing mainstream completely.

1.2 Silicon on Insulator Advantages

The SOI substrate comprises of a silicon device layer usually tens of nanometers thick isolated from the substrate by a relatively thick layer of insulating material, usually silicon dioxide, called buried oxide. The cross-section of SOI device is shown in Figure 1-1. The major advantage of SOI comes from the fact that the source and drain junctions end on the buried oxide layer, hence junction capacitances are minimized. Also, because thin silicon film is employed, the junction depth is small and sub-surface leakage paths are eliminated. In case of ultra thin body, the front gate has strong control over the channel and short channel effects are suppressed. The reduction in source-drain parasitic capacitances makes switching operations faster and enhances speed. It also leads to reduction in power consumption. IBM reported a 20% to 35% increase in chip speed and 35% to 70% reduction in power consumption for their PowerPC chips [4] Because, short channel effects are suppressed, SOI device has a steep subthreshold slope which translates to a smaller off-state leakage current and larger drive current. The device is well isolated from substrate both vertically by buried oxide and laterally by shallow trench or LOCOS grown oxide which has three significant advantages. Firstly, any causes for latch-up in CMOS and cross-talk between devices in mixed signal ICs are avoided. Secondly, soft errors from radiation effects usually in case of SRAMs are minimized. And thirdly, different voltages may be used on different devices without the added processing steps required for triple wells. As semiconductor process technologies move down the nanometer scale from 90nm to 65nm and smaller, the benefits of silicon-on-insulator (SOI) wafers in reducing junction capacitance, improving the short-channel effect, reducing leakage and decreasing soft error rates become more and more attractive.

Figure 1-1 Cross-section of an ultra thin body fully-depleted SOI device (UTB SOI) [5]

1.3 Silicon on Insulator Devices

Dependingonthethicknessofthesiliconlayer,SOIMOSFETwilloperateinfullydepleted(FD) or partially depleted (PD) regime. In PD regime, the silicon body is thick enough so that the depletion region in the channel doesnt extend up to the bodyBOX interface. A neutral region existsandgivesrisetofloatingbodyeffectssuchaskinkinIdVdcharacteristics;latchanddrain current overshoot and undershoot. [6] The majority carriers, generated by impact ionization, collectinthetransistorbody.Thiscausesthebodypotentialtorise,whichlowersthethreshold voltage.ThisfeedbackgivesrisetoakinkinIdVdcharacteristics,hysteresisandlatchinlogId Vgcurves,andactivationofthelateralbipolartransistor.[7]Properdesignisneededtominimize thedetrimentalaspectsofthefloatingbodyandtakeadvantageoftheextracurrentavailablefor fabricatingfastercircuits.InFDMOSFETs,thedepletionregioncoversthewholebodyandthe depletion charge is independent of the gate bias. A better coupling develops between gate voltageandinversioncharge,leadingtoenhanceddrivecurrent.Inaddition,thefrontandback surface potentials also become coupled. The coupling factor is roughly equal to the thickness ratio between gate oxide and buried oxide. Due to interface coupling, the frontgate threshold voltagebecomesafunctionofthebackgatebias.Thebackgatebiasgivesadditionalcontrolover settingthethresholdvoltageofthedevice.TheFDdeviceshaveseveraladvantagescomparedto thePDdevices:freefromkinkeffect[7],enhancedsubthresholdswing[8],highestgainsincircuit speed,reducedpowerrequirementsandhighestlevelofsofterrorimmunity[9].Forsub100nm channellengthdevices,FDSOIdevicesarethepreferredchoice. Beyondthe65nmtechnologynode,nonclassicalCMOSdevicesbasedonSOIwilltakeoverfrom bulk devices. The frontrunner is the ultra thin body (UTB) SOI MOSFET shown in Figure 11. Following it are multiple gate devices which have two or more surfaces along which inversion occurs and current flows. These include doublegate and triplegate structures such as the quantumwire[10],theFinFET[11]andchannelSOIMOSFET[12],andquadruplegatedevices suchasthegateallaround(GAA)device[13],theDELTAtransistor[14],verticalpillarMOSFETs [15],andPigateSOIMOSFETs[16].Itiswellknownthatthedoublegate(topandbottomgate) silicononinsulator (SOI) MOSFET and the gateallaround device are the most suitable device structures for suppressing shortchannel effects such as DIBL and subthreshold slope

degradation [13], [17], [18]. Figure 12 shows the existing gate configuration for thinfilm SOI MOSFETs:1)singlegate;2)doublegate;3)triplegate;4)quadruplegate(orGAA)and5)pigate.

Figure12DifferentgateconfigurationsforSOIdevices:1)singlegate;2)doublegate;3)triple gate;4)quadruplegate;5)PigateMOSFET[19] TheFinFET,showninFig.12,hasthinfinsofSietchedintothetopSilayerandgateelectrodes that are deposited and patterned on the sides of each fin. The inversion layer is formed on the verticaledgeofeachfin,andthecurrentflowsfromsourcetodrainalongtheseedges

Figure13CrosssectionofaFinFET[5] While 2D and 3D device simulation of mutilple gate devices show them to be the ultimate deviceswithsuppressedshortchanneleffectsandsteepsubthresholdslope,asrequiredforsub 50nm devices, unfortunately the process proposed to fabricate these is incompatible with standardCMOSorevenSOICMOSmanufacturing.Itisexpectedthatbythetimetheneedfor multiple gate structures becomes necessary, advancements in lithography, etching and wafer processingtechniqueswilloccurtoallowforeasyfabricationofthesedevices.

1.4 Silicon on Insulator Fabrication

CurrentmethodsofSOIfabricationincludethosebasedpurelyonwaferbonding,suchasBond and EtchBack SOI (BESOI), those based purely on ion implantation, such as Separation by Implantation of Oxygen (SIMOX), and those based on combination of wafer bonding and ion implantation,suchasSmartCutbySOITEC.

1.4.1 Bond and Etch Back (BESOI)

BESOI wafers are made by bonding together two oxidized wafers, annealing, and etching or grindingandpolishingtoachieveathinsilicondevicelayer.Whenplacedtogether,theoxidized waferssticktogetherwithaweakhydrogenbond.Anannealingstepremovesexcesswaterfrom theinterface,andcreatesacontinuousburiedoxide(BOX)layer.Eitheretchingorgrindingand polishing is employed to thin the silicon layer up to desired silicon body thickness. Etching requirestheuseofanetchstopwhichisusuallyaburiedlayerofimplantedboron.BESOIwafers aretypicallymadebythegrind/polishmethod,astheyarenolongerconsideredusefulforthin filmSOI.[20]Thesewafersresultinthicksiliconbodyandareusedforhighvoltage,highpower devicesormicroelectromechanicalsystems.[21]ThethicksiliconassociatedwithBESOImakesit notappropriateforultrathinbodydevices.

1.4.2 Separation by Implantation of Oxygen (SIMOX)

A large dose of oxygen ions is implanted into a silicon wafer. A postimplant anneal at about 1300C follows for as long as 6 hours. Oxygen ions react with silicon to form silicon dioxide. Annealing also repairs damage done to silicon device layer by implantation and restores its crystalline quality. The implantation energy decides the location of silicon dioxide underneath the surface and therefore controls the silicon body thickness. Implantation dose must be controlled to ensure that there is sufficient oxygen to create a full SiO2 layer of the appropriate thickness, and also that no silicon islands appear in the oxide film after annealing. [21] Lower doses and higher annealing temperature anneals are used to minimize defect generation in the silicon device layer. SIMOX wafers have good thickness uniformity, low defect density (except threading dislocations: 104106 cm2), sharp SiSiO2 interface, robust BOX, and high carrier mobility.[22]

1.4.3 Unibond or Smart-CutTM

Hydrogen ions are implanted into a thermallyoxidized wafer.The depth of implant below the oxideformsthesiliconbodythickness.Itisthereforecontrolledbytheimplantationenergy.This waferisthenbondedtoasiliconhandlewafer,followedbyatwostepannealingprocess.[21]A firstannealat400600Callowsmicrocracksinthesiliconintheimplantedregionthatcausethe wafer to split, leaving a thin silicon device layer on top of the thermal oxide layer. A second annealat1100Cfortwohoursremovessilanolgroupsfromthebondedinterface,whichleavesa silicon/oxideinterfaceofsimilarqualityasthatofathermallygrownoxideonsilicon.[21].Touch polishing (removes tens of nanometers) of the surface silicon layer is done to complete the processingofSOIwafer.TheadvantagesofUnibondwaferinclude1)noetchbackstep,2)seed wafers can be reused, 3) thickness control of oxide layer by oxidation time, 4) much better thickness control of device layer and 5) only conventional equipment is needed for mass production

1.5 Silicon on Insulator Challenges

Although SOI technology is well established to provide high performance at low power, the widespread adoption of SOI wafers still faces both real and perceived challenges. The main barriertothewidespreadadoptionofSOIwafersformainstreamCMOSfabricationinthepast hasbeentheuncertainsiliconfilmorsilicondioxidelayerqualityandthehighcostofSOIwafers. The key materials quality issues are 1) the continuity and thickness uniformity of the BOX, 2) thicknessuniformityofsilicondevicelayerand3)levelofdefectsinsiliconlayer.ImportantBOX defects include voids and inclusions while defects in the silicon top layer include threading dislocations and pits. Also, the interface charge trapped at the interface of the top silicon layer and the BOX must be kept small since it tends to shift the threshold voltage from the desired value and affects electrical behavior of the device. As the CMOS technology scales, the requirement for thinner and thinner silicon films also becomes a concern and a challenge for presentSOIfabricationprocesses.

1.6 References

[1] D. K. Sadana and M. Current, Fabrication of SiliconOnInsulator (SOI) Wafers Using Ion Implantation, in Ion Implantation Science and Technology, Edited by J. F. Ziegler, Ion ImplantationTechnologyCo.,2000,p.341374. [2]InternationalTechnologyRoadmapforSemiconductors2005Edition (http://www.itrs.net/Links/2005ITRS/Home2005.htm) [3]ChrisHall,SoitecmovesaheadinSOI,DigiTimes.com,Taipei,Tuesday13September2005 [4]http://www.ibm.com/developerworks/library/pa-pek/ [5] G. A. Brown, P. M. Zeitzoff, G. Bersuker, and H. R. Huff, Scaling CMOS: materials and devices,MaterialsToday,p.2025,Jan2004 [6]G.G.Shahidietal,Aroomtemperature0.1umCMOSonSOI,IEEETrans.ElectronDevices 41(1994)2405. [7]S.CristoloveanuandS.S.Li,ElectricalCharacterizationofSOIMaterialsandDevices,Kluwer, Norwell(1995). [8] R. Berger, J. Burns, CL Chen, C. Chen, M. Fritze, P. Gouker, J. Knecht, A. Soares, V. Suntharalingam, P. Wyatt, DR Yost, Craig L. Keast, Low power, high performance, fully depletedSOICMOStechnology,DARPAJMTOAMEReview,31/8/1999 [9] M. I. Current, S. W. Bedell, I. J. Malik, L. M. Feng, F. J. Henley, What is the future of sub 100nm CMOS: Ultrashallow junctions or ultrathin SOI? Solid State Technology, Vol. 43, September,2000. [10]J.P.Colinge,X.Baie,V.Bayot,andE.Grivei,Asilicononinsulatorquantumwire,Solid StateElectron.,vol.39,no.1,pp.4951,1996. [11] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, and C. Hu, Sub 50 nm FinFET:PMOS,inIEDMTech.Dig.,1999,pp.6770. [12]Z.JiaoandC.A.T.Salama,AfullydepletedchannelSOInMOSFET,inProc.Electrochem. Soc.20013,2001,pp.403408. [13] J. P. Colinge, M. H. Gao, A. RomanoRodriguez, H. Maes, and C. Claeys, Siliconon insulatorgateallarounddevice,inIEDMTech.Dig.,1990,pp.595598. [14]D.Hisamoto,T.Kaga,Y.Kawamoto,andE.Takeda,Afullydepletedleanchanneltransist or(DELTA)anovelverticalultrathinSOIMOSFET,inIEDMTech.Dig.,1989,pp.833836. [15]C.P.AuthandJ.D.Plummer,Asimplemodelforthresholdvoltageofsurroundinggate MOSFETs,IEEETrans.ElectronDevices,vol.45,pp.23812383,Nov.1998. [16] J. T. Park, J. P. Colinge, and C. H. Diaz, Pigate SOI MOSFET, IEEE Electron Device Lett., vol.22,pp.405406,Aug.2001. [17]H.S.P.Wong,K.K.Chan,andY.Taur,Selfalign(topandbottom)doublegateMOSFET witha25nmthicksiliconchannel,inIEDMTech.Dig.,1997,pp.427430. [18] J. P. Denton and G. W. Neudeck, Fully depleted dualgated thinfilm SOI PMOSFETs fabricatedinSOIislandswithanisolatedburiedpolysiliconbackgate,IEEEElectronDeviceLett., vol.17,pp.509511,Nov.1996. [19]J.T.ParkandJ.P.Colinge,MultiplegateSOIMOSFETs:Devicedesignguidelines,IEEE Trans.ElectronDevices,vol.49,no.12,pp.22222229,Dec.2002. [20]R.A.McKee,F.J.Walker,andM.Chisholm,Phys.Rev.Lett.81(1998)3014. [21]J.Lettieri,J.H.Haeni,andD.G.Schlom,J.Vac.Sci.Technol.A20(4)(2002)13321340. [22]S.Cristoloveanu,AreviewoftheelectricalpropertiesofSIMOXsubstratesandtheirimpact ondeviceperformance.JElectrochemSoc138(1991),p.3131

Chapter 2
Floating Epitaxy SOI
2.1 Motivation for Research
Inordertomeettheeverincreasingdemandforhighspeedandlowpowerconsumption,devices continue to shrink in physical dimensions. As devices scale below 100nm gate length, silicon bodyneedstobethinnerandthinner.Twodimensionaldevicesimulationsin[1]showthat,the relationshipLg/TSi5betweengatelength,Lgandsiliconbodythickness,TSiisneededforFDSOI devicestosuppressshortchanneleffects(SCEs).Thismeans,forsub50nmdevices,siliconbody needstobelessthan10nmthick.Theburiedoxide(BOX)thicknessneedstoscaleaswelltogive more options for controlling the SCEs and improve subthreshold slope. [2] For substantive reduction of SCEs, BOX thickness needs to be less than 25nm. [3][4] Thus, from device performanceperspective,thinsiliconfilmandBOXthicknessarerequired.Atthesametime,the siliconfilmneedstobeasinglecrystalfilmofgoodqualityandfreefromdefects.Thiscreatesa challengetothepresentdaySOIfabricationprocesses.IbisTechnologyCorporationreportsthat typicalSOIparametersforSIMOXwafersare10145nmsiliconfilmthicknessanda145nmthick buriedoxide.[5]SOITEC,themanufacturerofSmartCutwafers,currentlyproducesSOIwafer with silicon thickness of 50nm100nm and uniformity of +/5nm, and buried oxide thickness of 50nm145nm +/5nm. [6] Neither of the two meets the specifications for silicon film and BOX thicknessforthisyear,setbyInternationalTechnologyRoadmapforSemiconductors.[7]Thus, current SOI manufacturing processes based on wafer bonding and ion implantation do not guaranteecontinuedsiliconlayerthinningandappropriatethicknesscontrol.Besides,thereare material issues and problems. Shallow implantation to produce thin silicon films results in defectsinsilicon.ThedisadvantagewithSIMOXtechniqueisthatimplantedoxygenionscause damage to silicon device layer. In order to repair the damage, a high temperature anneal is necessary which increases processing steps. A low dose of oxygen guarantees a thin BOX but qualityofoxidedegrades.Waferbondingtechniqueshavethedifficultyofappropriatethickness

control.Annealingisrequiredforbondedwafers,toallowwafersplitting,andthedistributionof hydrogenatomscanresultinunevensplittingandaneedforwaferpolishing.Thecombination of implantation, annealing, and polishing steps required to make SOI wafers by current SOI manufacturing processes renders the manufacturing very expensive. According to [8] SOI manufacturinginvlovesper300mmwafercostof~$1200,comparedtothebulksiliconwafercost of$200$250.TheneedoftodayisaSOIfabricationprocessthatiscapableofproducingdefect free and thin silicon films and at the same time allows a lower cost of production thereby promotingtheuseofSOIinthesemiconductorindustry.

2.2 Floating Epitaxy SOI A Novel Approach

Floating Epitaxy SOI is a novel approach proposed by Angus Kingon, JonPaul Maria, and Veena Misra to achieve good quality thin silicon film, designed so as to allow SOI to meet the longtermITRSspecificationsandmakeSOItechnologyadvantageousfromdeviceperformance andcostofproductionperspectives.TheconceptisillustratedinFigure21.Anepitaxialoxideis grownonsiliconsubstrateandisusedasatemplatetodepositepitaxialsiliconontop.Epitaxial deposition of silicon will make possible to produce thin films with good thickness control, less defectsandnegatetheneedforpostprocessingannealorpolishing.

Figure 2-1 Cross-section of Floating Epitaxy SOI substrate [9]

A thin layer of epitaxial oxide, which is crystalline in nature and closely latticematched to silicon,isdepositedonsiliconsubstratebymolecularbeamepitaxyprocess.Thislayerisrather thintokeepthelayercommensurateandavoidmisfitdislocationsandrelaxationasmuchasis feasible. The structure is heated in presence of oxygen, to allow oxygen to diffuse through the template oxide and form SiO2 at the silicon interface, effectively floating the stillepitaxial templateoxideontopofanamorphousinsulatinglayer.Oncetheinsulatinglayerissufficiently

thick, silicon is deposited under UHV conditions on the template layer, completing the SOI substratestructure.Bythisprocess,itiseasiertoproducethinratherthanthicklayersofsilicon and buried oxide, making Floating Epitaxy SOI an especially viable solution for the future technologygenerationsrequiringthinSOIfilmsforbetterdeviceperformance

2.3 Choice of Epitaxial Oxide

Goodprogresshasbeenmadeintheprocessingofepitaxialoxidesonsilicon.Materialsstudied includecomplexoxidesdepositedwithanalkalineearthoxidetemplate,ordirectdepositionof oxides such as Y2O3, Pr2O3, Gd2O3, CeO2, MgO and simple solid solution such as (LaxY1x)2O3. [10][11][12]However,forthefloatingepitaxySOI,thechoiceofepitaxialoxidedependslargely onthelatticeparameter.Theoxideshouldbeascloselylatticematchedtosiliconaspossibleforit toactasatemplateforgrowingsiliconontop.However,thefinalchoiceofoxidewilldependon experimentalgrowthandtemperaturestabilityresults.Agraphcomparingthelatticeparameter ofseveralcandidateoxideswiththatofsiliconoverthetemperaturerangeofinterestisshownin Figure22.Forgraphingpurposes,anaverageoftheaandblatticeparametersisused.

Figure 2-2 Comparison of lattice parameter mismatch to silicon over a temperature range [9]

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Several crystal structures are considered: cubic rocksalt structures (BaO, SrO), cubic and pseudocubic perovskites (SrTiO3, CaTiO3, LaAlO3), and bixbyite structures (Sm2O3, Ho2O3, Dy2O3). While pure oxides may not latticematch with silicon very well, the solidsolution combination of these pure oxides yields a lattice parameter rather close to silicon, for a given temperaturefor example Ba0.64Sr0.36O, a solid solution of BaO and SrO. Out of several explored template oxides, LaAlO3, SrTiO3 or a stack of LaAlO3 over SrTiO3 is found useful for Floating EpitaxySOI.

2.4 Floating Epitaxy SOI Advantages

Themostimportantadvantageoffloatingepitaxyprocessisthepossibilityofmakingultrathin silcon films on top of thinburied oxide. This isa very attractivefeature to thescaling needs of comingtechnologygenerations.Epitaxialdepositionofsiliconalsoassuresagoodqualitydevice layer. Moreover, the need for postprocessing annealing or polishing is avoided. With fewer fabrication steps involved, the novel process also guarantees a cost reduction in SOI manufacturing.Ifitcomesthroughsuccessfully,FloatingEpitaxywillsupersedetheSIMOXand SmartCuttechniquesandbecometheprimeSOImanufacturingprocess.

2.5 Thesis Goal

The work in this thesis involves modeling ultra thin body fullydepleted MOSFET based on Floating Epitaxy SOI and determining the viability of this novel substrate in terms of device electricalperformance.Since,UTBSOIMOSFETisthedeviceofchoiceforsub100nmMOSFETs; itisofinteresttoinvestigatethedeviceperformancebasedonFloatingEpitaxySOI.Aconcern from device performance perspective is that most of the candidate epitaxial oxides are highk oxides. While SrO has k=13, BaO has k=34. While LaAlO3 has k=26, SrTiO3has k=300. Traditionally, it has been shown that a high permittivity of buried oxide degrades device performance by introducing additional short channel effects. The aim of this work is to determine ifthe FloatingEpitaxy based UTB SOI device, irrespective of highk buried oxide, is capableofmeetingtheITRSspecificationsintermsoftheoffstateleakagecurrent,Ioffandmore importantlyIon/IoffratiowhereIonisthedrivecurrent.Thegoalofthesisistostudytheimpact ofdevicedesignparametersonperformanceofUTBSOIdeviceatdifferentgatelengthsandto reengineerthedevicestructureandparameterssoastomeettheITRSprojectionsdownto10nm

11

gatelength.UTBSOIdeviceisthefocusofthisworkasagainstmultiplegatedevicebecauseof the challenges associated with fabrication of the latter. This work explores the device design issuesrelatedwithsub100nmSOIdevices.

2.6 Thesis Organization

Chapter3describesdevicemodelingofUTBFDSOIdevicebasedonFloatingEpitaxySOI.The device design parameters are discussed. Chapter 4 describes how strain in silicon channel is modeled in device simulations and the impact of strain on device performance. Chapter 5 describes initial device simulation and defines the problem. Chapter 6 discusses in detail the concept of groundplane in suppressing short channel effects. Chapter 7 discusses other alternatives such as silicon body thinning, backgate bias effect and gate workfunction engineeringandtheirroleincontrollingshortchanneleffectsandsettingthethresholdvoltage. Chapter8discussesburiedlayerengineeringanditsroleinsuppressingshortchanneleffects.It alsohighlightsinterestingfactsabouttheroleofburiedoxidepermittivityatthickandthinBOX. Chapter 9 deals with device design optimization and highlights separately the device design parameters at which the ITRS Ion/Ioff specification is met for every gate length. I conclude my work finally with Chapter 10 describing future work that can be done to demonstrate the functionalityandadvantagesofUTBSOIdevicebasedonnovelFloatingEpitaxyapproach.

2.7 References
[1] V. P. Trivedi and J. G. Fossum, Scaling fully depleted SOI CMOS, IEEE Trans. Electron Devices,vol.50,no.10,pp.20952103,Oct.2003. [2] T. Numata, K. Uchida, J. Koga, and S. Takagi, Device design for subthreshold slope and thresholdvoltage control in sub100 nm fullydepleted SOI MOSFETs, IEEE Trans. Electron Devices,vol.51,pp.21612167,Dec.2004 [3] A.Vandooren, D. Jovanovic, S. Egley, M. Sadd, B.Y. Nguyen, B. White, M. Orlowski,and J. Mogab, Scaling assessment of fullydepleted SOI technology at the 30 nm gate length generation,inProc.IEEEInt.SOIConf.,Oct.2002,pp.2526. [4]V.P.TrivediandJ.G.Fossum,NanoscaleFD/SOICMOS:ThickorthinBOX,IEEEElectron DeviceLett.,vol.26,no.1,pp.2628,Jan.2005 [5] R.Dolan et al. 16th International Conference on Ion Implantation Technology 6/1113/06 (http://www.ibis.com/assets/pdf/iit2006characterizationpaper.pdf),accessed7/13/06 [6]SOITECProductsWebsite(UltrathinUNIBOND1) [7]InternationalTechnologyRoadmapforSemiconductors,2005Edition (http://www.itrs.net/Links/2005ITRS/Home2005.htm) [8]J.R.Sims,Jr.andR.N.Blumenthal.HighTemperatureScience8(1976)99110.

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[9]JenniferHydrick,PhDThesis,MaterialsScienceEngineering,NCSU,2006 [10]J.Lettieri,J.H.HaeniandD.G.Schlom,J.Vac.Sci.Technol.A20(4),Jul/Aug2002,pp.1332 1340 [11]V.Narayananetal,AppliedPhysicsletters,vol.81,No.22,2002,pp.41834185 [12]J.Kwoetal,AppliedPhysicsletters,vol.77,No.1,2000,pp.130132

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Chapter 3
Device Modeling on Floating Epitaxy SOI
3.1 Introduction
The advantages of Floating Epitaxy SOI are attractive from the perspective of producing thin silicon and buried oxide films and reducing the processing steps involves thereby easing manufacturing costs. However, it needs be investigated if the devices based on this novel substrate will meet the electrical device performance expectations as specified by the semiconductor roadmap. This chapter describes the device structure modeled on Floating EpitaxySOI,physicalparametersformaterialsusedandotherdevicedesignfeatures.

3.2 UTB Device Structure

Figure31showscrosssectionofafullydepletedUTBMOSFETbasedonFloatingEpitaxySOI. Silicon body is thin and rests on top of template oxide. The insulator underneath silicon body comprises of a thin layer of template oxide with SiO2 underneath. The device geometry and featuresarediscussedinfollowingsections.

3.2.1 Silicon Body

Siliconbodythicknessis7nmorless.ThechoiceofTSi<10nmisdictatedbysuppressionofshort channeleffectspointofviewasdiscussedinchapter1.Thesiliconchannelisdoped1E11cm3that is, it is virtually undoped. An advantage of SOI is that it permits device scaling with undoped silicon body. High channel doping results in mobility degradation (which results in reduced drive current) and dopant induced threshold voltage fluctuation. In order to avoid the above problems,itisbesttoscalewithundopedbodytoassmallgatelengthdimensionaspossible.

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Figure 3-1 UTB SOI MOSFET based on Floating Epitaxy SOI

3.2.2 Buried oxide

TheburiedoxidecomprisesofastackofthintemplateoxideoverSiO2.Thetemplatethicknessis varied between 2nm and 5nm in accordance with results from experimental growth. The template oxide is modeled with physical parameters corresponding to that of LaAlO3/SrTiO3 stack.SinceLaAlO3haspermittivity,k=26,andSrTiO3 hask=300,thepermittivityofstackwould vary between k=26 and k=300 depending upon the thickness of each layer. For modeling purposes, the template oxide is assumed to have a permittivity value of k=28. The bandgap is 5eV.TheSiO2underneathhasapermittivity,k=3.9.Thetotalinsulatorthicknessisatmost15nm thick.TheadvantageoffloatingEpitaxytechniqueisthatitiseasiertofabricatethinburiedoxide filmsthanthick.

3.2.3 Silicon Substrate

The silicon substrate is ptype and lowly doped 1E15cm3. A low substrate doping keeps body effectlowandalsominimizesparasiticsource/draintosubstratecapacitances.Ontheotherhand, ahighsubstratedopingisrequiredtopreventlatchupissues.Acompromisebetweenlowand highsubstratedopingisconsideredasanalternativetoreduceshortchanneleffectsinchapter6. The backgate bias is varied and its effect on device performance and suppression of SCEs is discussedindetailinchapter7.

15

3.2.4 Gatestack
Thegatestackcomprisesofmetal/highk.ThegateoxideisHfO2withpermittivity,k=24.5.The thickness is 5.54A which corresponds to an Equivalent Oxide Thickness (EOT) of 9A as projectedbysemiconductorroadmapforsub100nmdevices.Ahighkgatedielectricischosenas it allows the gate oxide to be physically thicker for the sane gate oxide capacitance thereby reducingthegateleakagecurrentduetoquantummechanicaltunneling.Ametal/highkstackis preferred over polySi/highk stack because of higher resulting channel mobility. Moreover, a metalgatesolvestheproblemofpolysilicondepletionassociatedwithpolySigateelectrode.A metal gate also allows for tuning the threshold voltage by gateworkfunction engineering. The workfunction is varied between 4.53eV and 5.45eV. For devices to scale with undoped silicon body, metal workfunction engineering is needed to set the right threshold voltage to suppress SCEs.

3.3 Modeling Setup

ThedevicestructureisbuiltusingMDRAWfromSynopsysTCAD.Analyticalprofilesareused tocreaten+source/drainjunctions.Thedopantforsource/draindiffusionisArsenicandjunction dopingis1E21cm3.Forchannelandsubstrate,constantdopingprofileandborondopantisused. A commercial device simulator, Sentaurus Device (version X2005.10) from Synopsys (formerly ISETCAD) is used to perform two dimensional device simulations based on driftdiffusion transportmechanism.Thedensitygradientmodelisincludedwhichtakesquantumeffectsinto consideration.ForIdVgsimulations,gatevoltageissweptfrom0Vto1V.Thedrainisbiasedata maximumorpowersupplyvoltageof1V.Themodelsformobilityusedforsimulationshavenot beencalibratedwithexperimentalresultsandareonlyasgoodastheTCADsoftwareclaims.

3.4 Conclusion
TheUTBSOIdevicestructurebasedonFloatingEpitaxySOIwasdescribed.Beforewesimulate devices of varying gate lengths and compare Ion, Ioff and Ion/Ioff ratio to ITRS projections, another device modeling feature incorporated for all simulations needs to be discussed. That featureistheadditionofbiaxialtensilestraintosiliconchannelinordertoimprovedrivecurrent. Nextchapterdiscussesstrainanditseffectondeviceperformanceindetail.

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Chapter 4
Strained Silicon and Device Performance
4.1 Need for strained silicon
As devices scale to nanoscale dimensions, alternatives in device design are being sought for to suppress the short channel effects. Most of these come at the cost of reduced transistor performance. According to Dennards principles for constant field scaling [1], the vertical dimensions(gateoxidethickness,junctiondepth,depletionwidth)mustscalealongwithlateral dimensions (channel length). Sub100 nm devices therefore operate under very high transverse electric field. Which is further expected to increase as scaling continues. The increase in the verticalelectricfieldseverelydegradessiliconchannelmobility.[2]Mobilitydegradationleadsto reductioninIonandunderminesthemuchbenefitsofscaling.Anotherissuewithshortchannel devices is the requirement for a shallow junction depth or reduced silicon body thickness. For 45nmtechnologynode,siliconbodyneedstobeasthinas10nmtosuppressDIBLthroughit.A thinnerbodyaddstotheseriesresistanceofsourceanddrainwhichhurtsIonandhence,device performance.[3]AreductioninIontranslatestoreducedoperatingspeed.Therefore,asscaling continues,innovationsindevicedesignarerequiredtokeepupthedeviceperformance.Inthis regard,strainedsiliconisanattractivefeaturewhichboostsdeviceperformance.Undersuitable conditions,straininsiliconchannelcausesanincreaseincarriermobilitywhichnotonlyresults in a larger Ion and speed but improves the otherwise unscalable subthreshold slope. Strain improvesbothelectronandholemobility.TheintegrationofstrainedsiliconmaterialsintotheIC manufacturing process is not very challenging. Most semiconductor companies like Intel and TexasInstrumentshaveswitchedtostrainedsiliconbaseddevices.Infact,atthepresentmoment, Silicon on Insulator (SOI) and Strained Silicon are the two key drivers of CMOS scaling. While the former suppresses short channel effects and reduces leakage currents by means of reduced parasiticcapacitances,thelatterenhancesdeviceperformance.

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4.2 Straining the Si Channel

Strain in silicon channel can be introduced either during processing known as processinduced strainorfromthebottombygrowingsiliconontopofacrystallinetemplatetypicallysiliconwith 20%ormoregermaniumcontent,knownassubstrateinducedstrain.

4.2.1 Process-induced strain

In processinduced strain, stresses are created by films and structures that surround the transistor. Stress can be induced during growth of oxides and silicides, etching and depositing layers, and introducing dopants into the silicon. Stress can be beneficial or detrimental to the nmos and pmos devices, depending on the stress pattern. In general, tensile stress improves electron mobility and compressive stress improves hole mobility, so tensile stress is used for nmos and compressive for pmos devices. Sources of stress include a nitride film on top of the device[4][5],theoxideinthenearbyshallowtrenchisolationstructure[6][7],silicidesandthe interlayer dielectric. For example, stress resulting from the standard shallowtrench isolation (STI) is known to enhance pmos performance by up to 20% while simultaneously degrading nmos performance by about 15%. [8] The use of Si1xGex in the source/drain creates significant uniaxial compression in the pmos channel whereas longitudinal uniaxial tensile strain is introducedintothenmoschannelbyasiliconnitridecappinglayerasshowninFigure41[5][9] [10].

4.2.2 Substrate-induced strain

Insubstrateinducedstrain,themosteffectivewaytointroducehightensilestraintothechannel is to epitaxially grow strained silicon on a relaxed silicon germanium (SiGe) layer. Bulk silicon and bulk germanium have different lattice constants, 5.43A and 5.65A respectively. The lattice constantinthealloySi1xGexisbetweenthatofSiandGeandvarieswithGeconcentrationasa(x) =aSi+(1x)aGe.IfathinsiliconfilmisgrownontopofSi1xGex,uptoacriticalthickness,Silattice follows the lattice of underlying substrate and gets stretched (or strained) in the plane of the interface.ThisresultsinbiaxialtensilestraininthechannelasshowninFigure42.[11]

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Figure 4-1 TEM micrograph of 45nm p-type and n-type MOS [10]

Figure 4-2 Formation of SiGe alloy and growth of strained Si on top [11]

Figure 4-3 Mobility enhancement ratio for strained Si n-MOSFETs [15]

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The first strained Si nMOSFETs were fabricated on relaxed Si1xGex substrates with 30% Ge contentandprovidedabout70%electronmobilityenhancementwithaverticaleffectiveelectric field up to 0.6 MV/cm [13]. At a lower gate bias, the current drive improvement over the unstrainedsiliconMOSFETsisaslargeas50%,whileatagatebiasof0.8V,thecurrentdriveofa strainedSideviceisabout35%higher[14].Figure43showsboththeexperimentaldataandthe theoreticalvaluesofthephononlimitedelectronmobilityenhancementversusthesubstrateGe content.[15]WiththeGecontentabove20%,themobilityenhancementfactorsaturatesnear1.8, inagreementwithcalculationsoftheimpactofstrainonthemobility.Experimentsalsoindicate that for electrons, the strain induced mobility enhancement factor is relatively constant with verticalelectricfield.

4.2.3 Uniaxial Vs Biaxial Strain

Unlike,processinducedstrainwhichisuniaxial,biaxialtensilestrainenhancesbothelectronand holemobilities.Thisisamajorreasonforcommercializationofwafersbasedonstrainedsilicon on top of Si1xGex layer despite process complexities and huge cost. This is opposed to process induced strain where both electron and hole mobilities respond oppositely to uniaxial tensile strain. However, it has been observed that for most PMOSFETs, biaxially stressed Si demonstrates nearzero hole mobility improvement at large vertical electric fields [11] where commercialMOSFETsoperate.Fischettietal.showedthatthelossinholemobilityenhancement at higher fields was due to reduction in the separation between the light hole and heavy hole bands(LHHH)[16].Basedontheexperimentaldata,itwasspeculatedthatthiswasduetothe confiningsurface potential operatingagainst the applied biaxial stressand trying to reducethe separation between the LH and HH bands. [16] On the other hand uniaxially stressed PMOSFETs, however, do not suffer from this performance problem. [10] The use of uniaxial stress for CMOS technology is not without its own complexities and so tradeoff exists as the strainedsilicontechnologyevolves.

4.3 Mobility Enhancement

The theory of mobility enhancement in strained silicon is still evolving. The most commonly acceptedexplanationisthatunderthebiaxialtensilestrain,thesixfolddegeneratevalleysinSi aresplitintotwogroups.Thegroupwiththelowerenergyistwofolddegenerate(labeledas2

20

in Figure 44), which is the primary contributor to carrier transport at low fields. The inplane effectivemassoftheelectronsoccupyingthesebandsisapproximatelyequaltotheSitransverse effectivemass(mt*=0.19m0).Ontheotherhand,theeffectivemassperpendiculartothetransport plane is equal to the longitudinal effective mass (ml* =0.92m0). The schematic representation of theenergyellipsesisshowninFigure44.Theenergyoftheconductionbandminimaofthefour valleysontheinplane<100>axesriseswithrespecttotheenergyofthetwovalleysonthe<100> axesperpendiculartotheplane[17],asshowninFigure45(a)[18].Theenergybetweenthetwo folddegenerateandthefourfolddegeneratevalleys,Estrain,isgivenbyEstrain=0.67xeV,where x is the Ge content of the relaxed Si1xGex substrate [19]. It should be noted that even in an unstrainedSiMOSinversionlayerthereisbandsplittingbetweenthesubbandenergiesinthe two and the fourfold valleys due to quantization in the inversion layer. In a strained Si MOS inversion layer, the band splitting of the conduction band Estrain is superimposed on this quantization,asschematicallyshowninFigure45(b)[18].Theelectronspopulatethelower2 valleys with lighter effective mass, which results in the reduction of the average conductivity effectivemass. TheothermechanismofmobilityenhancementproposedbyTakagietal.[18]isthesuppression of intervalley phonon scattering due to the energy splitting between the two fold and the four foldvalleys.Inunstrainedmaterial,thevalencebandmaximumiscomposedofthreebands:the degenerateheavyhole(HH)andlighthole(LH)bandsatk=0,andthesplitoff(SO)bandwhich isslightlylowerinenergy,asshowninFigure46[20].Thebiaxialstresscanberesolvedintoa hydrostatic and a uniaxial stress component. The hydrostatic stress equally shifts all three valencebands,whiletheuniaxialstressliftsthedegeneracybetweenLHandHHbandsbylifting theLHbandhigherthanHH.TheSObandisalsoloweredwithrespecttotheothertwobands. ThisleadstothepopulationofholesintheenergeticallyfavorableLHlikeband.Applicationof stressalsochangestheshapeofthebandsasshowninFigure46(b).Therefore,duetotheband deformation, the inplane transport mass becomes smaller and the interband scattering is also suppressed.Thustheholemobilityisimproved. The main difference between the effects on electron and hole mobilities is that the mobility of holes can be enhanced only at lower electric fields while the enhancement can be achieved at higherverticalelectricfieldsforelectrons.Fischettietal.showedthatthelossinholemobility

21

Figure 4-4 Strain induced conduction band splitting in silicon [11]

Figure 4-5 Energy alignment of the Si conduction band with and without the tensile strain [18]

Figure 4-6 Simplified hole valence band structure for longitudinal in plane direction [20]

22

enhancementathigherfieldswasduetoreductionintheseparationbetweenthelightholeand heavyholebands(LHHH)[16].

4.4 Strained Silicon-on-Insulator

StrainedSioninsulatorMOSFETscanbefabricatedfromstrainedsilicongrownonrelaxedSi1
x

Gex on insulator (SGOI) substrates [20]. SGOI can be achieved via several approaches such as

etchback and smartcut processes [20], SIMOX technology [21] and Ge condensation techniques. [22] The presence of the SiGe layer in strainedsilicon substrate leads to several challenges related to materials and integration, such as a high density of defects in strained silicon on relaxed SiGe induced by the strain relaxation in SiGe and a substantial difference in doping diffusion property in SiGe. (Boron diffusion is retarded, whereas arsenic diffusion is enhancedascomparedwiththediffusioninsilicon.)Suchchallengesrequireadditionaleffortsin junctionengineeringtocontrolSCEsandtosetthedevicethresholdvoltagetothedesiredvalue. Substantial device selfheating is also observed in strained silicon/SiGe devices because of the lowerthermalconductivityinSiGe.Recently,Rimetal.[23]demonstratedtransistorsusingultra thinstrainedsilicondirectlyoninsulator(SSDOI)structuresthateliminatetheSiGelayerbefore transistor fabrication, thereby providing higher mobility while mitigating the SiGeinduced materialandprocessintegrationproblems.AnSSDOIstructureisfabricatedbyalayertransfer orwaferbondingtechnique.First,anultrathinlayerofstrainedsiliconisformedepitaxiallyon arelaxedSiGelayer,andanoxidelayerisformedontop.Afterhydrogenisimplantedintothe SiGe layer, the wafer is flipped and bonded to a handle substrate. A hightemperature process splitsawaymostoftheoriginalwaferandleavesthestrainedsiliconandSiGelayersontopof the oxide layer. The SiGe is then selectively removed and transistors are fabricated on the remaining ultra thin strainedsilicon.Afabricated SSDOI devicestructureisshown inFig.3 A. Bothelectronandholemobilityenhancementhavebeenobserved,whichindicatesthatstrainis retainedafterthedeviceprocessingstepshavebeencompleted[23].

4.5 Modeling Strain in this work

The crystalline oxide used as template for growing silicon on top is closely lattice matched to silicon. While LaAlO3 has a lattice parameter of 3.8A, SrTiO3 has lattice parameter of 3.9A as opposedto5.43Aofsilicon.ThereisevidencethatwhenSrTiO3andLaAlO3aregrownonSi,

23

thentheSrTiO3orLaAlO3cuberotates45withrespecttotheSicube,sotheeffectivelattice mismatchwithSiissmall.Thisisbecausetheeffectivelatticeparameterwillnowbesqrt(2)times theactualvalue.ForthisreasonwhenSiisgrownontopofSrTiO3itwillseealatticeparameter of5.5Awhichislargerthan5.43Aandthereforeifthetemplateisrelaxed,siliconwillgettensile strained.Thestraincomponentwouldbesimilartoonethatresultswhensiliconisgrownontop of relaxed SiGe. Strain in this novel substrate will be advantageous over that in SiGe based substratessincemuchoftheproblemsassociatedwithSiGebufferlayerwillbeeliminated. Thesiliconbodyisthereforemodeledtobeunderbiaxialtensilestrain.Modelingisdoneusing SentaurusDevicefromSynopsys.AmaterialcalledStrainedSiliconisusedforthesiliconbody andacorrespondingparameterfilestrainedsilicon.parisused.Theamountofstrainaddedto siliconchannelissameasthatwouldresultinsilicongrownoverSiGealloywith20%Gecontent. Thestrainisassumedtobeconstantirrespectiveofthetemplatelayerthickness.Alsothestrain hasnotbeencalibratedwithexperimentalresults.Thestraindependentmobilitymodelusedis only as good as claimed by the TCAD software. The device simulations therefore will characterizeastrainedsilicononinsulatordevice.Inorder,toseetheeffectofmodeledstrainon deviceperformance,simulationsareperformedanddiscussedinnextsection.

4.6 Simulation Results

Inthissection,thestrainmodeledinthesiliconchannelischaracterized.Inordertoestablishthe effect of strain on the device performance, simulations are done with and without strain in the siliconchannelandtheprosandconsofaddingstrainareanalyzed.

4.6.1 Simulation Setup

The device structure is same as discussed in Chapter 3. The silicon body is 7nm thick and undoped.Thegatestackconsistsofmetalgate/HfO2.Themetalworkfunctionis4.53eV.EOTfor gate oxide is 9A. The template is 5nm thick with a dielectric constant of k=28. The SiO2 underneathis15nmthick.Thesourceanddrainaren+dopedwithconcentration1E20cm3.The substrateisptypeandlowlydoped1E15cm3.Thesourceandsubstratearetiedtoground.Drain isconnectedtosupplyvoltageof1V.

24

4.6.2 Strain and Drive Current

Figure 47 shows the IdVg curves for a 25nm gatelength device. Onstate current, Ion, for a device with strained channel is 1.87mA/um compared to 1.69mA/um for the device without strain in channel. At this gate length, strain results in 11% increase in drive current. Figure 48 shows the IdVg curves for a 15nm gatelength device. Onstate current, Ion, for a device with strainedchannelis3.16mA/umcomparedto2.59mA/umforthedevicewithoutstraininchannel. At this gate length, strain results in 22% increase in drive current. Figure 49a plots the drive current for different channel lengths. Since, Ion is inversely proportional to gate length; it increasesaschannellengthdecreases.Thebenefitofaddingstrainisvisibleateverygatelength asahighervalueofIon.

4.6.2 Strain and Leakage Current

FromFigure47andFigure48,itcanbeseenthatoffstateleakagecurrentdefinedasthedrain currentatzerobiasisalsosignificantlylargerforthedevicewithchannelunderstrain.For25nm device, while Ioff for device with strained silicon is 1.03E4A/um, it is 5.06E5A/um for device without strained channel. For 15nm gate length, Ioff is 8.97E4A/um for device with strained silicon and 5.73E4A/um for device without strained silicon. Thus, the enhancement in drive currentwithstraininchannelcomesatthecostofincreasedleakagecurrent.Figure49bplotsthe Ioffversusgatelength.Aschannellengthdecreases,Ioffincreasesbecauseofincreasedproximity of source and drain and added short channel effects such as draininduced barrier lowering (DIBL).DevicewithstraininsiliconchannelresultsinalargerIoffateverygatelengthcompared todevicewithoutstrainedchannel.

4.6.2 Strain and Threshold Voltage

TheincreaseintheIoffbyaddingstraintosiliconchannelcanbeexplainedbyadecreaseinthe threshold voltage. Figure 410a plots the saturation threshold voltage of the device with and without strain in silicon channel versus the gate length. As can be seen, strain results in a decrease in threshold voltage. Since Ioff varies exponentially with threshold voltage, Ioff increasesaschannellengthdecreases.ThesmallerVtofdeviceswithstrainisamajorconcernfor device design. Since, it requires more stringent conditions for to set the threshold voltages to a leveldesiredandtherebymitigateshortchanneleffects.

25

a)

b)

Figure 4-7 Id-Vg curves for Lg =25nm with and without strain in Si channel a) linear b) log scale

a)

b)

Figure 4-8 Id-Vg curves for Lg =15nm with and without strain in Si channel a) linear b) log scale

26

ThethresholdvoltageislowerforstrainedSiduetoitssmallerbandgap(commonlyassumed), electronaffinitychangeandbandoffsetbetweenSSandSiGe.Thenarrowingofbandgapisgiven by, Eg(SS)=Eg(Si)Eg(SS)=0.4x(eV)[24][25] TheshiftinVtofaNMOSdeviceduetostrainisgivenas[26], Vt(SS)=Ec(m1)Eg(SS)+(m1)(kT/q)ln(NvSi/NvSS) whereEc=SiSSrepresentsconductionbandloweringintheSSandmisthebodyeffect coefficientwithvaluebetween1.3and1.4fornanoscaledevices

4.6.3 Strain and Drain-Induced barrier Lowering

Figure 410b plots draininduced barrier lowering (DIBL) versus the channel length. DIBL is measuredasthedifferenceinmeasuredthresholdvoltageatdrainbiasof0.1Vand1V.Ascanbe seen, strain doesnt affect DIBL. Even though strain lowers the threshold voltage, it doesnt impactDIBL.Ithasbeenshownin[27]thatstraindoesntworsentheshortchanneleffects.What causesalowerDIBLinstrainedSionSiGesubstratesisthedifferenceinpermittivityofsilicon andSiGe.However,ifSiGeisassumedtohavesamepermittivityasthatofSi,thetwodevices with and without strain would result in same DIBL which is inline with what Figure 410b suggests.

4.7 Conclusion
From performance perspective, strained silicon channel is advantageous as it results in an increased drive current. However, because of band splitting that occurs, threshold voltage is lowered. This results in an increase in the offstate leakage current. Threshold voltage is an important device parameter and its control becomes more critical for strained silicon based devices. Generally an increase in threshold voltage is needed to bring the down the offstate currenttoaleveldesired.Since,Vtofstrainedsilicondevicesislower,morestringentcontrolof Vt is required. It has been shown that strain doesnt affect DIBL. However, when it comes to achievinganITRSprojectedleakagecurrentvalue;alowerVtdoesposeagreaterdevicedesign challenge.

27

Ion Vs Channel Length 6

Ioff Vs Channel Length 1.0E-02

1.0E-04
4 Ion (mA/um)

strained Si 3

Ioff (A/um )

unstrained Si

1.0E-06

strained Si unstrained Si

1.0E-08
1

0 10nm 15nm 25nm 30nm 45nm 60nm Channel Length

1.0E-10 10nm 15nm 25nm 30nm 45nm 60nm Channel Length

a) b) Figure 4-9 a) Ion and b) Ioff versus channel length for device with and without strain in Si channel

Threshold Voltage Roll Of Trend 0.6

DIBL Effect

0.35 0.30 0.25 Vt s hift (V)

unstrained Si

0.5 Threshold Voltage (V)

0.4 unstrained Si strained Si 0.2

0.20 0.15 0.10 0.05 0.00

strained Si

0.3

0.1

0 0 20 40 Channel length (nm) 60 80

10

100 Channel Length (nm)

1000

a) b) Figure 4-10 a) Threshold voltage and b) Drain induced barrier lowering (DIBL) versus channel length for device with and without strain in Si channel

28

4.8 References

[1] H.S. Wong, D. Frank, and P. Solomon, Device design considerations for doublegate, groundplane, and singlegated ultrathin SOI MOSFETs at the 25 nm channel length generation,Proc.Int.ElectronDevicesMeeting,pp.407,1998. [2] L. Ge, J. G. Fossum, and B. Liu, Physical compact modeling and analyses of velocity overshootinextremelyscaledCMOSdevicesandcircuits,IEEETrans.ElectronDevices,vol.48, pp.20742080,Sept.2001. [3] R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. R. LeBlanc, Design of ionimplanted MOSFETs with very small physical dimensions, IEEE J. SolidState Circuits,vol.SC9,pp.256,1974. [4] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki,T.Saitoch,andT.Horiuchi,Mechanicalstresseffectofetchstopnitrideanditsimpact ondeepsubmicrontransistordesign,inIEDMTech.Dig.,2000,pp.247250. [5]A.Shimizu,K.Hachimin,N.Ohki,H.Ohta,M.Koguchi,Y.Nonaka,H.Sato,andF.Ootsuka, Localmechanicalstresscontrol(LMC):AnewtechniqueforCMOS,inIEDMTech.Dig.,2001, pp.19.4.119.4.4 [6]R.Bianchietal.,Accuratemodelingoftrenchisolationinducedmechanicalstresseffectson MOSFETelectricalperformance,IEDMTech.Dig.,2003,pp.117120 [7]Morozetal.,TheImpactofLayoutonStressEnhancedTransistorPerformance,Int.Conf. SISPAD,2005,pp.143146 [8]Morozetal.,Analyzingstrainedsiliconoptionsforstressengineeringtransistors,SolidState Technology,Jul2004,Vol.47Issue7,p4952 [9] T. Ghani, et al., A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nmGateLengthStrainedSiliconCMOSTransistors,Proc.IEDM,pp.978980,2003. [10] S.E. Thompson, et al., A Logic Nanotechnology Featuring Strainedsilicon, IEEE Electron Dev.Lett.,Vol.25,No.4,pp.191193,2004. [11] K. K. Rim, J. L. Hoyt, and J. F. Gibbons, Fabrication and analysis of deep submicron strainedSiNMOSFETs,IEEETransactionsonElectronDevices,vol.47,pp.14061415,2000. [12]L.Geppert,TheAmazingVanishingTransistorAct,IEEESpectrum,pp.2833,vol.39,no. 10,2002. [13]J.Welser,J.L.Hoyt,andJ.F.Gibbons,NMOSandPMOStransistorsfabricatedinstrained silicon/relaxedsilicongermaniumstructures,ElectronDevicesMeeting,1992.TechnicalDigest., International [14]H.S.P.Wong,Beyondtheconventionaltransistor,IBMJournalofResearchandDevelopment, vol.46,pp.133168,2002 [15] J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis,StrainedsiliconMOSFETtechnology,presentedatElectronDevicesMeeting,2002. IEDM02.Digest.International,2002. [16] M. V. Fischetti, Z. Ren, P. M. Solomon, M. Yang, and K. Rim, Sixband k center dot p calculation of the hole mobility in silicon inversion layers: Dependence on surface orientation, strain,andsiliconthickness,JournalofAppliedPhysics,vol.94,pp.10791095,2003 [17]R.People,PhysicsandApplicationsofGexSi1X/SiStrainedLayerHeterostructures,IEEE JournalofQuantumElectronics,vol.22,pp.16961710,1986. [18]S.I.Takagi,J.L.Hoyt,J.J.Welser,andJ.F.Gibbons,Comparativestudyofphononlimited mobilityoftwodimensionalelectronsinstrainedandunstrainedSimetaloxidesemiconductor fieldeffecttransistors,JournalofAppliedPhysics,vol.80,pp.15671577,1996.

29

[19] T. Vogelsang and K. R. Hofmann, ElectronTransport in Strained Si Layers on Si1XGex Substrates,AppliedPhysicsLetters,vol.63,pp.186188,1993. [20] S. Takagi, N. Sugiyama, T. Mizuno, T. Tezuka, and A. Kurobe, Device structure and electrical characteristics of strainedSioninsulator (strainedSOI) MOSFETs, Materials Science andEngineeringBSolidStateMaterialsforAdvancedTechnology,vol.89,pp.426434,2002. [21]D.Hisamoto,T.Kaga,Y.Kawarnoto,E.Takeda,IEDMTech.Dig.1989. [22]X.Huangetal.,IEDMTech.Dig.1999,67(1999) [23]K.Rimetal.,IEDMTech.Dig.2003,49,(2003). [24] G. Armstrong and C.Maiti, StrainedSi channel heterojunction PMOSFETs, SolidState Electron.,vol.42,pp.487498,Apr.1998. [25] T. Numata et al., Control of threshold voltage and short channel effects in ultrathin strainedSOICMOS,inProc.IEEEInt.SOIConf.,Sep.2003,pp.119121. [26]W.ZhangandJ.Fossum,OnthethresholdvoltageofstrainedSiSi1xGexMOSFETs,IEEE Trans.Electron.Devices,vol.52,no.2,pp.263268,2005.

30

Chapter 5
Initial Device Design
5.1 Introduction
ThischapterdescribestheresultsofinitialsimulationofdevicebasedonFloatingEpitaxySOIor epitaxial buried oxide. The goal of the simulation is to evaluate the device performance and to knowhowfarofftheperformanceisfromcorrespondingITRSprojection,fordifferentchannel lengths. Also it is desirable to know how the device performs compared to the standard SOI device. The chapter also helps tounderstand the effect of template layer thicknessand channel lengthondeviceperformance.Accordingly,deviceparameterswouldberemodeledtosuppress shortchanneleffectsandachieveITRSprojectedvalues.

5.2 Simulation Setup

Figure51showsthedevicebasedontheepitaxialburiedoxidewhichissimulated.Thetemplate thicknessisvariedfrom5nmdownto2nm.Thepermittivityoftemplateisassumedtobe28.0. ThethicknessofSiO2underneaththetemplateissuchthatthetotalinsulatorthicknessisconstant at15nm.Since,theshortchanneleffectsareafunctionofburiedoxidethickness,itsbesttokeep itconstantsothattheeffectoftemplatematerialandthicknessbecomesclear.Thesubstrateisp typeandlowlydopedwithconcentration1E15cm3.Thesiliconbodyis7nmthickandundoped. Thegatestackcomprisesofmetal/HfO2.MetalWorkfunctionissetat4.53eV.Thesiliconchannel isassumedtobeunderbiaxialtensilestrainasdiscussedinChapter4.Forsimulation,thesource andsubstrateareconnectedtoground.Drainisbiasedat1V.Thegatevoltageissweptfrom0V to1Vanddeviceparameterssuchasthresholdvoltage,offstatecurrentandonstatecurrentare extracted from IdVg plots. The channel length is varied from 60nm down to 10nm. The performance of the epitaxial oxide based device (epiSOI) at every channel length is compared withthatofstandardSOIdeviceinFigure52.ThestandardSOIdevicehasauniform15nmthick SiO2asburiedoxide.Also,thesiliconbodyisassumedtobeundernoaddedbiaxialtensile

31

Figure 5-1 Epitaxial-oxide based SOI device (eSOI)

Figure 5-2 Standard SOI device or the Core device

32

strain.Otherthanthis,thedevicearchitectureisthesame.ThedeviceinFigure52isreferredto ascoredevice.

5.3 Simulation Results

Figure 53 through Figure 58 plot the threshold voltage, offstate current (Ioff0 and onstate current (Ion) as a function of template thickness for a range of channel length from 60nm to 10nm.Theresultsarediscussedinthefollowingsections.

5.2.1 Template Thickness Effect

Theeffectoftemplatethicknessondeviceperformanceissummarizedbelow. 1. For all channel lengths, the threshold voltage increases as template thickness decreases. As templatethicknessdecreases,thethicknessofSiO2beneathincreases.Thisisbecausetotalburied oxide (BOX) thickness is a constant 15nm. Because SiO2 now comprises of a greater fraction of BOX thickness the effective dielectric constant of the BOX is lowered. A lower permittivity (lowerk) BOX reduces the coupling of field lines from drain to channel via the BOX, thereby, reducingtheshortchanneleffects.Consequentlythresholdvoltageishigher.Figure59shows the potential contours in the buried oxide of a 30nm and 10nm epiSOI device with 5nm thick template. As can be seen, the equipotential contours in the BOX are not parallel to body/BOX interface and couple drain to channel. This bring back interface between the body and BOX under conduction worsening DIBL. Reducing the BOX permittivity reduces this coupling and improvesshortchanneleffects.MorewillbediscussedonthisinChapter8. 2.Forallchannellengths,theoffstatecurrentdecreasesastemplateismadethinner.Thisisdue to reduced short channel effects mainly DIBL through BOX and resulting increase in threshold voltage. 3. The onstate current decreases as template thickness decreases. This is because a larger Vtt resultsinsmallerIonsinceIondependsonVtas(VgsVt)2

33

5nm 1.0E-08
epi-SOI Threshold V oltage (V ) 0.56 Core Vt = 0.551

4nm

3nm

2nm

0.97

Template Thickness (nm)

0.94 Io n (m A ) epi-SOI 0.91 Core Ion = 0.88mA

0.53

Io ff (A/u m )

1.0E-09

1.0E-10 epi-SOI
0.5 5nm 4nm 3nm 2nm Template Thickness (nm)

0.88

Core Ioff = 7.48E-11A 1.0E-11

0.85 5nm 4nm 3nm 2nm Template Thickness (nm)

Figure 5-3 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for core and new device

5nm
0.55 Threshold V oltage (V )

4nm

3nm

2nm
1.19

1.0E-06 Template Thickness (nm)

0.53 epi-SOI 0.51 Core Vt=0.526

1.0E-07 Io ff (A/u m )
Io n (m A )

1.15 epi-SOI 1.11 Core Ion = 1.05mA

1.0E-08

epi-SOI Core Ioff = 5.3E-10A

0.49

1.0E-09

1.07

0.47 5nm 4nm 3nm 2nm

1.0E-10

1.03 5nm 4nm 3nm 2nm Template Thickness (nm)

Template Thickness (nm)

Figure 5-4 Lg = 45nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for core and new device

34

5nm
0.5

4nm

3nm

2nm

1.8 1.7 1.6 epi-SOI Core Ion = 1.34mA Io n (m A )

1.0E-03 Template Thickness (nm) 1.0E-04 Io ff (A /u m )

Th resho ld V o ltage (V )

0.45

epi-SOI Core Vt=0.474

1.0E-05 1.0E-06 1.0E-07 epi-SOI Core Ioff = 9.5E-8A

1.5 1.4 1.3 1.2

5nm 4nm 3nm 2nm

0.4

0.35 5nm 4nm 3nm Template Thickness (nm) 2nm

1.0E-08

Template Thickness (nm)

Figure 5-5 Lg = 30nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for core and new device

5nm
0.49 T h resh o ld V o ltag e (V )

4nm

3nm

2nm

2 1.9 1.8

1.0E-03 Template Thickness (nm)

epi-SOI Core Vt=0.43 0.33

Io ff (A/u m )

Io n (m A )

0.41

1.0E-04 epi-SOI 1.0E-05 Core Ioff = 1.87uA

1.7 1.6 1.5

epi-SOI Core Ion = 1.51mA

0.25 5nm 4nm 3nm 2nm Template Thickness (nm)

1.0E-06

1.4 5nm 4nm 3nm 2nm Template Thickness (nm)

Figure 5-6 Lg = 25nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for core and new device

35

5nm 1.0E-02

4nm

3nm

2nm
3.2

Template Thickness (nm) epi-SOI

Io n (m A )

epi-SOI 2.8 Core Ion = 2.3mA

Io ff (A /u m )

Core Ioff = 0.27mA 1.0E-03

2.4

1.0E-04

5nm

4nm 3nm Template Thickness (nm)

2nm

Figure 5-7 Lg = 15nm a) Ioff c) Ion versus Template Thickness for core and new device
5nm 1.0E-02 Template Thickness (nm) 4nm 3nm 2nm

5.7

5 I o n (m A )
Io ff (m A /u m )

epi-SOI 4.3 Core Ion = 3.71mA

1.0E-03

epi-SOI Core Ioff = 1.24mA

3.6

2.9
1.0E-04

5nm

4nm

3nm

2nm

Template Thickness (nm)

Figure 5-8 Lg = 10nm a) Ioff c) Ion versus Template Thickness for core and new device

36

Figure 5-9a Equipotential Contours in 30nm epi-SOI device with 5nm thick template

Figure 5-9b Equipotential Contours in 10nm epi-SOI device with 5nm thick template

37

4.Foranytemplatethickness,thecoredeviceresultsinalargerthresholdvoltageandthereforeasmaller offstatecurrentandalargeronstatecurrent.SincethecoredevicehasSiO22asburiedoxide,thelower permittivityofSiO2resultsinlesserDIBLthroughBoxandreducedshortchanneleffectsimplyahigher thresholdvoltage.TheeffectofBOXpermittivitywillbediscussedinChapter8. Figure 510a plots threshold voltage versus template thickness for a whole range of channel lengths. Figure 510b and Figure 510c do the same for Ioff and Ion respectively. Some key observations from theseplotsare, 1.Vtincreasesalmostlinearly,foranychannellength,astemplateismadethinner.TheincreaseinVtas templatethicknessdecreasesfrom5nmto2nm,ismoreforshortchanneldevices(Lg=25nmand30nm) andlesserforlongerdevices(Lg=45nmand60nm) 2. For a device with same template thickness, Vt is more for long channel devices and falls as channel lengthdecreases. Foradevicewithsametemplatethickness,say5nm,thedecreaseinVtasLgreduces from 60nm to 45nm is much smaller than the decrease in Vt as channel length reduces by the same amount,15nmfrom45nmto30nm.Thisisattributedtothethresholdvoltagerolloffeffect. 3. The decrease in Ioff with decreasing template thickness from 5nm to2nm, is more for long channel devices (Lg = 45nm and 60nm) and lesser for shorter devices (Lg=25nm and 30nm). This is because Vt fallsrapidlyforshorterdevicesthereforeIoffincreaseslessrapidly. ThefactthatIoffisnearlyconstant for all template thicknesses for 10nm and 15nm channel length devices shows that Vt changes more rapidlywithtemplatethicknessfortheselengths. 4. For a device with same template thickness, say 5nm, Ioff increases as channel length reduces. The increase per 5nm decrease in channel length is larger for longer channel devices and smaller for short channeldevices.SinceVtfallmorerapidlyforshortchannellengthdevices,Ioffincreasesslowlyforshort channel devices and rapidly for longer channel devices. For this reason, the increase in Ioff as channel lengthdecreasesfrom30nmto25nmismoreascomparedtotheincreaseaschannellengthdecreasesfall from15nmto10nm.

38

0.55

5nm 1.0E+00

4nm

3nm

2nm

0.5

1.0E-01 1.0E-02

) Threshold Voltage (V

0.45 Lg = 60nm 0.4 Lg = 45nm Lg = 30nm Lg = 25nm 0.35

1.0E-03

Ioff (A/um )

Lg = 60nm 1.0E-04 1.0E-05 1.0E-06 1.0E-07 Lg = 45nm Lg = 30nm Lg = 25nm Lg = 15nm Lg = 10nm

0.3

1.0E-08 1.0E-09

0.25 5nm 4nm 3nm 2nm

1.0E-10 Template Thickness (nm)

Template Thickness

a)
6

b)

4 Lg = 60nm

Ion (mA)

Lg = 45nm 3 Lg = 30nm Lg = 25nm Lg = 15nm Lg = 10nm 2

0 5nm 4nm 3nm 2nm

Template Thickness (nm)

c) Figure 5-10 a) Threshold Voltage b) Off-state current and c) on-state current versus Template Thickness

39

5.2.2 Channel Length Effect

Figure 511 plots the variation of threshold voltage, offstate current and on state current respectively with channel length. Threshold voltage falls more rapidly at short channel lengths becauseofVtrolloffeffect.ThedifferencebetweenVtfordifferenttemplatethicknessesbecomes moreforshortchanneldevices.Forthisreason,theoffstatecurrentdoesntchangemuchwith template thickness for 10n and 15nm devices. Both Ioff and Ion increase as channel length decreases.ThechangeinIonwithchangeintemplatethicknessisverysmall.ThechangeinIoff withchangeintemplatethicknessbecomessmallonlyatsmallchannellengths.

5.2.3 ITRS and Device Performance

Figure 512 plots Ioff and Ion for different channel lengths and compares it with ITRS High PerformanceLogic projected values. The parameteron xaxis is the device physicalgate length and for long channel devices older versions of ITRS were used to obtain the performance projections.TheultimategoalistoachieveITRSprojectionsforallchannellengthsandengineer thedeviceaccordingly.InsteadofIonorIoff,Ion/Ioffratioisabettermetricforevaluatingdevice performance. The Ion/Ioff ratio is plotted in Figure 513s. The key observation is that for 60nm andlongerchannellengthdevices,theepitaxialoxidebaseddeviceunderinvestigationmeetsthe ITRS requirements for Ion/Ioff ratio irrespective of the template thickness. For 45nm channel length,ITRSprojectionsaremetexceptfor5nmthicktemplate.However,aschannellengthscales below 45nm, device performance is off from ITRS projection by a big margin for all template thicknesses. The device below 45nm therefore, needs to be reengineered to meet ITRS projections. 5.4

Conclusion and Next

AthinnertemplateyieldsasmallerIoffandisbettersuitedtomeetITRSrequirements.However, for very small channel lengths, 15nm and below, the effect of template thickness becomes less and performance for different template thicknesses becomes comparable. The epitaxialoxide baseddeviceperformsworsethanstandardSOIdevicebecauseofalargerthicknessandsmaller permittivityofSiO2.ThedeviceunderinvestigationmeetstheITRSprojectionsfor60nmchannel

40

0.55
10nm 1.0E-02 15nm 25nm 30nm 45nm 60nm

0.45

1.0E-03

Threshold Voltage (V)

1.0E-04

0.35
1.0E-05
5nm 4nm

Io (A ff )

0.25

1.0E-06

3nm 2nm Core Device

1.0E-07

5nm 4nm 3nm

0.15

1.0E-08

2nm Core Device

1.0E-09

0.05 15nm 25nm 30nm 45nm 60nm

1.0E-10

Channel Length (nm)

Channel Length (nm)

a)b)
6

5nm 4nm

Ion (m A)

3nm

2nm Core Device

0 10nm 15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

c) Figure 5-11 a) Threshold Voltage b) Off-state current and c) on-state current versus Channel Length

41

10nm 1.0E-02

15nm

25nm

30nm

45nm

60nm

1.0E-03

1.0E-04

5nm 4nm 3nm 2nm ITRS HP

4 5nm Ion (m ) A 4nm 3 3nm 2nm ITRS HP

1.0E-05 Ioff (A/um)

1.0E-06

1.0E-07

1.0E-08

1
1.0E-09

0
1.0E-10 Channel Length (nm)

10nm

15nm

25nm

30nm

45nm

60nm

Channel Length (nm)

Figure 5-12 a) Ioff b) Ion comparison with ITRS High Performance Logic Projections

1.0E+07

1.0E+06

1.0E+05

Ion/Ioff

1.0E+04

1.0E+03

5nm 4nm 3nm 2nm ITRS HP

1.0E+02

1.0E+01

1.0E+00 10nm 15nm 25nm 30nm 45nm 60nm Channel Length (nm)

Figure 5-13 Comparison of device Ion/Ioff ratio and ITRS High Performance Logic projections

42

lengthdevicehoweverbelow45nmregime;thereisabigoffsetfromprojectionsforanytemplate thickness.Thus,devicedesignparameterssuchassiliconbodythickness,buriedoxidethickness, gateworkfunctionandothersmustbereengineeredtosuppressshortchanneleffectsandmeet ITRS requirements for sub45nm channel length devices. In the following chapters, device alterationstoreduceshortchanneleffectswillbeinvestigated.

43

Chapter 6
Ground Plane Concept
6.1 Introduction
FrompreviouschapterwehaveseenthatforSOIdevicetoscalebelow45nmgatelength,short channel effects need to be suppressed. The ultimate SOI device would be a doublegate or multiplegatedevice.Howeverbecauseoftheprocessingissuesinvolved,thesedevicesarehard to fabricate. A groundplane device is a compromise between the singlegate and doublegate deviceandeffectiveinsuppressingshortchanneleffects.Thischapterdescribestheconceptand advantagesofgroundplanedevice.Thegroundplanedeviceissimulatedforthewholerangeof channel length and reduction in offstate leakage current and improvement in Ion/Ioff ratios is highlighted.

6.2 Ground Plane Concept

A major cause of short channel effectsin sub100nm fully depleted SOI devices is attributed to thefringingelectricfieldlinesintheburiedoxideandsubstrate(Figure61).[1]Thebiasingof draincausesfieldlinesemanatingfromdrain.Whilethechannelisshieldedfromthesefieldlines at the top by the gate electrode, the field lines penetrate laterally through the body and from underneath through the buried oxide and underlying substrate. The field lines through the buriedoxideandsubstratecouplethedraintobodypotentialandcauseparasiticbackchannel conduction. There occurs a peak in the potential at body/BOX interface and a potential rise in substrateaswell.[1][2]Thebackchannelisdrivenfromdepletiontoweakinversionanddueto interfacecouplingthethresholdvoltageislowered.Thisdegradessubthresholdslopeandresults in severe draininduced barrier lowering. According to [2] the effect is referred to as drain induced virtual substrate biasing where drain acts a positively biased backgate. Figure 62 showsfringingfieldlinesintheburiedoxide,whicharehighlydeformedandnotparalleltothe body/BOXinterface.Itisindicativeofthefactthatthebackchannelpotentialisgovernedbythe

44

Figure 6-1 Schematic of fringing fields in SOI device [3]

Figure 6-2 Electrostatic Potential Contours in the BOX and substrate of a SOI device [4]

Figure 6-3 Ground-Plane structures [1] [3] [6]

45

drain rather than the substrate. In other words, the 2D drain/source to body capacitances dominatesoverthe1Dbodysubstratecapacitance.Thedraininfluenceonbodypotentialcanbe reduced by BOX thickness scaling or reducing the BOX permittivity. Both these effects will be discussedinchapter8howevertheeffectofbothofthemisenhancedbyemployingaground plane. Groundplanehasbeenprovedeffectiveinsuppressingshortchanneleffects[4][5].Itreferstoa conductingsurfacebeneaththeburiedoxide.Typicallyasinglep+implantlocatedintheburied oxidealignedwiththegateoxideortwop+implantslocatedunderthesourceanddrainserveas groundplanestructures(Figure63).Thedopingingroundplaneelectrodeisatleast1E18cm3. Ahighlyconductingsurfaceactsasanelectricfieldstopandshieldsthefringingfieldlinesfrom drainfromcouplingtochannel.Whenthesubstrateislowlydoped,depletionregioninsubstrate islargeandaddstotheeffectiveburiedoxidethickness.Employingagroundplanesuppresses substratedepletionandpreventsdraininducedconductionofbackchannel.

6.3 Ground Plane Vs Classical SOI

Figure64showspotentialcontoursinfullydepletedSOIdeviceclassicalSOIandgroundplane SOI device. The ground plane is located under the gate and results in reduced electric field penetration in the buried oxide and sunstrate. Figure 65 shows the electrostatic potential variation along the vertical axis for 80nm SOI device with 20nm thick silicon film with and withoutgroundplane.ThepeakinpotentialinBOXandraiseinpotentialinsubstrateoccursdue to fringing fields from drain. The peak is lowered and substrate potential is reduced by employing a ground plane. Figure 65b suggests that a combination of ground plane and thin buried oxide completely suppresses the peak in potential and almost completely suppresses DIBL through BOX. The first groundplane FDSOI [7] was fabricated on a 140nm long device with150nmthickBOXand80nmthicksiliconfilm.Thesubstrateconcentrationwas1E15cm3and ground plane was doped 5E18cm3. The key processing steps are shown in Figure 66. After formingtheshallowtrenchisolationadummynitridegateisformedandPSGisdeposited.CMP isusedtoformaninverseprintofthegate.Thenitrideisetchedandboronisimplantedtoform the selfaligned ground plane. The nitride is removed and polysilicon deposition and CMP are

46

usedtoformthegate.ThePSGisremovedfinallytoallowforsourceanddrainformation.Figure 67

a)

b)

Figure 6-4 Equipotential contours in a 0.1mm long device with Vg = 0V and Vd = 1.5V. a) Device without ground plane b) Device with ground plane in substrate under the gate [3]

47

Figure 6-5 Vertical potential profile in the middle of a 80-nm-long SOI MOSFET with conventional and GP configuration. BOX thickness is (a) 380 nm, (b) 50 nm. Si Film thickness is 20 nm [4]

Figure 6-6 Key processing steps: A: Nitride patterning, B: PSG Deposition and CMP, C: Nitride etch and Boron implant, D: Gate-Oxide growth, polysilicon deposition and CMP [7]

48

compares threshold voltage rolloff and DIBL trend for the device with and without ground planeimplant.Figure67showsthethresholdvoltagerolloffandDIBLbehaviorfordevicewith and without ground plane implant. Significant reduction in DIBL is observed in case of the groundplanedevice.

6.4 Ground Plane Simulation Setup

Figure67showsthedevicestructurewithgroundplaneimplantintheBOXunderthegate.The device parametersare thesameas in last chapter. Silicon body is7nm thickand undoped.The frontgateEOTis9A.GatestackconsistsofMetal/HfO2.Thetotalburiedoxidethicknessis15nm and template thickness is varied. The groundplane is p+ doped to concentration 5E18cm3. Substrate is lowly doped 1E15cm3 and connected to ground. IdVg simulations are done with drainbiasedat1V.

6.5 Simulation Results

Figure 68 plots vertical electrostatic potential across the center of silicon body for 25nm gate lengthdevicewithandwithoutthegroundplane.Figure69plotsthepotentialcontoursinBox andsubstrate.Figure610throughFigure615plotthethresholdvoltage,offstatecurrent(Ioff) andonstatecurrent(Ion)asafunctionoftemplatethicknessforarangeofchannellengthfrom 60nm to 10nm. Three device designs are comparedone without groundplane, other with groundplaneunderthegateandthirdonewithcontinuousgroundplaneorauniformlydoped substrateofptypeconcentration5E18cm3.Theresultsarediscussedinthefollowingsections.

6.5.1 Potential in BOX and substrate

InFigure68,weseethat,forthelowdopeddevicei.e.devicewithoutgroundplane,thereoccurs apeakinthepotentialatthebody/BOXinterface.ThisriseinpotentialintheBOXandalsointhe substrate is attributed to the draininduced conduction of back channel. Figure 69a shows potentialcontoursintheBOX.ThepotentiallinesintheBOXarenotparalleltothebody/BOX interfacebuthighlydeformedsuggestingthecouplingofdraintobackchannel.Inotherwords, theelectricfieldvectorpointsfromdraintochannelviatheBOX.Thisalsomeansthat2Ddrain

49

a)

b)

Figure 6-7 a) Vt roll-off and b) DIBL for device with and without ground plane [7]

Figure 6-8 Simulated vertical potential along the center of silicon body for 25nm long device: lowdoped (uniform substrate 1E15cm-3) and ground-plane device. The scale on y-axis is in volts and xaxis in um

50

a)

b) Figure 6-9 Simulated potential contours in 25nm long device with 5nm thick template. Drain is biased at 1V and back-gate at 0V a) Device without ground-plane (epi-SOI) b) Device with ground plane (GP epi-SOI)

51

to body capacitance dominates. On the other hand, for the case of groundplane, the peak in potential is lowered though not completely suppressed. The potential in the substrate is also lowered. Moreover, in Figure 69b, the potential contours in the BOX are flat and parallel to body/BOXinterfaceatleastintheSiO2layer.Thissuggeststhatthedrainhaslostsomecontrol overthebackchannelreducingtheDIBL.However,forcompletesuppressionofDIBL,theBOX thicknessneedstobescaled.

6.5.2 Template Thickness Effect

From Figure 610 through Figure 615, we see that, the groundplane improves device performance. EpiSOI refers to the device without ground plane. GP epiSOI refers to device withgroundplanealignedwiththegateandGPconepiSOIreferstodevicewithcontinuous groundplaneoruniformsubstrateofhighdoping.Forallchannellengths,groundplaneresults inahigherthresholdvoltageascomparedtothedevicewithoutgroundplane.Thisisbecauseof the reduced short channel effects. Consequently, the offstate current is lower for the ground planedevice.SoistheonstatecurrentthoughthedecreaseinIonissmallcomparedtodecrease inIoff.Asforthedevicewithoutgroundplane,thethresholdvoltageforgroundplaneincreases astemplatethicknessdecreases.Therefore,IoffandIonbothdecreasewithdecreasingtemplate thickness. For 60nm to 25nm channel length devices, the reduction in Ioff caused by ground planeisalmostanorderofmagnitude.Howeverfor15nmand10nmlongdevices,thereduction is not significant. This means that groundplane is more effective for long devices. And as channel length shrinks, additional device alterations such as BOX thickness scaling need to be adoptedtofurthersuppresstheshortchanneleffects.

6.5.3 Continuous Ground-plane Vs Ground-plane under gate

Continuous ground plane refers to a uniform substrate of doping 5E18cm3. To employ a continuousgroundplanewouldmeantostartwithahighlyconductingsubstrateandnomask set would required for defining the groundplane under the gate. However, the ease of fabrication comes at the cost of performance. As can be observed from Figures 610 through Figures 615, continuous ground plane results in a larger Ioff values compared to the ground plane under the gate. The reason is that very high substrate doping increases the parasitic capacitances between the source/drain and substrate undermining the benefits of using SOI

52

0.62 Threshold V oltage (V )

5nm 1.0E-08

4nm

3nm

2nm

0.97 0.92 Io n (m A ) 0.87 0.82 0.77 epi-SOI GP epi-SOI GP con epi-SOI

Template Thickness (nm)

0.59 epi-SOI GP epi-SOI GP Con epi-SOI

1.0E-09 Io ff (A/u m )

0.56

1.0E-10

0.53

1.0E-11
0.5 5nm 4nm 3nm 2nm Template Thickness (nm)

epi-SOI GP epi-SOI GP con epi-SOI

0.72 5nm 4nm 3nm 2nm Template Thickness (nm)

1.0E-12

Figure 6-10 Lg = 60nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for device with and without ground-plane

5nm
0.59 T hresho ld V oltag e (V ) 0.57

4nm

3nm

2nm

1.0E-06 Template Thickness (nm) 1.0E-07 Io ff (A /u m )

1.18 1.14 1.1 Io n (m A ) 1.06 1.02 0.98 0.94 epi-SOI GP epi-SOI GP con epi-SOI

0.55 0.53 0.51 0.49 0.47 5nm 4nm 3nm 2nm epi-SOI GP epi-SOI GP con epi-SOI

1.0E-08

epi-SOI GP epi-SOI GP con epi-SOI

1.0E-09

1.0E-10

0.9 5nm 4nm 3nm 2nm Template Thickness (nm)

Template Thickness (nm)

Figure 6-11 Lg = 45nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for device with and without ground-plane

53

5nm
0.5

4nm

3nm

2nm

1.8 1.7 1.6 Io n (m A ) 1.5 1.4 epi-SOI GP epi-SOI GP con epi-SOI

1.0E-03 Template Thickness (nm)

T hresh o ld V o ltage (V )

1.0E-04
0.45 epi-SOI GP epi-SOI GP con epi-SOI 0.4

Io ff (A /u m )

epi-SOI GP epi-SOI GP con epi-SOI

1.0E-05

1.0E-06

1.3 1.2
5nm 4nm 3nm 2nm

0.35 5nm 4nm 3nm Template Thickness (nm) 2nm

1.0E-07

Template Thickness (nm)

Figure 6-12 Lg = 30nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for device with and without ground-plane

5nm
0.49 epi-SOI Threshold V oltage (V ) GP epi-SOI GP con epi-SOI

4nm

3nm

2nm

2 1.9 1.8

1.0E-03 Template Thickness (nm)

Io ff (A /u m )

1.0E-04

Io n (m A )

0.41

1.7 1.6

0.33

1.0E-05 epi-SOI GP epi-SOI GP con epi-SOI

1.5 1.4 5nm

epi-SOI GP epi-SOI GP con epi-SOI

0.25 5nm 4nm 3nm 2nm Template Thickness (nm)

1.0E-06

4nm

3nm

2nm

Template Thickness (nm)

Figure 6-13 Lg = 25nm a) Threshold Voltage b) Ioff c) Ion versus Template Thickness for device with and without ground-plane

54

5nm 1.0E-02

4nm

3nm

2nm

3.4

Template Thickness (nm) epi-SOI GP epi-SOI GP con epi-SOI 1.0E-03

3 Ion (mA)

Ioff (A/um)

2.6

epi-SOI GP epi-SOi GP con epi-SOI

1.0E-04

2.2 5nm 4nm 3nm Template Thickness (nm) 2nm

Figure 6-14 Lg = 15nm a) Ioff c) Ion versus Template Thickness for core and new device

5nm 1.0E-02

4nm

3nm

2nm

5.5

Template Thickness (nm)

5
Ioff (m A /um )

Ion (m A)

epi-SOI GP epi-SOI GP con epi-SOI

4.5

epi-SOI GP epi-SOI GP con epi-SOI

4
1.0E-03

5nm

4nm

3nm

2nm

Template Thickness (nm)

Figure 6-15 Lg = 10nm a) Ioff c) Ion versus Template Thickness for core and new device

55

material. [7]. Also very high substrate doping increases body effect. The increased parasitic capacitancesleadtogreateroffsatecurrentandreducedspeed.Forthisreason,itispreferredto haveagroundplanestructureintheBOXunderneaththegateandkeepthesubstrateaslowly doped.Alowdopingconcentrationwouldkeepparasiticcapacitancestominimum.

6.5.4 Ground-plane Device and ITRS

Figure616showstheIoffvaluesversuschannellengthforthedevicewithandwithoutground planeandhowtheycomparewithITRSprojections.Thetemplatethicknesssis5nmisallcases. Figure617doesthesameforIon/Ioffratios.Itistonotethatthegroundplanegreatlyimproves Ioff and Ion/Ioff ratios down to 25nm channel length. For 15nm and 10nm length devices, improvement with ground plane is small. The device with continuous groundplane performs only slightly worse than device with groundplane under gate. While the ITRS projection for 45nmdevicewasnotmetearlier,itiseasilymetwithgroundplanedevice.

6.6 Conclusion and Next

The groundplane in the substrate underneath the gate reduces fringing field lines in the substratefromthedrain.Itcausesdraintolosecontroloverbackchanneltherebyloweringthe potential in Box and substrate. The result is a reduction in short channel effects mainly DIBL throughBOX.SimulationsshowthatemployinggroundplanecanhelpmeetITRSrequirement withmoreease.Thus,fromthispointon,devicewithgroundplanewillbeconsidered.Thegoal from now on would be to understand other measures for reducing short channel effects and altering device design parameters accordingly to meet the ITRS specification at all gate length levels.

56

10nm 1.0E-02 1.0E-03 1.0E-04 1.0E-05

15nm

25nm

30nm

45nm

60nm

Ioff (A/um)

1.0E-06 1.0E-07
5nm epi-SOI

1.0E-08 1.0E-09 1.0E-10 1.0E-11

5nm GP epi-SOI 5nm GP con epi-SOI ITRS HP

Channel Length (nm)

Figure 6-16 Comparison of device Ioff values with ITRS High Performance Logic projections for device with and without ground-plane and 5nm thick template

1.0E+08 1.0E+07 1.0E+06 1.0E+05 Ion/Ioff 1.0E+04 1.0E+03 1.0E+02 1.0E+01 1.0E+00 10nm 15nm 25nm 30nm 45nm 60nm Channel Length (nm)

5nm epi-SOI 5nm GP epi-SOI 5nm GP con epi-SOI ITRS HP

Figure 6-17 Comparison of device Ion/Ioff ratios with ITRS High Performance Logic projections for device with and without ground-plane and 5nm thick template

57

6.7 References
[1]T.ErnstandS.Cristoloveanu,Thegroundplaneconceptforthereductionofshortchannel effectsinfullydepletedSOIdevices,ElectrochemicalSocietyProceedings,pp.329334,1999. [2] Ernst T, Cristoloveanu S. Buried oxide fringing capacitance: a new physical model and its implicationonSOIdevicescalingandarchitecture.IEEEIntSOIConf1999;389. [3]J.P.Colinge,J.T.ParkandC.A.Colinge,SOIDevicesforSub0.1umgatelengths,Proc.Int. Conf.Microelectronics,1215May,2002,pp.109113 [4] T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, Fringing field in sub0.1 um fully depletedSOIMOSFETs:Optimizationofthedevicearchitecture,SolidStateElectron.,vol.46,pp. 373378,2002. [5]W.XiongandJ.P.Colinge,SelfalignedimplantedgroundplanefullydepletedSOIMOSFET, ElectronicsLetters,Vol.35,No.23,IEE,pp.205960,1999 [6] Y. Omura, Silicononinsulator (SOI) MOSFET structure for sub50nm channel regime , in SilicononInsulatortechnologyandDevicesX,Ed.byS.Cristoloveanu,P.L.F.Hemment,K.Izumi, G.K.Celler,F.AssaderaghiandY.W.Kim,ElectrochemicalSocietyProceedings,Vol.20013,pp.205 210,2001 [7] Xiong W, Ramkumar K, Jang SJ, Park JT, Colinge JP., Selfaligned groundplane FDSOI MOSFETIn:ProcIEEEIntSOIConf,2002.p.23.

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Chapter 7
Suppressing Short Channel Effects
7.1 Introduction
Loweringofthethresholdvoltageaschannellengthscalesisreferredtoasshortchanneleffects. Thresholdvoltageisreducedbychargesharinganddraininducedbarrierlowering(DIBL)inthe silicon film. An extra component of DIBL results from the fringing fields from drain into the buried oxide and underlying substrate. Charge sharing occurs when the charge on the gate is balancednotonlybythesemiconductorchargeunderthegatebutalsobychargeinthesource anddraindepletionregions.Chargesharingisvisibleinshortchanneldevicesevenatlowdrain voltages.DIBLontheotherhandisattributedtotheelectrostaticinfluenceofdrainonthesource to channel barrier height. A high positive bias on the drain causes field lines from drain to electrostaticallycoupletothechannel,loweringthebarrieratsourceside.Thisresultsingreater flow of electrons from source thereby reducing the threshold voltage. Short channel effects in fully depleted SOI MOSFET therefore are influenced by silicon body thickness, silicon film doping, buried oxide material and thickness, substrate doping and backgate bias. As devices scaletosub100nmregime,severaldesignoptionsneedtobeconsideredtoeffectivelycontrolthe threshold voltage and ensure short channel effects to minimum. In order to scale with an undoped silicon body, the gate workfunction engineering needs to be adopted. This chapter discussesseveralaspectsoftheFDSOIdevicethatcontrolthethresholdvoltage.

7.2 Silicon Channel Doping Effect

Doping the silicon channel reduces depletion width under the gate and increases threshold voltage. It shields the channel from electric field lines from drain via the silicon body which would otherwise lower the barrier for electrons to flow from source to channel. High silicon channel doping is an effective way of suppressing short channel effects for both bulk and SOI device.Infact,forbulkdevices,itisthelastalternativetocontinuescaling.However,veryhigh

60

doping of concentration of the order of 1E19 cm3 is required. Even for short channel FDSOI devices, high channel doping is advantageous. High channel doping also implies thin silicon bodytoensurefulldepletion.Figure71showsshiftinthresholdvoltagefora100nmlongSOI device with 5nm thick gate oxide and 360nm thick buried oxide for different channel doping densities.[1]Whenthesiliconfilmisthick,deviceispartiallydepleted(PD)andbelowacritical thickness,fulldepletionoccurs.WhileinPDmode,highdopingresultsinreducedDIBL,inFD mode,DIBLissmallerwithlighterfilmdoping.TheadvantageofathinfilmSOIdeviceisthat thechannelcanbeundoped.However,forverysmallFDSOIdevices,channeldopingbecomes necessary for threshold voltage control. Figure 72 shows channel doping requirements for FDSOIthatareneededtoachieveathresholdvoltageof0.25VandDIBLofabout100mV/V.[2] The results are based on 2D device simulations using MEDICI. For Leff=28nm, extremely high doping of ~1019cm3 with silicon film thickness, TSi<6nm is needed. The doping requirement reaches6.5E19cm3 forLeff=9nmwithTSi=3nm.RecentlyLuetal,[3]revisedthescalingtheoryfor ultrathinbodySOIMOSEFET.Figure73from[3]showsthresholdvoltagerollofffordifferent channel doping. It indicates that minimum channel length set by DIBL of 100mV/V is 25% improved with the channel doping concentration raised to 1.4E19 cm3 from lowly doped 3.9E15cm3. Using Halo implants while keeping the channel undoped is another option for suppressingshortchanneleffects.Simulationsin[4]showthatstronghaloimplantsresultsinless DIBlthanmildhaloimplants.Figure74from[4]showssuppressedthresholdvoltagerollofffor strongerhaloimplants.Despitetheadvantagesofhighchanneldoping,utilizingthisoptionis not viable. Firstly, high channel doping results in reduced carrier mobility. The mobility reduction at high field is attributed mainly to dopant induced scattering. [5] Reduction in mobility results in reduced current drive. Secondly, high doping causes increased threshold voltage fluctuation due to random dopant placement effects. [6] Bandtoband tunneling associatedwithstrongdrainhaloalsocausesaconsiderableoffstateleakagecurrent.Apartfrom above,dopingthechanneltosuchhighimpuritylevelsinultrathinsiliconfilmsisalsoquitea challenge.

7.3 Silicon Film Thickness Effect

Both Figure 71 and Figure 72 indicate that reducing the silicon film thickness greatly reduces shortchanneleffects.ThisistheprimaryadvantageofultrathinbodySOI.Athinsiliconbody ensuresnopathinchannelisfarawayfromthegatewhichhasfullcontroloverthechannel.In

61

Figure 7-1 Vt shift Vs TSi for different channel doping [1]

Figure 7-2 MEDICI predicted TSi and channel doping requirements for FDSOI CMOS. Noted front oxide thickness values track SIA ITRS 2001 [2]

Figure 7-3 Threshold voltage roll-off for different channel doping [3]

62

other words, subsurface leakage paths are eliminated. A thin silicon body also allows for undoped channel and thus avoids much of the above mentioned prolems associated with high channeldoping.Figure75showsreducedDIBLandimprovedsubthresholdslopeforthinnerTSi devices. [2] As TSi scales from 10nm to 5nm, DIBL is reduced from 140mV/V to 40mV/V and subthresholdswingfrom83to66mV/decadeforLg=40nm.Accordingscalingtheoryin[3],two dimensionaldevicesimulationshowsthatforathingateinsulator,theminimumchannellength canbeexpressedas,

Lmin 4.5 (TSi + ( Si / I ) TI )

where TSi is the silicon thickness, and I and TI are the permittivity and thickness of the gate insulator. This reduces to LminTSi/4 for SiO2 as gateoxide and LminTSi/5 for highk gate dielectric.2Dsimulationsin[2]alsopredictLminTSi/5forconventionalthickBOXFDSOIdevice. Thereexistsalimitforsiliconfilmthicknessscaling.Whenthesiliconfilmistoothin,structural aswellaselectricfieldinducedconfinementleadstocarrierenergyquantization.[7]TheVtshift duetoquantummechanical(QM)confinementincreasesquadraticallywithsiliconfilmthickness for a given film thickness control. [8] The threshold voltage uncertainty makes it impossible to design the device in this regime. In Figure 76, dotted lines show the Vt shift due to QM confinement of thin silicon channel. This sets a lower limit of TSi=4nm on silicon channel thickness.Also,ahighseriesresistanceofthinsiliconchannelresultsinsmallerdrivecurrent.[7] Inadditiontothesequantizationeffects,ithasbeenobservedthatcarriermobilitydecreaseswith decreasing TSi and is attributed to higher phonon scattering rates for spatially confined carriers and also increases surfaceroughness scattering. [9] These effects limit silicon film thickness scalingtoabout4nm.

7.4 Back-gate Bias Effect

InFDSOItransistor,becausesiliconbodyisthin,thereexistselectricalcouplingbetweensurface potentials at the front and the back interfaces. [10] As a result of this interface coupling, the thresholdvoltageismodulatedbythebackgatebias.[11]Severalanalyticalmodelsforthreshold voltage dependence on backgate bias have been proposed. [12][13][14]. Figure 77 shows the theoreticaldependenceoffrontgatethresholdvoltageonbackgatebiasforNMOSdevice.[12]If

63

Figure 7-4 Threshold voltage versus channel length for mild and strong halo implants [3]

Figure 7-5 DIBL and subthreshold swing Vs channel length for different TSi [2]

Figure 7-6 Dependence of Vt and QM shift in Vt on TSi. On right axis is sensitivity of Vt to TSi [8]

64

the backgate voltage is negative and less than VAGb the back surface is accumulated and back surfacepotentialisindependentofbackgatevoltageasisthethresholdvoltage.ForVGbbetween VAGbandVIGb,thebacksurfaceisdepletedandthresholdvoltagedecreaseslinearlyasbackgate voltage increases. For VGb> VIGb, the back surface is inverted and back surface potential is virtually invariant so is the threshold voltage. Figure 78 shows experimental results for thresholdvoltagevariationwithbackgatevoltagefor0.25umand80nmdeviceswith20nmthick siliconfilm.[14]ThelineardecreaseofVtwithbackgatebiasVG2ismodeledas,

VTdep = VTacc 1 1

CSi Cox 2 (VG 2 VGacc ) 2 Cox1 ( Cox 2 + CSi + Cit 2 )

Where Cox1,2 are front and backgate oxide capacitances, CSi=Si/TSi is the depleted film capacitance, Cit2=qDit2 is the back interface trap capacitance, VaccT1 is the front gate threshold voltageforbackchannelaccumulation,andVaccG2isthebiasbelowwhichthebackchannelwill alwaysbeinaccumulationirrespectiveofVG1.Theslopeoflinearregionisnamedbodyfactorn anddependsonBOXthickness.InFigure78changeinslopeoccursatslightlypositivebackgate biaswhenthebacksurfaceisdrivenfromdepletiontoweakinversion.Thisleadstodegradation insubthresholdslope.[8]Figure79showsthatamorenegativebackgatebiasresultsinreduced DIBL. Thus, backgate bias is an effective way of tuning the threshold voltage and thereby reducingshortchanneleffects.

7.5 Gate Workfunction Effect

AsimplifiedexpressionforthresholdvoltageofaFDSOIdeviceis[15],

Vth = VFB + 2F +

qN SOI tSOI COX

Asdevicesscale,thesiliconbodythicknessscalesaswell.Withtheuseofhighkgatedielectrics, the gateoxide capacitance increases. It becomes difficult to control the threshold voltage by changingtheimpurityconcentrationofthechannel.Infact,inordertoavoidtheproblems

65

Figure 7-7 Theoretical dependence of Vt on back-gate voltage [12]

Figure 7-8 Dependence of Vt on back-gate voltage [14]

Figure 7-9 DIBL Vs TSi for different back-gate voltages [8]

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associated it with high channel doping it is preferable to keep the channel undoped. In such a case, gateworkfunction engineering gives an option for controlling the threshold voltage. [16][17]Figure710showsthevariationofoffstateleakagecurrentfor50nmFDSOIMOSFETfor different gateworkfunction values. [17] The body is lightly doped 1E15cm3. The dotted and solidlinesmarkthetargetsofITRSforHighperformance(HP)andLowOperatingPower(LOP) applications. AS gateworkfunction increases, both Ion and Ioff decrease due to increase in thresholdvoltage.Forgatematerialswithhigherworkfunctions,Ioffdecreasesmorerapidlywith body thickness while Ion decreases slowly. The ratio Ion/Ioff is plotted in Figure 711. It is observedthatforsamebodythickness,higherworkfunctionyieldsgreaterIon/Ioffratio.Thus,a largerworkfunctionismoresuitedtomeetITRSrequirements.Figure712showsthatincreasing workfunctionsuppressingshortchanneleffects.Here,Vtismeasuresasdifferentinthreshold voltage at drain bias of 0.05V and 1.2V. The Vt of devices with larger workfunctions is higher whichresultsinsmallerDIBLor,Vt/Vt.

7.6 Simulation Setup and Results

Twodimensionalsimulationswereperformedontheepitaxialoxidebaseddeviceemployingthe ground plane implant in the substrate under the gate to study the effects of above discussed parametersforcontrollingthresholdvoltageandsuppressingshortchanneleffects.

7.6.1 Varying the silicon film thickness

Twodevicestructuresaresimulated.Thesoideviceistheepitaxialoxidebaseddevicewithout groundplaneanduniformlydopedsubstrateofconcentration1E15cm3.Theotheristheground plane device with a backgate bias of Vbg=0.2V. The template is 5nm thick and the silicon film thickness is varied. The metal workfunction is 4.7eV. DIBL is measured as the difference in thresholdvoltageatdrainbiasof0.1Vand1V.Figure713plotsDIBLversuschannellengthfor threedifferentsiliconfilmthicknesses.Evidently,thinnersiliconfilmresultsinlesserDIBL.Also, DIBLfordevicewithgroundplaneislesserthanthatwithoutgroundplane.Thus,bothreducing thesiliconfilmthicknessandemployinggroundplaneareeffectiveinsuppressingshortchannel effects.Figure714andFigure715plotthresholdvoltagerollofftrend.DeltaVtismeasuredas deviationofthresholdvoltagefromitsvaluefora1umlongdevice.Rolloffisworseforthicker siliconfilmandimproveswithgroundplane.Figure716plotssubthresholdswingversus

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Figure 7-10 TSi dependence of the off-state current of 50nm UTB device for different M values [17]

Figure 7-11 Ratio of Ion/Ioff pf 50nm UTB device for different TSi and M values [17]

Figure 7-12 Ratio of Vt/Vt versus TSi with different M values [17]

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10 0.0 -0.1
-0.05

100

10

100

1000

0.00

DIBL (Delta Vt) (v)

-0.2
Delta Vt (V) -0.10 tsi = 5nm gp -0.15 tsi = 10nm gp tsi = 5nm soi -0.20 tsi = 10nm soi

-0.3 -0.4 -0.5 -0.6 -0.7 Channel Length (nm)

tsi = 5nm GP tsi = 10nm GP tsi = 15nm GP tsi=5nm soi tsi=10nm soi tsi=15nm soi

-0.25

-0.30 Channel Length (nm)

Figure 7-13 DIBL Vs Lg for different TSi for device with ground-plane (GP, Vbg=-0.2V) and without (soi). Template thickness is 5nm

Figure 7-14 Vt roll-off for TSi =5nm and 10nm for device with ground-plane (GP, Vbg=-0.2V) and without (soi). Template thickness is 5nm

10

100

1000

1800
0.00 -0.05 -0.10 Delta Vt (V) -0.15 -0.20 -0.25 -0.30 -0.35 tsi = 5nm gp tsi = 15nm gp tsi = 5nm soi tsi = 15nm soi

1600 Subthreshold Swing (mV/dec) 1400 1200 1000 800 600 400 200 0 tsi = 5nm gp tsi = 10nm gp tsi = 15nm gp tsi = 5nm soi tsi = 10nm soi tsi = 15nm soi

-0.40 Channel Length (nm)

10

100

Channel Length (nm)

Figure 7-15 Vt roll-off for TSi =5nm and 10nm for device Figure 7-16 Subthreshold Swing Vs Lg for different with ground-plane (GP, Vbg=-0.2V) and without (soi). TSi for device with and without ground-plane. Template thickness is 5nm Template thickness is 5nm

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channel length. A thinner Si film results in a better subthreshold slope. The value is about 70mV/decade for groundplane device for TSi=5nm and begins to degrade substantially as channellengthscalesbelow20nm.Groundplanedevicethoughprovidesabettersubthreshold characteristicthanthedevicewithoutit.Figure717plotsoffstateleakagecurrentfordifferent siliconfilmthicknesses.Aschannellengthscales,Ioffincreases.Athinnersiliconbodythickness results in a smaller leakage current. Consequently, Ion/Ioff ratio is larger for thinner Si film as showninFigure718.

7.6.2 Varying the back-gate bias

Figure 719 plots threshold voltage rolloff for TSi=7nm and Vbg=0.2V, 0.6V and 1V. Metal workfunctionis4.7eV.Anegativebiasonthebackgatedrivesthechanneltowardsaccumulation andcausethethresholdvoltagetoincrease.Thebackgatebiasislimitedbythemagnitudeofthe powersupplyvoltageonthenegativeendandonthepositiveendbyavaluethatdrivestheback channel into inversion and leads to degradation in subthreshold slope. Figure 720 plots DIBL versus channel length. Since, Vbg=1V results in a larger threshold voltage, it results in the smallestvalueofDIBLforanygatelength.Amorenegativebiasonthebackgatealsoimproves subthresholdswingasshowninFigure721.Theswingdegradeshoweverforsub20nmdevices. Figure722andFigure723plotvariationofIoffandIon/Ioffratiowithchannellength.Alarger negativebiasresultsinasmallerIoffandlargerIon/Ioffvalue.For15nmand10nmgatelength devices,IoffandIon/Ioffvaluesdontchangemuchwithchangeinbackgatebias.

7.6.3 Relationship between silicon film thickness and back-gate bias

Figure 724 plots threshold voltage versus backgate bias for TSi=5nm and 10nm. Vt decreases linearlyasbackgatebiasincreases.AtaroundVbg=0.2V,thereoccursachangeinslopewhenthe back channel is driven into weak inversion. Beyond this point, the subthreshold swing also degradessubstantiallyasshowninFigure725.Thus,thevalueofbackgatebiasmustlieinthe rangethatensuresthatthebackchannelisunderdepletion.Figure726plotsDIBLversusback gatevoltage.Asdiscussedbefore,athinnersiliconfilmandamorenegativebackgatebiasresult in lesser DIBL. Thus, backgate bias is an essential feature for controlling the threshold voltage andsuppressingshortchanneleffectsinsub100nmFDSOIdevices.

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Ioff Vs Channel length

10 100

Ion / Ioff Ratio 1.0E+16 1.0E+14

1.0E-01 1.0E-03 1.0E-05 Ioff (A/um) 1.0E-07 1.0E-09 1.0E-11 1.0E-13 1.0E-15 tsi = 5nm tsi = 10nm tsi = 15nm

1.0E+12 Ion / Ioff (A/A) 1.0E+10 1.0E+08 1.0E+06 1.0E+04 1.0E+02 tsi = 5nm tsi = 10nm tsi = 15nm

1.0E-17 Channel Length (nm)

10

100

Channel Length (nm)

Figure 7-17 Ioff Vs Lg for different TSi for device with ground-plane, Vbg=-0.2V and 5nm thick template

Figure 7-18 Ratio Ion/Ioff Vs Lg for different TSi for device with ground-plane, Vbg=-0.2V and 5nm thick template

0.9 0.85 Threshold Voltage (V) 0.8 0.75

Delta Vt (V) 0.00 -0.10 -0.20

20

40

60

80

100

0.7 0.65 0.6 0.55 0.5 10

vbg = -1V vbg = -0.6V vbg = -0.2V

-0.30 -0.40 -0.50 -0.60 -0.70

vbg = -1V vbg = -0.6V vbg = -0.2V

100 Channel Length (nm)

1000

-0.80 Channel Length (nm)

Figure 7-19 Vt Vs Lg for ground-plane device with TSi =7nm and different back-gate voltages. Template is 5nm thick

Figure 7-20 DIBL Vs Lg for ground-plane device with TSi 7nm and different back-gate voltages. Template is 5nm thick

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10
Subthreshold Swing (mV/decade) 860

100

1.0E-03
vbg = -1V

1.0E-05
660
vbg = -1V vbg = -0.6V

vbg = -0.6V vbg = -0.2V

Ioff (A/um)
100

1.0E-07 1.0E-09 1.0E-11 1.0E-13

460

vbg = -0.2v

260

60 10 Channel Length (nm)

1.0E-15 Channel Length (nm)

Figure 7-21 Subthreshold Swing Vs Lg for ground Plane device with TSi=7nm and different back-gate voltages. Template is 5nm thick.

Figure 7-22 Ioff Vs Lg for ground-plane device with TSi=7nm and different back-gate voltages. Template is 5nm thick.

1.0E+16 1.0E+14
vbg = -1V

Ion / Ioff (A/A)

1.0E+12 1.0E+10 1.0E+08 1.0E+06 1.0E+04 1.0E+02 10

vbg = -0.6V vbg = -0.2V

100 Channel Length (nm)

Figure 7-23 Ratio Ion/Ioff Vs Lg for ground-plane device with TSi=7nm and different back-gate voltages. Template is 5nm thick

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0.7 0.65 0.6 0.55 0.5 0.45 0.4 -1 -0.6 -0.2 0.2 Back-gate Voltage (V)
tsi = 5nm tsi = 10nm

200 190 180 170 160 150 140 130 120 110 100 -1 -0.6 -0.2 0.2 Back-gate Voltage (V)
tsi = 5nm tsi = 10nm

Figure 7-24 Threshold Voltage Vs Back-gate voltage for Figure 7-25 Subthrehsold Swing Vs Back-gate ground-plane device with TSi=5nm and 10nm and 5nm voltage for ground-plane device with TSi=5nm and template thickness 10nm and 5nm template thickness

Threshold voltage (V)

-0.15 -0.2 Delta Vt (V) -0.25 -0.3 -0.35 -0.4 -0.45 -1 -0.6 -0.2 0.2 0.6 Back-gate Voltage, Vbg (V)
tsi = 5nm tsi = 7nm tsi = 10nm

Figure 7-26 DIBL Vs Back-gate voltage for ground-plane device with TSi=5nm and 10nm and 5nm template thickness

S-factor (mv/decade)

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7.7 Conclusion
Two dimensional device simulations show that groundplane is effective in reducing short channel effects. Sub100nm FDSOI devices will employ groundplane along with a thin silicon film.Siliconfilmthicknessneedstobebelow10nmforsubstantivereductionofSCEs.Moreover, inordertoscalewithundopedbody,bothworkfunctionengineeringandbackgatecontrolneed tobeexercised.Alargerworkfunctionandanegativebackgatebiasresultinalargerthreshold voltageandlesserSCEs.Theroleofsiliconbodythickness,bodydoping,gateworkfunctionand backgatebiasincontrollingtheSCEswasdiscussedcomprehensively.However,thereremains another important device feature that can be used to suppress SCEs. This is the buried oxide materialandthickness.Thisformsthediscussionofnextchapter.

7.8 References
[1]L.T.Su,J.B.Jacobs,J.Chung,andD.A.Antoniadis,Deepsubmicrometerchanneldesignin silicononinsulator(SOI)MOSFETs,IEEEElectronDeviceLett.,vol.15,no.5,pp.183185,May 1994. [2] V. P. Trivedi and J. G. Fossum, Scaling fully depleted SOI CMOS, IEEE Trans. Electron Devices,vol.50,no.10,pp.20952103,Oct.2003. [3]WeiYuanLuandYuanTaur,OnthescalinglimitofultrathinSOIMOSFETs,,IEEETrans. ElectronDevices,vol.53,no.5,pp.11371141,May2006 [4]B.Doris,etal.,ExtremescalingwithultrathinSichannelMOSFETs,inIEDMTech.Dig.,Dec 2002,pp.267270. [5] L. Ge, J. G. Fossum, and B. Liu, Physical compact modeling and analyses of velocity overshootinextremelyscaledCMOSdevicesandcircuits,IEEETrans.ElectronDevices,vol.48, pp.20742080,Sept.2001. [6]D.J.Franketal.,MonteCarlomodelingofthresholdvariationduetodopantfluctuation,in Symp.VLSITech.Dig.,June1999,pp.169170. [7] D. J. Frank, S. E. Laux, and M. V. Fischetti, Monte carlo simulation of a 30 nm dualgate MOSFET:HowshortcanSigo?,inIEDMTech.Dig.,1992,pp.553556. [8] H.S. Wong, D. Frank, and P. Solomon, Device design considerations for doublegate, groundplane, and singlegated ultra thin SOI MOSFETs at the 25 nm channel length generation,inProc.Int.ElectronDevicesMeeting,1998,p.407. [9]F.Gmizetal.,MonteCarlosimulationofelectrontransportpropertiesinextremelythinSOI MOSFETs,IEEETrans.ElectronDevices,vol.45,pp.11221126,May1998. [10] I. Yang, C. Vieri, A. Chandrakasan, and D. Antoniadis, Backgated CMOS on SOIAS for dynamicthresholdvoltagecontrol,IEEETrans.ElectronDevices,vol.44,p.822,1997. [11]S.R.Banna,P.C.H.Chan,P.K.Ko,C.T.Nguyen,M.Chan,Thresholdvoltagemodelfor deepsubmicrometer fully depleted SOI MOSFETs, IEEE Trans. Electron Devices, vol. 42, pp. 194955,November1995 [12] H.K. Lim and J. G. Fossum, Threshold voltage of thinfilm silicononinsulator (SOI) MOSFETs,IEEETrans.ElectronDevices,vol.ED30,pp.12441251,Oct.1983.

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[13]M.Noguchi,T.Numata,Y.Mitani,T.Shino,S.Kawanaka,Y.Oowaki,andA.Toriumi,Back gate effects on threshold voltage sensitivity to SOI thickness in fully depleted SOI MOSFETs, IEEEElectronDeviceLett.,vol.22,pp.3234,Feb.2001. [14] J. Pretet, S. Monfray, S. Cristoloveanu, and T. Skotnicki, Silicononnothing MOSFETs: performance,shortchanneleffects,andbackgatecoupling,IEEETrans.ElectronDevices,vol.51, no.2,pp.240245,Feb.2004. [15]H.Shimada,Y.Hirano,T.Ushiki,K.Ino,andT.Ohmi,TantalumgatethinfilmSOInMOS andpMOSforlowpowerapplications,IEEETrans.ElectronDevices,vol.44,pp.19031907,1997. [16] T. Numata, K. Uchida, J. Koga, and S. Takagi, Device design for subthreshold slope and threshold voltage control in sub100 nm fullydepleted SOI MOSFETs, in Proc. IEEE Int. SOI Conf.,Oct.2002,pp.179180. [17] AnX,HuangR,ZhaoB,ZhangXandWangY2004Design guideline of an ultrathin body SOIMOSFETforlowpowerandhighperformanceapplicationsSemicond.Sci.Technol.1934750

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Chapter 8
Buried Insulator Engineering
8.1 Introduction
InordertoscalefullydepletedSOIMOSFETbelow100nmgatelength,theburiedoxide(BOX) thickness must be scaled as well. Thinning the BOX cuts fringing field lines in the BOX from drain and improves draininduced barrier lowering (DIBL). It allows for additional control of thresholdvoltagetherebyallowingsiliconfilmtobethicker.BOXpermittivityalsohasaneffect on short channel effect. As a rule, scaling the BOX permittivity reduces DIBL. Engineering the buried oxide material and thickness to suppress short channel effects is referred to as buried insulatorengineering.

8.2 BOX Thickness Scaling

Theuseofahighlyconductingsubstrateunderneathathinburiedoxide(knownasgroundplane structure [1]) has been proved effective to reduce short channel effects in sub100nm fully depleted SOI devices. To scale the SOI device to shorter channel lengths (Lg <50nm), with an undoped Si body, requires a thinner BOX along with backgate voltage control to set the threshold voltage to a level so that short channel effects are suppressed [2]. A thinner BOX is neededmoresoastoensurethatsufficientreductionofshortchanneleffectsisachievedwithout requiring to increase the magnitude of backgate voltage beyond the supply voltage. This is because a thinner BOX increases the backgate coupling effect by increasing the bodysubstrate capacitance. Analysis in [3] show that Tbox < Lg/2 is required for substantive reduction of SCEs. Thismeansforsub50nmdevices,BOXmaybeatmost25nmthick.2Ddevicesimulationsin[2], [4]and[5]furthersupportthistheory. Figure 81a shows the potential contours in 30nm long device with groundplane and 200nm BOX thickness. The BOX permittivity is 3.9. The groundplane device has a p+ implant of

76

concentration5E18cm3inthesubstrateunderthegate.Thesubstrateisdoped1E18cm3andthe backgatevoltageis0.2V.Alsosimulatedisthedevicewithoutgroundplane.Ithasauniformly doped substrate of concentration 1E15cm3 and connected to ground. This is referred to as the lowdoped (LD) device. For both devices, silicon film is 7nm thick and metal workfunction is 4.7eV. WhentheBOXisthick,thelateralpenetrationofelectricfieldlinesfromdraintochannelviathe BOXandthesubstrateisthemajorcauseofDIBL.ThiscomponentofDIBLisreferredtoasDIBL throughBOX.[6]TheequipotentialcontoursinBOXarenotparalleltobody/BOXinterfacebut highly deformed as shown in Figure 81a for Tbox=200nm. At this thickness, the drain/source to body capacitances dominates over the bodysubstrate capacitance. The electric field vectors are from source to body and drain to body. The result is that the back channel is driven under conduction from depletion to weak inversion causing a peak in potential in BOX as shown in Figure 81b. This effect which causes additional short channel effects is referred to as drain induced virtual substrate biasing (DIVSB) [6]. The potential at drain is coupled to the back interface potential as if the substrate is positively biased. Ernst et al [3] developed analytical expressionsforsource/draintobodycapacitancesandderivedthecriterionforsuppressingthe DIVSB effect. The 1D bodysubstrate capacitance must dominate over the 2D source/drain to bodycapacitance.Accordingto[3],groundplanestructurealongwithverythinBOXshouldbe employed. Figure 82a shows potential contours in the groundplane device with 10nm thick BOX and permittivityvalue3.9,whicharehorizontalandparalleltoBOX/bodyinterfacemuchlikethosein thebodyofalongchanneldevice.ThismeansthatatTbox=10nm,thebackchannelisnolonger underthecontrolofdrain.ThechannelisnolongercoupledtodrainthroughtheBOXandDIBL through BOX is completely suppressed. Potential contours show that 1D bodysubstrate capacitance dominates over source/drainbody capacitances and the electric field vector is now perpendicular to the body/BOX interface. Figure 81b shows the vertical electrostatic potential through the center of silicon body for Tbox=10nm. As can be observed, the peak in potential at body/BOX interface is completely suppressed. It is to note that, while employing groundplane structurereducesthepeak,(comparisonwithLDandGPdeviceinFigure81b)combiningitwith athinBOXcompletelyeliminatesit.Thus,scalingtheBOXthicknessreducesshortchannel

77

 a)b)
Figure81a)Simulatedequipotentialcontoursingroundplanedevicewithsourceatground, drainat1VandbackgatevoltageVbg=0.2V.BOXthicknessis200nmandpermittivityis3.9. Thescaleonxandyaxisisinumb)ElectrostaticPotentialalongaverticalcutthoughcenter ofsiliconbody.Thescaleonxandyaxisisinumandvoltsrespectively

a)b)
Figure82a)Simulatedequipotentialcontoursingroundplanedevicewithsourceatground, drainat1VandbackgatevoltageVbg=0.2V.BOXthicknessis10nmandpermittivityisa)k= 3.9andb)k=20.Thescaleonxandyaxisisinum

78

effects. It leads to an increase in the threshold voltage and gives an alternative control over thresholdvoltageinadditiontobackgatevoltageandgateworkfunctionengineering.

8.3 BOX Permittivity Scaling

PermittivityisaconstantcharacteristicoftheBOXmaterial.Ithasbeenshownthatreducingthe permittivitydecreasesshortchanneleffects.[7][8]Inparticular,Oshimaetalhaveshownin[9] thatDIVSBcanbealleviatedusingalowkBOXmaterial.For60nmdevicewith20nmthickBOX, 10nm thick Si film and 1E15cm3 substrate doping, it has been shown [9] that, buried Alumina withk=12.0resultsin7%higherpeakinpotentialatbody/BOXinterfacecomparedtoburiedSiO2 with k=3.9. Also, for the groundplane device, withTbox=50nm, buried alumina results in 20mV higherDIBLthanburiedSiO2for25nmgatelengthdevice.Thusitiscommonlyunderstoodthat lowk BOX results in lesser DIBL. The fact has formed the guiding principle for siliconon nothing MOSEFT where an airgap acts as the dielectric between the silicon body and the substrate.[10][11] Forsub50nmFDSOIdevice,BOXthicknessneedstobethinnerthan25nm.Onewouldexpecta lowk/thin BOX combination to yield least short channel effects and best device performance. However,thisisnotthecaseasweshowinthischapter.ThereisalimittotheBOXthickness, untilwhich,reducingthepermittivityoftheBOXlowersDIBL.However,belowthislimitwhich occursaround25nmforthegroundplanedevice,theroleoftheBOXpermittivityisreversedin the sense that a lowerk BOX yields larger DIBL compared to a higherk BOX. The fact was brieflymentionedin[7]buthasnotbeendiscussedcomprehensivelysofar.Alsoquantumeffects werenotconsideredinsimulationsin[7].Inthischapter,thistheoryispresentedindetailand supportedwith2Ddevicesimulations.

8.4 Permittivity role at thick and thin BOX

DIBL in short channel devices is associated with electrostatic coupling of drain to channel. The coupling of drain to channel via the silicon body is referred to as DIBL through silicon body whereascouplingofdraintochannelviatheBOXandsubstrateisreferredtoasDIBLthrough BOX.WhentheBOXisthick,thefieldlinesfromdrainviatheBOXandsubstrateturntheback channelonasdiscussedaboveandthereforeDIBLthroughBOXdominates.

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Figure83plotsDIBLversusBOXthicknessforlowdopeddeviceandgroundplanedevicewith Vbg=0.2VandVbg=1V.Permittivityvaluesofk=3.9andk=20.0areconsidered.ForarangeofBOX thickness, from 200nmn down to a critical value, lower permittivity results in lower DIBL. At TBox=100nm,DIBLatk=20is139%higherforgroundplanedevicewithVbg=0.2V,102%higherfor groundplanedevicewithVbg=1Vand168%higherforlowdopeddeviceascomparedtoDIBL at k=3.9. Thus, at thick BOX, lowk BOX results in lesser DIBL. This is because, at thick BOX, potential contours in the BOX are not parallel to body/BOX interface. The electric field vectors begin from drain and curl up to channel via the BOX. (Figure 81a) Reducing the BOX permittivity reduces this 2D coupling of drain to channel via the BOX thereby reducing DIBL throughBOX.[9] However,thereexistsacriticalthicknessbelowwhichthepermittivityroleisreversedandnowa lowk BOX results in larger DIBL. Figure 84 reproduces the plot in Figure 83 for BOX thicknessesbelow60nm.ThecrossoverpointoccursatTbox=35nmforVbg=1Vand25nmforVbg= 0.2V in case of the ground plane device and at Tbox = 10nm for the lowdoped device. This suggests that the fringing field reducing effect of the BOX permittivity is no longer dominant belowthecriticalthicknessandbecomessecondarytoanotherroleplayedbypermittivitywhich needstobeexplained.Figure84suggeststhatbelow25nmBOXthickness(asrequiredforsub 50nm devices), a higher permittivity BOX is better suited to meet the scaling capability requirements set by ITRS in terms of suppression of DIBL and therefore, also in achieving the targetedoffstateleakagecurrentvalue. At BOX thickness, Tbox=10nm, DIBL for k=20 is lower than that for k=3.9 by 18mV (or 38%) for groundplanedevicewithVbg=0.2Vandby17mV(or45%)forgroundplanedevicewithVbg=1V. EventhoughthereductioninDIBLbyhighkBOXissmall,itprovesthepointthatahighkBOX doesnt hurt device performance at thin BOX thickness as needed by sub50nm devices. Moreover,highkBOXonlyslightlyimprovestheshortchanneleffects. Figure85plotsDIBLversusBOXthicknessesbelowTbox=60nmfork=3.9andk=5.0.Thecrossover pointoccursatTbox=25nmforVbg=1Vand20nmforVbg=0.2Vincaseofthegroundplanedevice andatTbox=8nmforthelowdopeddevice.Figure86plotsthethresholdvoltageversusBOX

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0.48 0.42 0.36 Delta Vt (V) 0.30 0.24 0.18 0.12 0.06 0.00 0 40 80 120 160 200 Box Thickness (nm)
k = 3.9 vbg=-0.2V k = 20 vbg=-0.2V k=3.9 vbg=-1V k=20 vbg=-1V k = 3.9 LD k = 20 LD

Figure 83 DIBL versus BOX thickness for groundplane device with Vbg=0.2V and Vbg=1V andlowdoped(LD)device.LowerkBOXgiveslowerDIBLforthickBOX 0.24 Vbg = 0V Vbg = -1V 0.18 Vbg = -0.2V 0.12 k=3.9 vbg=-0.2V k=20.0 vbg=-0.2V 0.06 k=3.9 vbg=-1V k=20 vbg=-1V k=3.9 LD k=20 LD 0.00 0 10 20 30 40 50 60 Box Thickness (nm) Figure84DIBLversusBOXthicknessforgroundplanedevicewithVbg=0.2VandVbg=1V and lowdoped (LD) device with Vbg=0V. Higherk BOX gives lower DIBL below a critical BOXthickness
Delta Vt (V)

81

0.17

0.14

Delta Vt (V)

0.11

0.08

0.05

0.02 0 10 20 30

k = 3.9 vbg=-0.2V k = 5.0, vbg = -0.2V k = 3.9, Vbg = -1V k = 5.0, vbg=-1V k=3.9, LD k=5.0, LD
40 50 60

Box Thickness (nm)

Figure85DIBLversusBOXthicknessfork=3.9andk=5.0.Lg=30nm,TSi=7nm,Wf=4.7eV

0.8

0.7

Threshold Voltage (V)

k=3.9,vbg=-0.2 k=5.0, vbg=-0.2 k = 3.9, vbg=-1V k = 5.0, vbg =-1V k=3.9, LD k=5.0, LD

0.6

0.5

0.4

0.3

0.2 0 20 40 60 80 100 120 140 160 180 200

Box Thickness (nm)

Figure86ThresholdVoltageversusTBoxfork=3.9andk=5.0.Lg=30nm,TSi=7nm,Wf=4.7eV

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thicknessfork=3.9andk=5.0.Since,thresholdvoltageisaffectedbyDIBL;itreflectsthecrossover asobservedinDIBLplot.Thedefinitionofthresholdvoltageusedinthispaperisasin[12]andis thegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x107A.Here,Wisthegatewidthsetat 1mandLmetisthemetallurgicalchannellengthcorrespondingto30nmphysicalchannellength. The slight difference in crossover thickness between DIBL and threshold voltage plots is attributedtotheconstantcurrentmodelusedformeasuringthresholdvoltage. So what is the role of BOX permittivity below critical BOX thickness? As shown in Figure 82a anddiscussedabove,atTBox=10nm,thepotentialcontoursintheBOXareflatandparalleltothe body/BOX interface. The 1D bodysubstrate capacitance dominates over the 2D source/drain bodycapacitancesoppositetowhathappensatthickBOX.Therefore,wecanconcludethatatthe critical BOX thickness, DIBL through BOX is suppressed and below it, the only persistent componentofDIBLisDIBLthroughsiliconbody. Atthisthickness,ahighkBOXincreasesbody substrate capacitance and results in increased coupling between the drain and substrate. This causeslateralfieldlinesemanatingfromdraintowardschannelviathesiliconbodytobepulled towardssubstratereducingtheDIBLthroughsiliconbody.InFigure82a,fork=3.9,thepotential lines from drain to channel exist beyond the drain boundary in the silicon body whereas in Figure82b,forthecaseofk=20,theyarepushedinsidetheboundaryindicatingterminationof fieldlinesonthesubstrate.Also,k=20resultsinmorehorizontalandflatpotentialcontoursinthe silicon body compared to k=3.9 implying reduced DIBL through silicon body. To support this, Figure87plotsthechannelpotentialalongthebody/BOXinterfacefork=3.9andk=20casesfor Tbox=10nmandTbox=200nm.ATTBox=200nm,thepotentialbarrierbetweenthesourceandchannel is larger for k=3.9 than k=20 implying lesser DIBL for k=3.9 case. However, at TBox=10nm, the barrierissignificantlyhigherfork=20ascomparedtothatfork=3.9implyinglesserDIBLfork=20 case.ThisexplainswhyahighkBOX,k=20yieldslowerDIBLbelowcriticalBOXthickness. Toconclude,alowkBOXyieldslowerDIBLforthickBOXbyreducingDIBLthroughtheBOX. AhighkBOXyieldslowerDIBLforthinBOXbyreducingDIBLthoughthesiliconbody.Since, Vbg=1V is more effective in suppressing DIBL through the BOX compared to Vbg=0.2V, the crossoverpointisreachedatalargerBOXthicknessfortheformer.ThisisbecauseDIBLthrough theBOXiseliminatedatathickerBOX(Tbox=35nminFigure84)fortheformerandathinner BOX(Tbox=25nminFigure84)forthelatter.Forthelowdopeddevice,depletioninsubstrate

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 Figure87Electrostaticpotentialalongbody/BOXinterfaceatTBox=200nmand10nmfork=3.9 andk=5.0.Lg=30nm,TSi=7nm,Wf=4.7eV.Scaleonxaxisisinumandyaxisinvolts

0.65 0.6 Threshold Voltage (V) 0.55 Tbox=10nm 0.5 0.45 0.4 0.35 0.3 0.25 0.2 -1.5 -1 -0.5 0 0.5 1 1.5 Back-gate Voltage Vbg (V)
Figure88ThresholdvoltageversusbackgatebiasforTBox=200nm,25nmand10nmfork=3.9 andk=5.0.Lg=30nm,TSi=7nm,Wf=4.7eV

k=3.9 k=5.0

Tbox=25nm

Tbox=100nm

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addstoBOXthicknessandsincethereisnogroundplane,ittakesamuchthinnerburiedoxide, (Tbox=10nminFigure84)tocompletelyeliminateDIBLthroughtheBOX. According to [5], SCEs in thinbox SOI device are reduced due to increased transverse electric field in the silicon body and not only reduction of fringing fields in the BOX. For significant reduction,Tbox<25nmforgroundplanedeviceandTbox<10nmforlowdopeddevicearerequired. The limits agree well with critical BOX thickness we conclude above for suppression of DIBL throughBOX.InfactinFigure82b,itisobservedthatthefieldlinesaremorecloselyspacedin thesiliconbodyfork=20ascomparedtok=3.9.Thissuggeststhat,thereisanincreaseinvertical electric field in the silicon body which gives more control to frontgate over channel and improvesDIBL.Thissupportsthetheoryin[5].

Animportantdevicedesignconsiderationforthegroundplanedeviceisthechoiceoftheback gate voltage. Figure 88 plots threshold voltage variation with backgate bias for Tbox=10nm, 25nm and 100nm for permittivity values of 3.9 and 5.0. The back channel should be biased in depletion and for this range of backgate voltage, for 10nm and 25nm BOX thicknesses, highk resultsinlargerthresholdvoltagesuggestingsmallerDIBLandcapabilityforyieldingsmallerIoff values. For thick BOX, Tbox=100nm, a lowk results in larger threshold voltage for the range of backgate bias suggesting lower DIBL. The above discussion explains the permittivity role reversal effect with regards to backgate bias. It is noted that at BOX thickness below critical thickness,highkBOXyieldslesserDIBLirrespectiveofthebackgatebias. ThesubthresholdswingvariationwithBOXthicknessatdrainbias,Vd =1VisshowninFigure8 9.TheswingimprovesasBOXthicknessisscaled[1]andforshortchanneldevicesisgoverned morebyDIBLthantheBOXcapacitanceeffect.ThecrossoverinDIBLcharacteristicsinFigure84 are reflected in subthreshold characteristics as well. A highk BOX leads to better swing below thecriticalthicknessthoughtheimprovementisonlyafewmV/decade.

Figure810plotsIdVgcurvesforgroundplanedevicewithVbg=0.2Vforpermittivityvaluesof k=3.9, 5.0 and 20.0 for Tbox=200nm and 10nm. While highk results in greater offstate leakage currentatTbox=200nm,itresultsinsmallerleakageatTBox=10nm.

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165 155 Subthreshold Swing (mV/decade)

k = 3.9 Vbg= -0.2V

145 135 125 115 105 95 85 75 0 10 20 30 40 50 60 BOX Thickness (nm)

k = 20 Vbg= -0.2V k = 3.9 Vbg= -1V k = 20 Vbg= -1V

Figure89SubthresholdswingVsBOXthicknessforgroundplanedevice

Figure 810 IdVg curves for groundplane device for Tbox=10nm and 100nm at BOX permittivityofk=3.9,5.0and20.0.Drainisat1V,sourceat0VandVbg=0.2V

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8.5 Device Simulation of epi-SOI device

TheabovesectionsdiscussedtheroleofBOXpermittivityatthickandthinBOXanditsimpact on short channel effects. The simulations were applicable to a standard device with buried insulator being a single material. However, for the epitaxialoxide based device under investigation,theburiedinsulatorconsistsofhighktemplatematerialontopofSiO2.Ifthetotal insulator thickness is kept constant, and the thickness of template material is varied, then the impact on device performance is indirectly due to the BOX permittivity variation. The ground planedeviceissimulatedwith5E18cm3dopedgroundplaneand1E15cm3dopedsubstrate.The templatethicknessisvariedbetween2nmand5nmkeepingthetotalinsulatorthicknessconstant equalto15nm.ThebackgatevoltageisVbg=1V,TSi=7nmandmetalworkfunctionis4.7eV.

8.5.1 Varying Template Thickness

The permittivity of the insulator is determined by the parallel combination of the capacitive divider formed by template material and SiO2 underneath. For 15nm total thickness, the permittivity of insulator is 5.4(5nm), 5.0(4nm), 4.7(3nm) and 4.4(2nm). Thus varying template thicknessvariesBOXpermittivity.Itistobenotedthatthough15nmBOXthicknessisbelowthe criticalthicknesswehaveconcludedaboveandonewouldexpectathinnertemplatematerialto yield a larger DIBL by virtue of lower permittivity, it doesnt happen so. This is because; the substrate doping for epitaxial buriedoxide based device is lowly doped 1E15cm3 as against 1E18cm3 used in simulations before. A lower substrate doping implies a smaller critical BOX thicknesstosuppresstheshortchanneleffectsassociatedwithBOX. Figure811plotsDIBLversuschannellengthfor5nmand2nmtemplatethicknesses.Athinner template results in smaller DIBL by virtue of lower BOX permittivity. It is observed that, employinggroundplaneunderthegatefurtherimprovesDIBL. Figure 812 and Figure 813 plot threshold voltage rolloff trends. DeltaVt is measured as deviationofthresholdvoltagefromitsvaluefora1umlongdevice.Rolloffisworseforthicker template and improves with groundplane. For groundplane device, delta Vt improves from 0.33Vto0.24Vastemplatethicknesschangesfrom5nmto2nm.

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10 0.00 -0.05 100

10 0 -0.05 Threshold Voltage (V) -0.1 -0.15 -0.2 -0.25 -0.3 -0.35

100

-0.10 -0.15 Delta Vt (V) -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 Channel Length (nm)
template template template template 5nm GP 2nm GP 5nm soi 2nm soi

5nm GP 4nm GP 3nm GP 2nm GP 5nm soi 4nm soi 3nm soi 2nm soi

Channel Length (nm)

Figure 8-11 DIBL Vs Lg for two template thicknesses for device with ground-plane (GP, Vbg=-1V) and without (soi)

Figure 8-12 Threshold voltage roll-off Vs Lg for different template thicknesses for device with ground-plane (GP, Vbg=-0.2V) and without (soi)

10 0 -0.05

100
180.00 160.00 140.00 120.00 100.00 80.00 60.00
5nm GP 4nm GP 3nm GP 2nm GP 5nm soi 4nm soi 3nm soi 2nm soi

-0.1 Delta Vt (V) -0.15 -0.2

template 5nm GP

-0.25 -0.3 -0.35

template 2nm GP template 5nm soi template 2nm soi

S-Factor (mV/decade)

Channel Length (nm)

10

Channel Length (nm)

100

Figure 8-13 Vt roll-off Vs Lg for 5nm and 2nm template Figure 8-14 Subthreshold Swing Vs Lg for different thicknesses for device with ground-plane (GP, template thicknesses for device with ground-plane Vbg=-0.2V) and without (soi) (GP, Vbg=-1V) and without (soi)

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Figure814plotssubthresholdswingversuschannellength.Thevalueisabout69mV/decadefor groundplane device until 60nm channel length and begins to degrade below it. Groundplane howeversignificantlyimprovessubthresholdslope.Asexpected,athinnertemplateresultsina bettersubthresholdslope.For15nmBOXthickness,itcanbeshownthatIon/Ioffratioisbetterfor athinnertemplatelayer.

8.6 Conclusion
ScalingtheBOXthicknessreducesfringingfieldsintheBOXandthelateralcouplingofdrainto channel via the BOX. At thick BOX, reducing the permittivity, reduces DIBL through BOX. However, at thin BOX, increasing the permittivity increases coupling between drain and substrate allowing the field lines from drain penetrating the channel via silicon body to be terminated on to substrate, thereby reducing DIBL through silicon body. Buried layer engineering is an essential ingredient to scale FDSOI devices below 100nm gate length. In particularfor15nmand10nmgatelengthdevices,theBOXthicknessneedstobebelow10nm.At this thickness, a thicker template by virtue of higher permittivity would allow more ease in meetingtheITRSspecifications.

8.7 References
[1]T.Ernst,andS.Cristoloveanu,Thegroundplaneconceptforthereductionofshortchannel effectsinfullydepletedSO1devices,Electrochem.Soc.Proc.,1999,99,(3),p.329 [2] T. Numata, K. Uchida, J. Koga, and S. Takagi, Device design for subthreshold slope and thresholdvoltage control in sub100 nm fullydepleted SOI MOSFETs, IEEE Trans. Electron Devices,vol.51,pp.21612167,Dec.2004 [3] T. Ernst, C. Tinella, C. Raynaud, and S. Cristoloveanu, Fringing field in sub0.1 um fully depletedSOIMOSFETs:Optimizationofthedevicearchitecture,SolidStateElectron.,vol.46,pp. 373378,2002 [4] A. Vandooren et al., Scaling assessment of fullydepleted SOI technology at the 30nm gate lengthgeneration,inProc.IEEEInt.SOIConf.,Oct.2002,pp.2526. [5]V.P.TrivediandJ.G.Fossum,NanoscaleFD/SOICMOS:ThickorthinBOX,IEEEElectron DeviceLett.,vol.26,no.1,pp.2628,Jan.2005 [6]T.ErnstandS.Cristoloveanu,Buriedoxidefringingcapacitance:Anewphysicalmodeland itsimplicationonSOIdevicescalingandarchitecture,inProc.IEEEInt.SOIConf.,1999,pp.38 39. [7] R. Koh, Buried layer engineering to reduce the draininduced barrier lowering of sub0.05 mSOIMOSFET,Jpn.J.Appl.Phys.,vol.38,no.4B,pp.22942299,1999

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[8] H.S. Wong, D. Frank, and P. Solomon, Device design considerations for doublegate, groundplane, and singlegated ultra thin SOI MOSFETs at the 25 nm channel length generation,inProc.Int.ElectronDevicesMeeting,1998,p.407. [9] K. Oshima, S. Cristoloveanu, B. Guillaumot, H. Iwai, and S. Deleonibus, Advanced SOI MOSFETswithburiedaluminaandgroundplane:Selfheatingandshortchanneleffects,Solid StateElectron,vol.48,pp.907917,2004. [10] J. Pretet,S. Monfray,S. CristoloveanuandT. Skotnicki, Silicononnothing MOSFETs: performance,shortchanneleffects,andbackgatecoupling,IEEETrans.ElectronDevices,vol.51, no.2,pp.240244,Feb.2004 [11]M.Jurczak,T.Skotnicki,M.Paoli,B.Tormen,J.Martins,J.L.Regolini,D.Dutartre,P.Ribot, D. Lenoble, R. Pantel, and S. Monfray, SilicononNothing (SON)an innovative process for advancedCMOS,IEEETrans.ElectronDevices,vol.47,pp.21792187,Nov.2000 [12]T.Numata,T.Mizuno,T.Tezuka,J.Koga,andS.Takagi,Controlofthresholdvoltageand shortchanneleffectsinultrathinstrainedSOICMOSdevices,IEEETrans.ElectronDevices,vol. 52,no.8,pp.17801786,Aug.2005

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Chapter 9
Device Design Optimization
9.1 Introduction
In chapter 7 and chapter 8, short channel effects degrading device performance of sub100nm fully depleted SOI devices were discussed. Device design parameters to control the threshold voltageandsuppressshortchanneleffectswerestudied.Themajordesignparametersaresilicon bodythickness,siliconbodydoping,buriedoxidethickness,substratedoping,backgatebiasand gate workfunction. The above parameters can be adjusted to achieve the desired device performance in terms of reduced offstate leakage or increased drive current or steep subthreshold slope or reduced draininduced barrier lowering. In this chapter, device design parameters for devices with gate lengths 60nm, 45nm, 30m, 15nm and 10nm are specified. The designspecificationsaresetinordertomeettheITRSHighPerformanceLogicTechnology(ITRS 2005) target for Ion/Ioff ratio. If instead of Ion/Ioff ratio, the performance target is DIBL or subthreshold slope, then the device parameters would need to be adjusted and would be different.However,forthiswork,andforthedevicesbasedonepitaxialburiedoxide,devicesare designedwithregardstomeetingtheIon/IoffratiospecificationbyITRS.

9.2 60nm Gate Length

For60nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare1E8A/umand0.9mA/umrespectively.ItwasshowninChapter5,thatthetargetsare metfor60nmdevicewithouttheneedforgroundplane.Thus,finaldevicedesignparametersfor thedeviceare, 1. 2. 3. SiliconbodythicknessTSi=7nm BuriedoxidethicknessTBox=15nm Undopedsiliconbody

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4. 5. 6.

Lowlydopedsubstrate1E15cm3withoutgroundplane Backgatebiasof0V Gateworkfunctionof4.53eV.

Figure91plotsIdVgcurvesfordevicewithaboveparametersfordifferenttemplatethicknesses. Foranytemplatethickness,theoffstatecurrentvalue,IoffislessthantheITRSspecifiedvalue.

ITRS Ioff 1E-8

Figure91IdVgplotforLg=60nmfordifferenttemplatethicknesses.Theparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um. The offstate leakage current for different template thicknesses is less than the ITRS specified value by almost an order of magnitude or 89% for 5nm thick template, 93% for 4nm thick template,96%for3nmthicktemplateand97.6%for2nmthicktemplate.ThedrivecurrentorIon valuesforeithertemplatethicknessislargerthantheITRStargetvalueof0.9mA/um.

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Table 91 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x 107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V. Table91Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor60nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIonspecificationsare1E8A/um and0.9mA/um Template 5nm 4nm 3nm Vt (V) 0.23 0.24 0.25 Ioff(A/um) 1.10E-09 7.10E-10 4.40E-10 Ion (mA/um) 0.961 0.955 0.947 SS (mV/decade) 79.1 76.5 73.9 DIBL (mV) 45.4 42.3 39.6

2nm 0.26 2.60E-10 0.937 72.1 36.4 From Table 91 it is inferred that for the design parameters listed above, the average threshold voltage is 0.24V, subthreshold swing is 75mV/decade and DIBL is 41mV. While the threshold voltageislowenoughandsoisDIBL,thesubthresholdswingseemsalittletoofarofffromthe ideal value of 60mV/decade at room temperature. However, device has been designed to meet theIon/Ioffrequirementsandnotspecificallyforsubthresholdslope.Ifsubthresholdslopeneeds tobeimproved,thedevicecanbereengineered. Forexample,iftheworkfunctionisincreasedfrom4.53eVto4.7eV,agroundplaneincludedin thesubstrateunderthegateandbackgatevoltagedecreasedfrom0Vto1V,keepingallother parameters the same, the subthreshold swing for the 5nm thick template case, reduces from 79.1mV/decade to 70mV/decade and Ioff reduces from 1.1E9 A/um to 1.4E15 almost by five orders of magnitude. However, the demerit is the reduction in Ion from 0.96mA/um to 0.3mA/um For the ground plane device with 4.7eV workfunction, as the back gate voltage is decreasedfrom0.2Vto1V,subthresholdswingimprovesfrom73mV/decadeto70mV/decade andIofffallsfrom5E14A/umto1.4E15A/um.Thedevicedesignparameterslistedintheabove tablethereforerepresentsonesetofsolutionsdesignedfordevicetomeetspecificallytheIon/Ioff ratiospecification.

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9.3 45nm Gate Length

For45nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare3E8A/umand0.98mA/umrespectively.ItwasshowninChapter5,thattheIon/Ioff ratiotargetismetfor45nmdevicewithouttheneedforgroundplaneforalltemplatethicknesses except 5nm. A groundplane structure is, therefore, included to suppress the short channel effectsandmeettargetvaluesforalltemplatethicknesses.Thus,finaldevicedesignparameters forthedeviceare, 1. 2. 3. 4. 5. 6. SiliconbodythicknessTSi=7nm BuriedoxidethicknessTBox=15nm Undopedsiliconbody Lowlydopedsubstrate1E15cm3withgroundplanedoped5E18cm3 Backgatebiasof0.2V Gateworkfunctionof4.53eV.

Figure92plotsIdVgcurvesfordevicewithaboveparametersfordifferenttemplatethicknesses. Foranytemplatethickness,theoffstatecurrentvalue,IoffislessthantheITRSspecifiedvalue. The offstate leakage current for different template thicknesses is less than the ITRS specified value by almost an order of magnitude or 95% for 5nm thick template, 96.4% for 4nm thick template,97.7%for3nmthicktemplateand98.7%for2nmthicktemplate.Thedrivecurrentor IonvaluesforeithertemplatethicknessislargerthantheITRStargetvalueof0.98mA/um. Table 91 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x 107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V. From Table 91 it is inferred that for the design parameters listed above, the average threshold voltage is 0.265V, subthreshold swing is 86.4mV/decade and DIBL is 62.5mV. As was the case with60nmdevice,whilethethresholdvoltageislowenoughandsoisDIBL,thesubthreshold swingseemsalittletoofarofffromtheidealvalueof60mV/decadeatroomtemperature.

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ITRS Ioff 3E-8A/um

Figure92IdVgplotforLg=45nmfordifferenttemplatethicknesses.Theparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um. However, device has been designed to meet the Ion/Ioff requirements and not specifically for subthresholdslope.Ifsubthresholdslopeneedstobeimproved,thedevicecanbereengineered. Table92Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor45nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIonspecificationsare3E8A/um and0.98mA/um Template 5nm 4nm 3nm 2nm Vt (V) 0.25 0.26 0.27 0.28 Ioff(A/um) 1.5E-09 1.1E-09 6.9E-10 3.9E-10 Ion (mA/um) 1.006 1.005 1.003 0.995 SS (mV/decade) 89.5 87.2 85.2 83.7 DIBL (mV) 73.9 67.6 59.1 49.2

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For example, if the workfunction is increased from 4.53eV to 4.7eV, and backgate voltage decreasedfrom 0.2V to1V, keepingall other parameters the same, the subthreshold swing for the 5nm thick template case, reduces from 89.5mV/decade to 76.87mV/decade and Ioff reduces from 1.5E9 A/um to 6.7E14 almost by five orders of magnitude. However, the demerit is the reductioninIonfrom1mA/umto0.764mA/um.Asthebackgatevoltageisdecreasedfrom0.2V to 1V, subthreshold swing improves from 85mV/decade to 76.87mV/decadeand Iofffallsfrom 2.7E12A/umto6.7E14A/um. Thedevicedesignparameterslistedintheabovetablethereforerepresentsonesetofsolutions designedfordevicetomeetspecificallytheIon/Ioffratiospecification

9.4 30nm Gate Length

For30nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare5E8A/umand1.09mA/umrespectively.ItwasshowninChapter5,thattheIon/Ioff ratio target is not met for 30nm device without ground plane for any template thickness. A groundplane structure is, therefore, included to suppress the short channel effects and meet targetvaluesforalltemplatethicknesses.Thus,finaldevicedesignparametersforthedeviceare, 1. 2. 3. 4. 5. 6. SiliconbodythicknessTSi=7nm BuriedoxidethicknessTBox=15nm Undopedsiliconbody Lowlydopedsubstrate1E15cm3withgroundplanedoped5E18cm3 Backgatebiasof0.85V Gateworkfunctionof4.53eV.

Figure93plotsIdVgcurvesfordevicewithaboveparametersfordifferenttemplatethicknesses. Foranytemplatethickness,theoffstatecurrentvalue,IoffislessthantheITRSspecifiedvalue. The offstate leakage current for different template thicknesses is less than the ITRS specified value by 54% for 5nm thick template,62% for4nm thick template, 74% for3nm thick template and87%for2nmthicktemplate.ThedrivecurrentorIonvaluesforeithertemplatethicknessis largerthantheITRStargetvalueof1.09mA/um.

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ITRS Ioff 5E-8A/um

Figure93IdVgplotforLg=30nmfordifferenttemplatethicknesses.Theparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Table 93 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x 107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V. Table93Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor30nmdevice designedtomeetITRStargetforIon/Ioffratio.ITRSIoffandIonspecificationsare5E8A/um and1.09mA/um Template 5nm 4nm 3nm 2nm Vt (V) 0.20 0.20 0.21 0.22 Ioff(A/um) 2.30E-08 1.90E-08 1.30E-08 6.40E-09 Ion (mA/um) 1.195 1.194 1.191 1.178 SS (mV/decade) 116.5 112.8 106.9 100.0 DIBL (mV) 146.2 144.1 135.6 121.6

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From Table 93 it is inferred that for the design parameters listed above, the average threshold voltage is 0.2V, subthreshold swing is 109mV/decade and DIBL is 137mV. While the threshold voltageislowenough,thesubthresholdswingisreasonable.ForDIBL,avaluelessthan100mV isgenerallyconsideredagoodvalue. As before, the device can be reengineered to further reduce DIBL and improve subthreshold swing. For example, if the silicon body thickness reduced from 7nm to 5nm, workfunction increasedfrom4.53eVto4.7eVandbackgatevoltagedecreasesfrom0.85Vto1V,subthreshold swing for 5nm thick template case reduces from 116.5mV/decade to 96.5mV/decade and DIBL improvesfrom146.2mVto119mV.Thus,devicedesignparametersspecifiedinabovetablerefer toonlyonepossiblesetofsolutionsdesignedfordevicetomeettheIon/Ioffratiotarget.

Figure 94 IdVg plot for Lg=30nm for 5nm and 4nm thick template at Tbox=15nm and 10nm. TheparameteronxaxisisgatevoltageinvoltsandonyaxisisdraincurrentinA/um. It was shown in chapter 8 that for ground plane device, a lowk buried oxide yields slightly largerDIBLandthereforelargeroffstateleakagecurrentatBOXthicknessbelowacriticalvalue.

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Since,thesubstratein60nm,45nmand30nmdevicesislowlydoped1E15cm3asagainst1E18cm
3

usedforsimulationsinchapter8,thecriticalBOXthicknessoccursatlessthan15nm.Therefore,

at Tbox=10nm, a thinner template thickness should yield larger offstate current by virtue of smaller effective BOX permittivity. Figure 94 plots IdVg curves for 5nm and 4nm thick templatesforTBox=15nmand10nm.Themetalworkfunctionis4.53eVandbackgatevoltageis 0.2V.ItisobservedthatwhileatTbox=15nm,5nmthicktemplateyieldslargerIoff,atTbox=10nm,it yields lower Ioff compared to 4nm thick template. Therefore, if the 30nm device is engineered with a 10nm BOX thickness, ITRS Ioff requirement will be met with ease however, a thinner templatewouldyieldalargeroffstateleakagecurrent.AlsotobenotedfromFigure94isthat, keepingallotherdeviceparametersthesame,Tbox=10nmresultsinasteepersubthresholdslope andsmallerDIBLbutatthecostofslightlyreduceddrivecurrent.

9.5 25nm Gate Length

For25nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare1.7E7A/umand1.48mA/umrespectively.ItwasshowninChapter5,thattheIon/Ioff ratio target is not met for 25nm device without ground plane for any template thickness. A groundplane structure is, therefore, included to suppress the short channel effects and meet targetvaluesforalltemplatethicknesses.Thus,finaldevicedesignparametersforthedeviceare, 1. 2. 3. 4. 5. 6. SiliconbodythicknessTSi=7nm BuriedoxidethicknessTBox=15nm Undopedsiliconbody Lowlydopedsubstrate1E15cm3withgroundplanedoped5E18cm3 Backgatebiasof0.7V Gateworkfunctionof4.8eV.

Figure95plotsIdVgcurvesfordevicewithaboveparametersfordifferenttemplatethicknesses. Foranytemplatethickness,theoffstatecurrentvalue,IoffislessthantheITRSspecifiedvalue. The offstate leakage current for different template thicknesses is less than the ITRS specified value by 70% for 5nm thick template,77% for4nm thick template, 87% for3nm thick template

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and95%for2nmthicktemplate.ThedrivecurrentorIonvaluesforeithertemplatethicknessis however smaller than the ITRS target value of 1.48mA/um. Nevertheless the Ion/Ioff target is met.

ITRS Ioff 1.7E-7A/um

Figure95IdVgplotforLg=25nmfordifferenttemplatethicknesses.Theparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Table 94 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x 107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V. From Table 94 it is inferred that for the design parameters listed above, the average threshold voltageis0.25V,subthresholdswingis160mV/decadeandDIBLis278mV.Whilethethreshold voltage is low enough, the subthreshold swing is large. For DIBL, a value less than 100mV is generally considered a good value. However, for 25nm gate length device, this DIBL value is veryreasonable.

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Table94Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor25nmdevice designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 1.7E7 A/umand1.48mA/um Template 5nm 4nm 3nm 2nm The above set of device design parameters meets the Ion/Ioff target. However, this represents onlyoneoutofseveralpossibledevicedesigns.Discussedbelowareotherdevicedesignoptions. I.TSi=7nm,TBox=10nm,Workfunction=4.6eV If the Workfunction is 4.6eV and BOX thickness is 15nm, then the ITRS target for 5nm thick template is not met even with 1V bias on the backgate. In order to avoid doping the silicon body,theBOXthicknessmustbescaledkeepingtheWorkfunctionasthesame.WithM=4.6eV andTBox=10nm,thebackgatebiasneedstobeatleast0.2VwhichresultsinanIoffof6.2E8A/um andIonof1.17mA/um.Ifthebackgatebiasis0.1V,resultingIoffis1.1E7A/umwhichdoesnt meetthetarget.Thus,withTSi=7nm,TBox=10nm,andworkfunction=4.6eV,therangeofbackgate biasisVbg0.2V. II.TSi=7nm,TBox=10nmor15nm,Workfunction=4.7eV Iftheworkfunctionisincreasedto4.7eV,theITRStargetfor5nmthicktemplatecanbemetwith 15nmBOXthicknessunlikethecaseaboveforM=4.6eV.Howeverthisrequiresabackgatebias of Vbg0.8V.At Vbg=0.8V, resulting Ioff and Ion are 9.94E8A/um and 1mA/um respectively. If theworkfunctioniskeptthesame,andBOXthicknessisscaledto10nm,therangeonbackgate biasisincreasedtoVbg0Vwhichprovidesmoretunability.AsVbgisdecreasedfrom0Vto0.4V, Ioff reduces from 5.5E8A/um to 4E9A/um and Ion from 0.948mA/um to 0.825mA/um respectively. Vt (V) 0.22 0.23 0.26 0.30 Ioff(A/um) 5.1E-08 3.8E-08 2.1E-08 7.9E-09 Ion (mA/um) 0.789 0.787 0.776 0.755 SS (mV/decade) 172.1 165.6 155.8 145.6 DIBL (mV) 311.4 296.5 270.1 233.2

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III.TSi=7nm,TBox=10nmor15nm,Workfunction=4.8eV Iftheworkfunctionisincreasedto4.8eV,theITRStargetfor5nmthicktemplatecanbemetwith 15nmBOXthicknesswithabackgatebiasofVbg0.4V.AtVbg=0.4V,resultingIoffandIonare 1.2E7A/um and 0.834mA/um respectively. And at Vbg=0.7V, as shown in the table above, resulting Ioff and Ion are 5.1E8A/um and 0.789mA/um respectively. If the BOX thickness is scaled to 10nm, the target can be met at Vbg=0V resulting in Ioff and Ion as 1.5E8A/um and 0.707mA/umrespectively.

ITRS Ioff 1.7E-7A/um

Figure96IdVgplotforLg=25nmfortwodevicedesignparameters.TSi=7nmand5nmthick template for both. The parameter on xaxis is gatevoltage in volts and on yaxis is drain currentinA/um. Figure 96 plots IdVg curves for 5nm thick template for two device design conditions. For TBox=15nm and M=4.8eV, the backgate bias is adjusted to be 0.7V and for second case with TBox=10nm and M=4.6eV, Vbg is adjusted to be 0.3V so that both result in same Ioff of 3.5E 8A/um.Itisclearthat,forsameIoff,athinnerBoxthickness,TBox=10nmresultsinamuchsteeper subthresholdslopeandthereforelargerdrivecurrent.AmajorreasonforscalingBOXthickness

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is the improvement in subthreshold swing. However, a thin BOX also increases parasitic source/drain substrate capacitances and undermines that advantage of using SOI substrate. Withregardstothis,thedevicesolutionfor25nmgatelengthinvolves15nmBOXthickness.

Figure 97 IdVg plot for Lg=25nm for 5nm and 4nm thick template at Tbox=15nm and 10nm. TheparameteronxaxisisgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Figure 97 plots IdVg curves for 5nm and 4nm thick templates for TBox=15nm and 10nm. The metalworkfunctionis4.8eVandbackgatevoltageis0V.ItisobservedthatwhileatTbox=15nm, 5nm thick template yields larger Ioff, at Tbox=10nm, it yields lower Ioff compared to 4nm thick template.ThisisduetotheBOXpermittivityrolereversalbelowcriticalthicknessasdiscussedin chapter 8. Therefore, if the 25nm device is engineered with a 10nm BOX thickness, ITRS Ioff requirementwill be met with more ease fora thicker template layer by virtue of a higher BOX permittivity.

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9.6 15nm Gate Length

For15nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare2.9E7A/umand2.03mA/umrespectively.ItwasshowninChapter5,thattheIon/Ioff ratio target is not met for 15nm device without ground plane for any template thickness. A groundplane structure is, therefore, included to suppress the short channel effects and meet targetvaluesforalltemplatethicknesses.Itwasdiscussedinchapter8thatTBox<Lg/2isrequired forsubstantivereductionofDIBL.Keepingthisinview,6nmBoxthicknessischosen.However, sincethisisbelowthecriticalthickness,athinnertemplatewouldfinddifficulttomeettheITRS target. Also, silicon body thickness is reduced to 5nm to suppress short channel effects. Thus, finaldevicedesignparametersforthedeviceare, 1. 2. 3. 4. 5. SiliconbodythicknessTSi=5nm BuriedoxidethicknessTBox=6nm Undopedsiliconbody Lowlydopedsubstrate1E15cm3withgroundplanedoped5E18cm3 Backgate bias is adjusted to be 0.2V(5nm template), 0.6V(4nm template), 0.9V(3nm template,1V(2nmtemplate) 6. Gateworkfunctionof4.53eV.

Figure98plotsIdVgcurvesfordevicewithaboveparametersfordifferenttemplatethicknesses. Foranytemplatethickness,theoffstatecurrentvalue,IoffislessthantheITRSspecifiedvalue. The offstate leakage current for different template thicknesses is less than the ITRS specified value by 91% for 5nm thick template,85% for4nm thick template, 78% for3nm thick template and63%for2nmthicktemplate.ThedrivecurrentorIonvaluesforeithertemplatethicknessis however smaller than the ITRS target value of 2.03mA/um. Nevertheless the Ion/Ioff target is met. Table 95 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x

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107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V.

ITRS Ioff 2.9E-7A/um

Figure98IdVgplotforLg=15nmfordifferenttemplatethicknesses.Theparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Table95Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor15nmdevice designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 2.9E7 A/umand2.03mA/um Template 5nm 4nm 3nm 2nm Vt (V) 0.19 0.17 0.15 0.11 Ioff(A/um) 3.47E-08 5.57E-08 7.98E-08 1.36E-07 Ion (mA/um) 1.28 1.35 1.41 1.50 SS (mV/decade) 131.5 135.2 135.3 141.2 DIBL (mV) 221.8 230.3 242.7 255.2

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From Table 95 it is inferred that for the design parameters listed above, the average threshold voltageis0.16V,subthresholdswingis136mV/decadeandDIBLis237mV.Thethresholdvoltage islowenough.Thesubthresholdswingisgoodfor15nmdeviceandDIBLissmallenough.The above set of device design parameters meets the Ion/Ioff target. However, this represents only oneoutofseveralpossibledevicedesigns.Discussedbelowareotherdevicedesignoptions. I.TSi=5nm,TBox=6nm,Workfunction=4.53eV If the Workfunction is 4.53eV and BOX thickness is 6nm, then the ITRS target for 5nm thick templateiswithbackgatebiasofVbg<0V.TheITRStargetforIoffandIonare2.9E7A/umand 2.03mA/um. As Vbg is decreased from 0.1V to 0.6V, Ioff decreases from 6.4E8A/um to 3.2E 9A/um and Ion from 1.35mA/um to 1.02mA/um. The subthreshold swing improves from 139mV/decadeto116.5mV/decade.For4nmthicktemplate,thebackgatebiasneedstobeVbg< 0.4V. For 3nm thick template, Vbg<0.8V and for 2nm thick template, Vbg<1V. However, at the samevalueofbackgatebias,athinnertemplateyieldslargeroffstateleakagecurrent.Therefore, thedeviceperformancespecificationsareeasiertomeetwiththickertemplate. For 4nm thick template case, as Vbg is decreased from 0.4V to 1V, Ioff decreases from 1.4E 7A/um to 7.8E9A/um and Ion from 1.46mA/um to 1.15mA/um. The subthreshold swing improvesfrom141mV/decadeto119mV/decade.For3nmthicktemplatecase,asVbgisdecreased from 0.8V to V, Ioff decreases from 1.1E7A/um to 5.3E8A/um and Ion from 1.46mA/um to 1.37mA/um.The subthreshold swingimproves from 135mV/decade to134mV/decade. For 2nm thick template case, Vbg=1V yields Ioff of 1.36E7A/um, Ion of 1.5mA/um and subthreshold swingof141,2mV/decade. The Ioff target is met easily but Ion values are smaller than the desired value. Nevertheless, Ion/Iofftargetismet. II.TSi=5nm,TBox=6nm,Workfunction=4.6eV Whentheworkfunctionisincreasedto4.6eV,theconstraintonbackgatevoltageislessharshfor samevalueofIoff.WithM=4.6eV,thebackgatebiasneedstobe,Vbg<0Vfor5nmthicktemplate, Vbg<0.2Vfor4nmthicktemplate,Vbg<0.5Vfor3nmthicktemplateandVbg<0.7Vfor2nmthick template. For 5nm thick template, as Vbg decreases from 0V to 0.8V, Ioff reduces from 3.9E

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8A/um to2.6E10A/um, Ion from 1.22mA/um to 0.719mA/um and subthreshold swing from 139mV/decadeto114mV/decade.For4nmthicktemplate,Vbg=0.4vresultsinIoffof4.7E8A/um, Ion of 1.26mA/um and subthreshold swing of 137mV/deacde. For 3nm thick template, as Vbg decreasesfrom0.5Vto0.8V,Ioffreducesfrom1.6E7A/umto3.6E8A/um,Ionfrom1.39mA/um to 1.25mA/um and subthreshold swing from 142mV/decade to 135mV/decade. For 2nm thick template,Vbg=0.9Vand1Vresultin1E7A/umand6.4E8A/umofoffstateleakagecurrentboth meetingtheITRStarget.

ITRS Ioff 2.9E-7A/um

Figure 99 IdVg plot for Lg=15nm for 4nm thick template. TSi=5nm, TBox=6nm, M=4.53eV. TheparameteronxaxisisgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Figure99plotsIdvgcurvesforM=4.53eVand4nmtemplatethicknessforfourdifferentback gatevoltages.WhileIofftargetisnotmetatVbg=0.2V,itismetwithmosteaseatVbg=1V.Figure 910plotsIdVgcurvesforM=4.53eVandVbg=1Vfordifferenttemplatethicknesses.Itverifies the fact that at TBox=6nm, keeping all other parameters the same, a thicker template yields a smallerIoffbyvirtueofahigherBOXpermittivity.

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ITRS Ioff 2.9E-7A/um

Figure 910 IdVg plot for Lg=15nm with TSi=5nm, TBox=6nm, M=4.53eV and Vbg=1V. The parameteronxaxisisgatevoltageinvoltsandonyaxisisdraincurrentinA/um. Thus, several device design parameters meeting the target have been discussed. The important thingtonoteisthatIon/Ioffratiotargetismetwithouttheneedforsiliconchanneldoping.With BOX thickness as thin as 6nm, the workfunction requirement is 4.53eV or 4.6eV unlike a high valueas4.8eVlikefor25nmdevice.

9.7 10nm Gate Length

For10nmgatelengthdevice,theITRStargetvaluesforsubthresholdleakagecurrentanddrive currentare3.7E7A/umand2.18mA/umrespectively.ItwasshowninChapter5,thattheIon/Ioff ratio target is not met for 10nm device without ground plane for any template thickness. A groundplane structure is, therefore, included to suppress the short channel effects and meet targetvaluesforalltemplatethicknesses.Itwasdiscussedinchapter8thatTBox<Lg/2isrequired for substantive reduction of DIBL. This means that BOX thickness needs to be as thin as 5nm.

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Andsincethisisbelowthecriticalthickness,athinnertemplatewouldfinddifficulttomeetthe ITRStarget.Siliconbodythicknessneedstobeasthinas5nmtosuppressshortchanneleffects. Thus,finaldevicedesignparametersforthedeviceare, 1. 2. SiliconbodythicknessTSi=5nm Buried oxide thickness TBox=6nm ( for 5nm and 4nm thick template) and 4nm (for 3nm and2nmthicktemplate) 3. 4. 5. Undopedsiliconbody Lowlydopedsubstrate1E15cm3withgroundplanedoped5E18cm3 Backgate bias is adjusted to be 0.4V(5nm template), 1V(4nm template), 0.3V(3nm template,0.7V(2nmtemplate) 6. Gate workfunction is adjusted to be 4.8eV(5nm template), 4.98eV(4nm template), 5.3eV(3nmtemplate)and5.45eV(2nmtemplate)

ITRS Ioff 3.7E-7A/um

Figure911IdVgplotforLg=10nmfordifferenttemplatethicknessesTheparameteronxaxis isgatevoltageinvoltsandonyaxisisdraincurrentinA/um.

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Figure 911 plots IdVg curves for device with above parameters for different template thicknesses. For any template thickness, the offstate current value, Ioff is less than the ITRS specifiedvalue. The offstate leakage current for different template thicknesses is less than the ITRS specified value by 70% for 5nm thick template,77% for4nm thick template, 87% for3nm thick template and95%for2nmthicktemplate.ThedrivecurrentorIonvaluesforeithertemplatethicknessis however smaller than the ITRS target value of 2.1.8mA/um. Nevertheless the Ion/Ioff target is met. As can be observed the device design parameters are different for different thicknesses of template. When template is 5nm thick,the effectiveBOX permittivity is28.0and ITRS target is met with a good subthreshold slope. However, as template thickness reduces, increase in BOX permittivity makes it harder to achieve the target. This is the reason why 5nm and 4nm thick templatesrequireTBox=5nmwhereas3nmand2nmthicktemplatesneedTBox=4nm.Eventhegate workfunctionincreasesfrom4.8eVfor5nmthicktemplateto5.3eVfor2nmthicktemplate. Table 96 specifies the threshold voltage, Ioff, Ion, subthreshold swing and DIBL values. The definitionofthresholdvoltageusedisthegatebiasthatresultsinadraincurrent,IDS=(W/Lmet)x 107 A. DIBL is measured as difference in threshold voltages at drain bias of 0.1V and 1V. Subthresholdswingismeasuredatadrainbiasof1V. Table96Thresholdvoltage,Ioff,Ion,SubthresholdswingandDIBLvaluesfor10nmdevice designed to meet ITRS target for Ion/Ioff ratio. ITRS Ioff and Ion specifications are 3.7E7 A/umand2.18mA/um Template 5nm 4nm 3nm 2nm Vt (V) 0.28 0.29 0.42 0.48 Ioff(A/um) 1.80E-08 2.55E-08 1.73E-08 1.38E-08 Ion (mA/um) 0.785 0.652 0.228 0.122 SS (mV/decade) 160.0 186.5 233.1 247.0 DIBL (mV) 360 460 480 490

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From Table 96 it is inferred that for the design parameters listed above, the average threshold voltage is 0.36V, subthreshold swing is 206mV/decade and DIBL is 447mV. The subthreshold swing and DIBL are large. A good way to improve those wouldbe to dope the silicon channel which however is not a good option because of dopant induced Vt fluctuation and mobility degradation.TheabovesetofdevicedesignparametersmeetstheIon/Iofftarget.However,this represents only one out of several possible device designs. Discussed below are other device designoptions. I.TSi=5nm,TBox=5nm,5nmTemplateThickness Figure 912 plots IdVg curves for 5nm template thickness for three different values of gate workfunction. Silicon body and BOX thickness is 5nm. Backgate bias is 0.4V. If the gate workfunctionincreasesfrom4.6eVto4.8eV,offstateleakagecurrentdropsfrom2.9E7A/umto 1.8E8A/umandIonfrom1.32mA/umto0.785mA/um.Withworkfunctionof4.8eV,whileVbg= 0.2V yields 6.5E8A/um of leakage current, Vbg=0.4V reduces it to 1.8E8A/um. Subthreshold swingdegradesslightlyfrom178.6mV/decadeto160mV/decade.

ITRS Ioff 3.7E-7A/um

Figure912IdVgplotforLg=10nmwithTSi=5nm,TBox=5nm,Vbg=0.4VandvariableM.The parameteronxaxisisgatevoltageinvoltsandonyaxisisdraincurrentinA/um.

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II.TSi=5nm,TBox=5nm,4nmTemplateThickness WithM=4.8eV,Vbg=0.8VresultsinIoff=5E7A/umanddoesntmeetthetarget.Whenbackgate voltageisreduced toVbg=1V, Ioff reduces to2.1E7A/umand resulting Ionis 1.13mA/um. The ITRSIofftargetisalsometwithM=5.0eVandVbg<0.4VuntilIondecreasesbyalargeamount and ITRS Ion/Ioff ratio target is not met. The chosen set of device parameters however are M=4.98eVandVbg=1V. II.TSi=5nm,TBox=4nm,3nmTemplateThickness If BOX thickness is retained at 5nm, the gateworkfunction needs to be increased to more than 5.3eV.For(M,Vbg)={5.3eV,1V},Ioffis3.6E8A/umandIonis0.289mA/um.TheIon/Ioffratiois 8E3A/A. If M is increased to 5.44eV and Vbg is kept the same, resulting Ioff and Ion are 1.2E 8A/umand0.123mA/umrespectively.TheIon/Ioffratioincreasesto1E4A/A.IfMisincreased further,onewouldexpectadropinIoffandthereforeriseinIon/Ioffratio.However,Iondrops byalargeamountbyvirtueofincreaseinthresholdvoltagesotheIon/Ioffratioisnotimproved. ForM=5.5eVandVbg=1V,Ioffreducesto7.4E9A/umbutIonbecomesameager7.8E5A/um.The resultingIon/Ioffratioisthus9.8E3A/AsmallerthanthatforM=5.44eVcase.Inordertoachieve alargerIon/Ioffratio,theBOXthicknessisreducedto4nmandsoforsametemplatethicknessof 2nm, the BOX permittivity is increased which provides more ease in achieving the target. At TBox=4nmwhile(M,Vbg)={5.3eV,0.3V}resultsin{Ioff,Ion}={1.7E8A/um,0.228mA/um},(M, Vbg) = {5.4eV, 0.3V} results in {Ioff, Ion} = {7.4E9A/um, 0.114mA/um. The Ion/Ioff ratio is 1.3E4A/Afortheformerand1.5E4A/Aforthelatter. III.TSi=5nm,TBox=4nm,2nmTemplateThickness AtTBox=4nmandM=5.45eV,asVbgisreducedfrom0.7Vto0.9V,Ioffreducesfrom1.4E8A/um to 4.3E9A/um, Ion from 0.122mA/um to 8.2E5A/um and consequently Ion/Ioff ratio increases from8.8E3A/Ato1.9E4A/A. Thedevicedesignconsiderationsfor10nmgatelengthdevicewerediscussed.Eventhoughthe ITRSIon/Ioffratiotargetsaremetwithundopedsiliconbody,thesubthresholdslopeandDIBL arelarge.Someimprovementcanresultinbydopingthesiliconchannel.Howevereventhen,the device under consideration would perform better than standard SOI device. This is because, at suchthinBOXthicknessasneededfor10nmdevice,ahighkBOXyieldslesserDIBLandgreater easeinmeetingthetargetoffstateleakagevalues.

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9.8 Meeting ITRS Ion/Ioff Specification

The goal of device modeling was to design the device so that ITRS High Performance Logic Technologyspecificationsaremetateverygatelength.Figure913plotsIon/Ioffratioasspecified byITRSandasdesigned,fordifferentgatelengths.Ithasbeenshowninprevioussectionsthat ITRS specifications can be met for any gate length with undoped silicon body and for any template thickness. Because, 15nm and 10nm devices require an ultrathin BOX with thickness belowcriticalthicknessasdescribedinchapter8,athickertemplateyieldsalargerIon/Ioffratio.
1.0E+08 5nm 1.0E+07 4nm 3nm 2nm 1.0E+06

Ion/Ioff

ITRS'05 HP Logic

1.0E+05

1.0E+04

1.0E+03 10nm 15nm 25nm 30nm 45nm 60nm

Channel Length (nm)

Figure913ITRSexpectedandSimulatedIon/Ioffratioversuschannellength Figure 914 shows an alternate representation of Ion/Ioff ratios versus channel length. The verticalbarscorrespondingtodifferenttemplatethicknessesarelargerthanthatcorresponding to the ITRS specification suggesting that the target is met for every template thickness and at everygatelength.For15nmand10nmgatelengths,athinnertemplateresultsinsmallerIon/Ioff ratio.Table97summarizesdevicedesignparametersforallgatelengthsasdiscussedindetail inabovesections.

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1.0E+08 5nm 1.0E+07 4nm 3nm 2nm 1.0E+06

Ion/Ioff

ITRS'05 HP Logic

1.0E+05

1.0E+04

1.0E+03 10 15 25 30 45 60

Channel Length (nm)

Figure914ITRSexpectedandSimulatedIon/Ioffratioversuschannellength Table97SummaryofdevicedesignparameterstomeetITRSHPLogicIon/Ioffspecification for different channellengths. Except for 60nm, allother gatelength devices employ ground plane.Substratedopingis1E15cm3andp+groundplaneimplantis5E18cm3 Channel SiliconBody BOX Body Gate Backgate LengthLg ThicknessTSi Thickness Doping Workfunction BiasVbg(V) (nm) (nm) TBox(nm) (cm3) M(eV) 60 45 30 25 15 7 7 7 7 5 15 15 15 15 6 4.53 4.53 4.53 4.80 4.53 0.00 0.20 0.85 0.70 5nm:0.2V 4nm:0.6V 3nm:0.9V 2nm:1.0V 5nm:0.4V 4nm:1.0V 3nm:0.3V 2nm:0.7V Undoped Undoped Undoped Undoped Undoped

10

5nm:5 4nm:5 3nm:4 2nm:4

5nm:4.80 4nm:4.98 3nm:5.30 2nm:5.45

Undoped

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9.9 Conclusion
In this chapter it has been shown that epitaxialoxide based SOI device can meet ITRS Ion/Ioff targetdownto10nmchannellength.Thedevicedesignparametersforeachgatelengthdevice werediscussed.Whileburiedoxideis15nmthickforuntil25nmgatelengthdevice,itbecomes as thin as 4nm for 10nm gatelength device. Silicon body thickness is small to make sure full depletion and suppressed DIBL through silicon body. It becomes as thin as 5nm for 15nm and 10nm gatelength devices. The silicon body is undoped for all gatelengths. This avoids the problemsassociatedwithveryhighchanneldoping.Thegateworkfunctionis4.53eVforuntil 30nmgatelengthandincreasesto5.45eVfor10nmdevice.Aslongastheburiedoxideisthick, 15nm,athinnertemplatematerialresultsinalargerIon/Ioffratio.However,for10nmand15nm devices, that require, BOX thickness below critical thickness of about 10nm, a thinner template material gets hard to meet the ITRS target with. Thus, while highk template oxide is not a favorableoptionatthickBOX,itprovidesbetterdeviceperformanceandscalabilityatthinBOX. Nevertheless,ithasbeenshownthatdespitehighktemplate,ITRSIon/Iofftargetcanbemetfor anychannellength.

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Chapter 10
Conclusion and Future Work
10.1 Conclusion
The goal of this work was to demonstrate that highk template oxide wont hurt device performance significantly and that ITRS Ion/Ioff specifications can be met for any gate length. TwodimensionaldevicemodelinghasshownthatFloatingEpitaxybasedSOIdevicescanmeet ITRSIon/Ioffspecificationsdownto10nmchannellengthforanythicknessoftemplatematerial between2nmand5nm..Thishoweverrequiresappropriatedevicedesign.Whilegroundplaneis essential to suppress short channel effects associated with buried oxide; silicon body thickness, backgate bias and gate workfunction are important device design parameters that control thresholdvoltage.Buriedlayerengineeringisanotheroptionforreducingshortchanneleffects.It requires appropriate selection and modeling of these parameters to meet the ITRS target and ensuringgoodsubthresholdslopeandsmallDIBLatthesametime. Amajorconclusionaspartofthisworkisalsothat,whilehighkBOXcausesmoreDIBLatthick BOX,itslightlyhelpsdeviceperformanceatthinBOXbyresultinginlesserDIBL.Therefore,for very small devices, in sub15nm regime, which require ultra thin buried oxides, a high permittivitywillbeofmoreadvantage.Thisisbecause;ahighpermittivityBOXismorecapable ofcausingfieldlinesfromdraintoterminateonsubstrateratherthanchanneltherebyreducing DIBLthroughsiliconbody. ItcanbeconcludedthatfutureSOIdevicesbasedonepitaxialburiedoxideasdiscussedinthis work will not only guarantee expected device performance but will also solve much of the problemsassociatedwithSOImanufacturingtodayfromeaseoffabricationandcostperspective.

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10.2 Future Work

Now that the device modeling has been done, devices will be fabricated on wafer samples availableofthefloatingepitaxysubstrate.Devicesofvaryinggatelengthandtemplatethickness willbefabricated.Devicecharacterizationandmeasurementswillrevealthedeviceperformance fromperspectiveofshortchanneleffectsandIon/Ioffratio.

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