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onsemi and       and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
MMDF3N06HD
Preferred Device

Advance Information
Power MOSFET
3 Amps, 60 Volts
N−Channel SO−8, Dual
These miniature surface mount MOSFETs feature low RDS(on) and http://onsemi.com
true logic level performance. Dual MOSFET devices are designed for
use in low voltage, high speed switching applications where power 3 AMPERES
efficiency is important. Typical applications are dc−dc converters, and
power management in portable and battery powered products such as 60 VOLTS
computers, printers, cellular and cordless phones. They can also be RDS(on) = 100 m

used for low voltage motor controls in mass storage products such as
disk drives and tape drives. N−Channel
• Low RDS(on) Provides Higher Efficiency and Extends Battery Life D D
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
G G
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature S S
• Mounting Information for SO−8 Package Provided

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) MARKING

DIAGRAM
Rating Symbol Value Unit
Drain−to−Source Voltage VDSS 60 Vdc
Gate−to−Source Voltage − Continuous VGS ± 20 Vdc SO−8, Dual
D3N06
Drain Current − Continuous @ TA = 25°C ID 3.3 Adc 8 CASE 751
LYWW
IDM 16.5 Apk STYLE 11
Source Current − Continuous @ TA = 25°C IS 1.7 Adc 1
Total Power Dissipation @ TA = 25°C PD 2.0 Watts
(Note 1.) L = Location Code
Y = Year
Operating and Storage Temperature Range TJ, Tstg − 55 to °C
WW = Work Week
150
Single Pulse Drain−to−Source Avalanche EAS 105 mJ
Energy − Starting TJ = 25°C PIN ASSIGNMENT
(VDD = 60 Vdc, VGS = 5.0 Vdc,
VDS = 32 Vdc, IL = 15 Apk, L = 10 mH, Source−1 Drain−1
1 8
RG = 25 Ω)
Gate−1 2 7 Drain−1
Thermal Resistance − Junction−to−Ambient RθJA 62.5 °C/W
Source−2 3 6 Drain−2
Maximum Lead Temperature for Soldering TL 260 °C
Purposes, 1/8″ from case for 10 seconds Gate−2 4 5 Drain−2
1. Mounted on G10/FR4 glass epoxy board using minimum recommended Top View
footprint.

ORDERING INFORMATION

Device Package Shipping

MMDF3N06HDR2 SO−8 2500 Tape & Reel

Preferred devices are recommended choices for future use

This document contains information on a new product. Specifications and information and best overall value.
herein are subject to change without notice.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

September, 2004 − Rev. XXX MMDF3N06HD/D
 MMDF3N06HD

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 − −

Zero Gate Voltage Drain Current IDSS µAdc

(VDS = 48 Vdc, VGS = 0 Vdc) − 0.001 1.0
(VDS = 48 Vdc, VGS = 0 Vdc, TJ = 125°C) − 0.05 25
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS − 12 100 nAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 0.25 mAdc) 1.0 − −

Static Drain−to−Source On−Resistance RDS(on) m

(VGS = 10 Vdc, ID = 3.3 Adc) − 67.5 100
(VGS = 4.5 Vdc, ID = 2.5 Adc) − 82.5 200
Forward Transconductance gFS Mhos
(VDS = 15 Vdc, ID = 1.5 Adc) − 7.5 −

DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 442 618 pF
Output Capacitance (VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss − 97.6 137
f = 1.0 MHz)
Transfer Capacitance Crss − 24.4 34.2

SWITCHING CHARACTERISTICS (Note 3.)

Turn−On Delay Time td(on) − 10.6 22.1 ns
Rise Time (VDD = 30 Vdc, ID = 3.3 Adc, tr − 15.9 31.8
VGS = 4.5
4 5 Vdc,
Vdc
Turn−Off Delay Time RG = 30 Ω) td(off) − 23.8 47.6
Fall Time tf − 14.7 29.4
Turn−On Delay Time td(on) − 7.0 14 ns
Rise Time (VDD = 15 Vdc, ID = 3.0 Adc, tr − 4.8 9.6
Vdc
VGS = 10 Vdc,
Turn−Off Delay Time RG = 9.1 Ω) td(off) − 32.4 64.8
Fall Time tf − 14.2 28.4
Gate Charge QT − 14.5 29 nC
(S Figure
(See Fi 8)
(VDS = 30 Vdc, ID = 3.3 Adc, Q1 − 1.8 −
VGS = 10 Vdc) Q2 − 3.5 −
Q3 − 3.75 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage VSD Vdc
(IS = 1.7 Adc, VGS = 0 Vdc) − 0.78 1.2
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125°C) − 0.65 −
Reverse Recovery Time trr − 27.9 − ns
(IS = 1.7
1 7 Adc,
Ad VGS = 0 Vdc,
Vd
ta − 23 −
dIS/dt = 100 A/µs)
tb − 4.9 −
Reverse Recovery Stored Charge QRR − 0.038 − µC
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.

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TYPICAL ELECTRICAL CHARACTERISTICS

6.0 6.0
VGS = 10 V 3.3 V 3.1 V
VDS ≥ 10 V
6.0 V 3.5 V
5.0 TJ = 25°C 5.0
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

4.5 V 3.7 V
4.3 V 2.9 V
4.0 3.9 V 4.0 100°C
4.1 V

3.0 3.0 25°C

2.7 V

2.0 2.0 TJ = −55°C

2.5 V
1.0 2.3 V 1.0
2.1 V
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 1.75 2.0 2.25 2.5 2.75 3.0 3.25 3.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.3 0.09
ID = 3.0 A TJ = 25°C
0.25 TJ = 25°C 0.085
VGS = 4.5 V

0.2 0.08

0.15 0.075

0.1 0.07
10 V
0.05 0.065

0 0.06
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current

Gate−to−Source Voltage and Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

1.8 1000
VGS = 10 V VGS = 0 V
1.6 ID = 1.5 A
1.4
100
TJ = 125°C
I DSS , LEAKAGE (nA)

1.2

1.0
10 100°C
0.8

0.6
1.0 25°C
0.4

0.2
0 0
−
50 −
25 0 25 50 75 100 125 150 0 5.0 10 15 20 25 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation Figure 6. Drain−to−Source Leakage Current

with Temperature versus Voltage

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POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted During the turn−on and turn−off delay times, gate current is
by recognizing that the power MOSFET is charge not constant. The simplest calculation uses appropriate
controlled. The lengths of various switching intervals (∆t) values from the capacitance curves in a standard equation for
are determined by how fast the FET input capacitance can voltage change in an RC network. The equations are:
be charged by current from the generator. td(on) = RG Ciss In [VGG/(VGG − VGSP)]
The published capacitance data is difficult to use for td(off) = RG Ciss In (VGG/VGSP)
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate The capacitance (Ciss) is read from the capacitance curve at
charge data is used. In most cases, a satisfactory estimate of a voltage corresponding to the off−state condition when
average input current (IG(AV)) can be made from a calculating td(on) and is read at a voltage corresponding to the
rudimentary analysis of the drive circuit so that on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
t = Q/IG(AV) complicate the analysis. The inductance of the MOSFET
During the rise and fall time interval when switching a source lead, inside the package and in the circuit wiring
resistive load, VGS remains virtually constant at a level which is common to both the drain and gate current paths,
known as the plateau voltage, VSGP. Therefore, rise and fall produces a voltage at the source which reduces the gate drive
times may be approximated by the following: current. The voltage is determined by Ldi/dt, but since di/dt
tr = Q2 x RG/(VGG − VGSP) is a function of drain current, the mathematical solution is
tf = Q2 x RG/VGSP complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
where finite internal gate resistance which effectively adds to the
VGG = the gate drive voltage, which varies from zero to VGG resistance of the driving source, but the internal resistance
RG = the gate drive resistance is difficult to measure and, consequently, is not specified.
and Q2 and VGSP are read from the gate charge curve.

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 11. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by

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Standard Cell Density

trr

I S , SOURCE CURRENT
High Cell Density
trr
tb
ta

t, TIME
Figure 7. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and must be adjusted for operating
forward biased. Curves are based upon maximum peak conditions differing from those specified. Although industry
junction temperature and a case temperature (TC) of 25°C. practice is to rate in terms of energy, avalanche energy
Peak repetitive pulsed power limits are determined by using capability is not a constant. The energy rating decreases
the thermal response data in conjunction with the procedures non−linearly with an increase of peak current in avalanche
discussed in AN569, “Transient Thermal Resistance − and peak junction temperature.
General Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded, and that the continuous current (ID), in accordance with industry
transition time (tr, tf) does not exceed 10 µs. In addition the custom. The energy rating must be derated for temperature
total power averaged over a complete switching cycle must as shown in the accompanying graph (Figure 9). Maximum
not exceed (TJ(MAX) − TC)/(RθJC). energy at currents below rated continuous ID can safely be
A power MOSFET designated E−FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 MMDF3N06HD

1200 12 30

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Ciss QT
TJ = 25°C 11
1000 10
9.0 VGS
C, CAPACITANCE (pF)

800 8.0 20
Crss 7.0
600 6.0
Ciss 5.0
400 4.0 Q1 Q2 10
3.0
200 Coss 2.0 ID = 3.0 A
1.0 Q3 TJ = 25°C
VDS
0 0 0
−10 −5.0 0 5.0 10 15 20 25 30 0 2.0 4.0 6.0 8.0 10 12 14 16
VGS VDS Qg, TOTAL GATE CHARGE (nC)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation Figure 9. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge

1000 2.5
VDD = 30 V
ID = 3.0 A TJ = 25°C
VGS = 0 V
IS, SOURCE CURRENT (AMPS)
VGS = 10 V 2.0
TJ = 25°C
100
1.5
t, TIME (ns)

td(off)
1.0
10 tf
tr
td(on) 0.5

1.0 0
1.0 10 100 0.5 0.55 0.6 0.65 0.7 0.75 0.8
RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Resistive Switching Time Variation Figure 11. Diode Forward Voltage
versus Gate Resistance versus Current

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100 120
VGS = 12 V
ID = 3.0 A

EAS, SINGLE PULSE DRAIN-TO-SOURCE

SINGLE PULSE
TA = 25°C 100
I D , DRAIN CURRENT (AMPS)

AVALANCHE ENERGY (mJ)

10 1.0 ms
80
10 ms
1.0 60

40
0.1 RDS(on) LIMIT dc
THERMAL LIMIT 20
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 25 45 65 85 105 125 145
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS

1.0
D = 0.5
Rthja(t), EFFECTIVE TRANSIENT

0.2
THERMAL RESISTANCE

0.1
0.1
0.05

0.02
0.01
0.0106 Ω 0.0431 Ω 0.1643 Ω 0.3507 Ω 0.4302 Ω
0.01 Chip
Junction
0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F
SINGLE PULSE Ambient

0.001
0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000
t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 15. Diode Reverse Recovery Waveform

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INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total interface between the board and the package. With the
design. The footprint for the semiconductor packages must correct pad geometry, the packages will self−align when
be the correct size to ensure proper solder connection subjected to a solder reflow process.

0.060
1.52

0.275 0.155
7.0 4.0

0.024 0.050
0.6 1.270
inches
mm

SO−8 POWER DISSIPATION

The power dissipation of the SO−8 is a function of the into the equation for an ambient temperature TA of 25°C,
input pad size. This can vary from the minimum pad size one can calculate the power dissipation of the device which
for soldering to the pad size given for maximum power in this case is 2.0 Watts.
dissipation. Power dissipation for a surface mount device is
PD = 150°C − 25°C = 2.0 Watts
determined by TJ(max), the maximum rated junction 62.5°C/W
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating The 62.5°C/W for the SO−8 package assumes the
temperature, TA. Using the values provided on the data recommended footprint on a glass epoxy printed circuit
sheet for the SO−8 package, PD can be calculated as board to achieve a power dissipation of 2.0 Watts using the
follows: footprint shown. Another alternative would be to use a
TJ(max) − TA
ceramic substrate or an aluminum core board such as
PD = Thermal Clad. Using board material such as Thermal
RθJA
Clad, the power dissipation can be doubled using the same
The values for the equation are found in the maximum footprint.
ratings table on the data sheet. Substituting these values

SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated • The soldering temperature and time shall not exceed
temperature of the device. When the entire device is heated 260°C for more than 10 seconds.
to a high temperature, failure to complete soldering within • When shifting from preheating to soldering, the
a short time could result in device failure. Therefore, the maximum temperature gradient shall be 5°C or less.
following items should always be observed in order to • After soldering has been completed, the device should
minimize the thermal stress to which the devices are be allowed to cool naturally for at least three minutes.
subjected. Gradual cooling should be used as the use of forced
• Always preheat the device. cooling will increase the temperature gradient and
• The delta temperature between the preheat and result in latent failure due to mechanical stress.
soldering should be 100°C or less.* • Mechanical stress or shock should not be applied
• When preheating and soldering, the temperature of the during cooling.
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When * Soldering a device without preheating can cause
using infrared heating with the reflow soldering excessive thermal shock and stress which can result in
method, the difference shall be a maximum of 10°C. damage to the device.

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TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of temperature versus time. The line on the graph shows the
control settings that will give the desired heat pattern. The actual temperature that might be experienced on the surface
operator must set temperatures for several heating zones of a test board at or near a central solder joint. The two
and a figure for belt speed. Taken together, these control profiles are based on a high density and a low density
settings make up a heating “profile” for that particular board. The Vitronics SMD310 convection/infrared reflow
circuit board. On machines controlled by a computer, the soldering system was used to generate this profile. The type
computer remembers these profiles from one operating of solder used was 62/36/2 Tin Lead Silver with a melting
session to the next. Figure 12 shows a typical heating point between 177 −189°C. When this type of furnace is
profile for use when soldering a surface mount device to a used for solder reflow work, the circuit boards and solder
printed circuit board. This profile will vary among joints tend to heat first. The components on the board are
soldering systems, but it is a good starting point. Factors then heated by conduction. The circuit board, because it has
that can affect the profile include the type of soldering a large surface area, absorbs the thermal energy more
system in use, density and types of components on the efficiently, then distributes this energy to the components.
board, type of solder used, and the type of board or Because of this effect, the main body of a component may
substrate material being used. This profile shows be up to 30 degrees cooler than the adjacent solder joints.

STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7

PREHEAT VENT HEATING HEATING HEATING VENT COOLING
ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7
“RAMP” “RAMP” “SOAK” “SPIKE” 205° TO 219°C
PEAK AT
200°C DESIRED CURVE FOR HIGH 170°C SOLDER
MASS ASSEMBLIES JOINT
160°C
150°C

150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
100°C 140°C (DEPENDING ON
MASS OF ASSEMBLY)
100°C

DESIRED CURVE FOR LOW

MASS ASSEMBLIES
5°C

TIME (3 TO 7 MINUTES TOTAL) TMAX

Figure 16. Typical Solder Heating Profile

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PACKAGE DIMENSIONS

SO−8
CASE 751−07
ISSUE V

−X−
NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
8 5 3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
B S 0.25 (0.010) M Y M SIDE.
1 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
4
K PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
−Y− EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0
8
0
8

N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
XXXXXX 3. SOURCE 2
4. GATE 2
ALYW 5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1

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 MMDF3N06HD

Notes

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MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

Thermal Clad is a registered trademark of the Bergquist Company.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment: CENTRAL/SOUTH AMERICA:
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