Control Engineering Practice 131 (2023) 105393

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Control Engineering Practice

journal homepage: www.elsevier.com/locate/conengprac

Integrated control algorithm for fast and accurate detection of the voltage sag
with low voltage ride-through (LVRT) enhancement for doubly-fed induction
generator (DFIG) based wind turbines
Arindam Chakraborty ∗, Tanmoy Maity
Department of Electrical Engineering, Indian Institute of Technology (Indian School of Mines) Dhanbad, Jharkhand 826004, India

ARTICLE INFO ABSTRACT

Keywords: Low voltage ride-through (LVRT) is one of the essential aspects of grid codes for integrating doubly-fed
Doubly fed induction generator (DFIG) induction generators (DFIG) to achieve reliable and uninterrupted electrical power generation. The detection
Low voltage ride-through (LVRT) time of the voltage sag is one of the crucial aspects for the LVRT improvement of the DFIG. This paper
Second-order generalized integrator-
introduces a second-order generalized integrator (SOGI), quadrature signal generator (QSG) with a frequency
quadrature signal generator- frequency locked
locked loop (FLL) based algorithm to detect the symmetrical voltage sag fast and accurately. The proposed
loop (SOGI-QSG-FLL)
Interval type-2 fuzzy logic-proportional
SOGI-QSG-FLL-based voltage sag detection algorithm (VSDA) works under a second-order band-pass filter with
integral (IT2-FLC-PI) controller an alfa-beta stationary reference frame. The proposed VSDA is integrated with the novel feed-forward transient
Voltage sag detection algorithm (VSDA) current compensation (FFTCC) scheme with an advanced interval type-2 fuzzy logic-proportional integral (IT2-
FLC-PI) controller to enhance the LVRT capability of the DFIG. This FFTCC scheme is activated after the
detection of voltage sag by using the proposed VSDA. The proposed FFTCC feeds the uninterrupted active and
reactive power to the grid and reduces the torque ripple of the DFIG. The detection time of voltage sag by
using the proposed VSDA is compared with existing algorithms. The experimental results are also presented
to validate the proposed algorithm.

1. Introduction active and reactive power of the DFIG while GSC controls the dc-link
voltage and grid side reactive power. The grid-connected wind turbine
Due to the exponential growth in the installed capacity of wind (WT) must fulfil some technical requirements called grid codes, which
power over the last two decades, wind energy is now performing a are of two types: static characteristics and dynamic features like grid
critical role in the world energy scenario. India will have the fourth- disturbance, voltage sag. The DFIG system is susceptible to grid inter-
highest installed capacity in the world by March 2021, with a total ruptions because the DFIG stator terminal is directly connected to the
installed capacity of 39.25 GW, and a target of 125 GW of renewable grid. Voltage sag is one of the challenging issues for the grid integration
energy by 2022 (Gupta & Shukla, 2022). There are four types of
of DFIG, and it is generally caused by symmetric or asymmetric grid
commercial wind turbines available; the doubly fed induction generator
fault, short circuit and overload (Hu, Xiao, & Zheng, 2020). If voltage
(DFIG)-based wind turbine system is probably the most frequently used
sag occurs in the grid side terminal of DFIG, the stator current increases
equipment to generate electricity (shown in Fig. 1). It is prevalent in
and can damage both GSC and RSC. Abrupt voltage drops (both in
the industry because it is a variable speed wind turbine with partially
symmetrical or asymmetrical conditions) at the DFIG stator terminals
rated converter, low cost, and high efficiency. DFIG can generate
the power in both super-synchronous as well as the sub-synchronous produce sudden dc component in the stator flux, resulting in a high
speed of the rotor. It can balance torque and power pulsations and transient current in the DFIG rotor circuit (LÓpez, Sanchis, Roboam, &
decrease mechanical stresses to improve power efficiency. In addition, Marroyo, 2007). The stator forced flux component is a function of stator
the performance of wind energy conversion system (WECS) may be voltage and rotating in synchronous speed. The natural or transient flux
maximized by the variable speed wind turbine since it can run at the component is stationary and independent on stator voltage. When the
optimum rotational velocity for each given wind speed. voltage sag occurs, the natural flux appears in the stator terminal. The
The stator of DFIG is connected directly to the grid, making power natural flux is the cause of the strong overvoltage and over current in
flow unidirectional. The rotor is connected to the grid via rotor side the rotor (LÓpez et al., 2007). If the RSC is unable to adjust the induced
converter (RSC) and grid side converter (GSC). RSC controls the stator voltage, a large transient rotor-current is generated in the rotor circuit

∗ Corresponding author.
E-mail address: arindam.18dr0038@mme.iitism.ac.in (A. Chakraborty).

https://doi.org/10.1016/j.conengprac.2022.105393
Received 19 April 2022; Received in revised form 12 September 2022; Accepted 15 November 2022
Available online 2 December 2022
0967-0661/© 2022 Elsevier Ltd. All rights reserved.
A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

more time to detect these voltage sags produce high transient current
Nomenclature in the rotor/stator and may affect the power electronic converters.
𝑖𝑑𝑟 , 𝑖𝑞𝑟 dq-axes rotor current The Fourier transform, a conventional wind-owing-based method, has
𝑖𝑞𝑟1 , 𝑖𝑞𝑟6 Harmonics components (ac quantities with significant limits in terms of slow dynamic response; therefore, a non-
sixth order fundamental frequency) linear adaptive filter is used to mitigate this problem (Naidoo & Pillay,
2007), but it cannot deliver an accurate result when the grid voltage
𝑖𝑑𝑠 , 𝑖𝑞𝑠 dq-axes stator current
is disrupted. The Improved synchronous reference frame (ISRF) based
𝜑𝑑𝑠 , 𝜑𝑞𝑠 dq-axes stator flux
controller is used in Inci, Bayındır, and Tümay (2016) that combines
𝑖𝑑𝑟1 , 𝑖𝑑𝑟6 Fundamental components (dc quantities) low pass filter and differentiator, but having a limitation of harmonics
𝜑𝑑𝑟 , 𝜑𝑞𝑟 dq-axes rotor flux hampering the performance. The synchronous rotating reference frame
𝜑𝑑𝑠1 , 𝜑𝑞𝑠1 Fundamental components (dc quantities) (SRRF) algorithm (Sillapawicharn & Kumsuwan, 2011) takes short time
𝑣𝑑𝑟 , 𝑣𝑞𝑟 dq-axes rotor voltage to detect voltage sag but, its implementation is moderate and accuracy
𝜑𝑑𝑠6 , 𝜑𝑞𝑠6 Harmonics components (ac quantities with is low. The Park transformation is also used to detect voltage sag by
sixth order fundamental frequency) monitoring the maximum level of grid voltage, but connecting filters to
𝑣𝑑𝑠 , 𝑣𝑞𝑠 dq-axes stator voltage the output terminal of the mathematical modules responsible for eval-
𝐿𝑠 Stator inductance uating voltage derivatives, results a lag in the detection algorithm (Fan
& Liu, 2012). Discrete Fourier transform (DFT) has been proposed
𝐿𝑟 Rotor inductance
in Abd-Elkader, Allam, and Tageldin (2014), but the dynamic response
𝐿𝑚 Mutual inductance
by using this method is prolonged. The Wavelet transform (Costa &
𝑅𝑟 Rotor resistance Driesen, 2013) and Hilbert-Huang transform (HHT) (Hasan, Muttaqi,
𝑅𝑠 Stator resistance & Sutanto, 2020) are also proposed for the detection of voltage sag
𝐿𝑡𝑟 Rotor transient inductance fast and accurately but implementation of these algorithms are difficult.
𝜔𝑠 Synchronous speed (rad/s) Kalman filter has been developed for detecting the magnitude of volt-
𝜔𝑟 Rotating speed of the DFIG rotor (rad/s) age sag, but harmonics are produced (Xi, Li, Zeng, Tang, Liu, & Xiao,
𝜔 Stator field rotating speed in arbitrary 2018). The SOGI-QSG-FLL is used as a voltage sag detection algorithm
reference frame (rad/s) (VSDA) in Kleber de Araújo, Guerrero, Tofoli, Branco, and Dantas
𝑇𝑒 Electromagnetic torque (2022) to detect the symmetrical and asymmetrical voltage sag fast and
accurately. The comparative analysis of the proposed SOGI-QSG-FLL
P No of the pole of the DFIG
based VSDA is presented in Table 1. It is seen that the proposed VSDA
𝜃𝑠 Stator flux angle
has low computational burden, high convergence speed, good transient
𝜃𝑟 Rotor flux angle response, strong anti-interface ability and therefore, SOGI-QSG-FLL is
𝜔𝑓 Resonant frequency adopted in this work.
𝑖∗𝑑𝑟 , 𝑖∗𝑞𝑟 dq-axes reference rotor current A novel SOGI-QSG-FLL based VSDA is proposed in this work to
𝑣𝛼𝑠 , 𝑣𝛽𝑠 Stator voltage in 𝛼𝛽 reference frame detect the voltage sag fast and accurately in grid connected DFIG
𝜑𝛼𝑠 , 𝜑𝛽𝑠 Stator flux in 𝛼𝛽 reference frame based WECS. The proposed VSDA is applied in the RSC side of the
𝑖𝛼𝑠 , 𝑖𝛽𝑠 Stator current in 𝛼𝛽 reference frame DFIG. The voltage sag detection times for SRRF, HHT, DST, ISRF, park
𝑃𝑠 , 𝑄𝑠 Stator active and reactive power transformation, Fourier transform, Kalman filter and wavelet transform
are evaluated and compared with that of the proposed SOGI-QSG-FLL
𝑣𝑎𝑟 , 𝑣𝑏𝑟 Rotor abc-axes voltage
in this research work. The efficiency of the proposed SOGI-QSG-FLL
𝑣∗𝑎𝑟 , 𝑣∗𝑏𝑟 , 𝑣∗𝑐𝑟 Rotor reference abc-axes voltage
based VSDA is compared with that of HTT and wavelet transform
𝑖𝑎𝑟 , 𝑖𝑏𝑟 , 𝑖𝑐𝑟 Rotor abc-axes current algorithm through experiments. The proposed VSDA is applicable for
𝑣𝑎𝑠 , 𝑣𝑏𝑠 , 𝑣𝑐𝑠 Stator abc-axes voltage symmetrical as well as asymmetrical voltage sag, but this paper limits
𝑣∗𝑎 , 𝑣∗𝑏 , 𝑣∗𝑐 Grid reference abc-axes voltage the symmetrical voltage sag only. After rigorous search, it is seen
that the SOGI-QSG-FLL based VSDA is not yet proposed for LVRT
improvement of DFIG during voltage sag.

that may damage the RSC, as a result, the wind turbine generator is to 1.2. Limiting transient rotor current
be disconnected from the grid. The low voltage ride-through (LVRT)
improvement schemes, employed normally in the DFIG system are LVRT is one of the essential grid codes in the DFIG-WECS (Din,
unable to detect the voltage sag accurately. Voltage sag detection is Zhang, Xu, Zhang, & Zhao, 2021a). According to the grid code, the
one of the important requirements for the grid-connected DFIG system. DFIG should be connected to grid for 625 ms and support the reactive
Large voltage sag detection time may damage the power electronic power during voltage sag (Din et al., 2021a). The LVRT enhancement
converters hampering the power quality of the grid (Gencer, Öztürk, & capability can be classified into two categories: (1) hardware-based
Erfidan, 2010). Therefore, it is required to detect the voltage sag first solutions and (2) software-based solutions (Din, Zhang, Zhu, Xu, &
and then to implement the LVRT enhancement technique for the grid- El-Naggar, 2019). Under hardware-based solution, there are two cost-
connected DFIG wind turbine. In this research work, the LVRT control effective devices for improving the LVRT of the grid-connected DFIG:
topology depends upon the voltage sag detection technique. When the one is a dc-chopper (Pannell, Zahawi, Atkinson, & Missailidis, 2013)
voltage sag is detected by proposed voltage sag detection algorithm and another is crowbar circuit (Morren & DeHaan, 2005), shown
(VSDA), the LVRT control topology is activated. In this study, various in Fig. 1. The dc chopper protects the dc link capacitor from overvoltage
type of VSDAs is presented in Section 1.1 after that LVRT improvement but this devices interrupt the reactive and active power during grid dis-
schemes are discussed in Section 1.2. turbances (Din et al., 2021a). Crowbar circuit is one of the conventional
devices which can protect the RSC from high rotor transient current,
1.1. Voltage sag detection algorithm (VSDA) but it is unable to provide the reactive power during voltage sag (Din,
Zhang, Xu, Zhang, & Zhao, 2021b). A capacitive dc reactor type fault
The detection time of the voltage sag is one of the crucial param- current limiter (CDRFCL) is proposed to limit the fault current during
eters for LVRT improvement capability of the grid-integrated DFIG grid disturbances, but CDRFCL is unable to feed the smooth uninter-
and many VSDAs are proposed to detect the voltage sag. Consuming rupted active and reactive power supply to the grid during voltage

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 1. A common DFIG-based wind energy conversion system.

Table 1
Comparative analysis of the proposed SOGI-QSG-FLL based VSDA.
VSDA Computational Computational Computational Convergence Transient Anti-interference Signal feature
efficiency complexity burden speed response ability preservation
Park transformation Low High Very High Very low Poor Very weak Poor
(Fan & Liu, 2012)
Fourier Moderate Medium High low Average Weak Average
transformation
(Naidoo & Pillay,
2007)
SRRF Low Medium low low Average Medium Average
(Sillapawicharn &
Kumsuwan, 2011)
ISRF (Inci et al., Moderate High Medium Medium Poor Weak Poor
2016)
DFT (Abd-Elkader Medium High High Average Medium Average
et al., 2014)
Kalman filter (Xi Moderate low Medium High Average Weak Good
et al., 2018)
Wavelet Transform High Medium low Medium Good Weak Average
(Costa & Driesen,
2013)
HHT (Hasan et al., Moderate low Medium High Good Medium Good
2020)
Proposed High Very low low Very High Very good Strong Very good
SOGI-QSG-FLL

sag (Shahbabaei Kartijkolaie, Radmehr, & Firouzi, 2018). The super controller is proposed in Liang, Howard, Restrepo, and Harley (2013)
magnetic energy storage (SMES) is an auxiliary device that is proposed to improve rotor transient current and torque ripple. The PI controller
to improve the LVRT of the DFIG-WECS during voltage dip (Xiao, Yang, is highly sensitive in nonlinear system and parameter variation. A
Zheng, & Wang, 2019). Although the SMES can inject the reactive classical PI controller cannot track the AC current references and as
power to the grid, it enhances the system complexity. a result the performance of LVRT is weakened (Zhu et al., 2018). The
Under the software-based solutions, linear quadratic regulator with PIR controller is used to improve the LVRT during voltage dip in Liang
integrator (LQRI) is proposed to enhance the LVRT of the DFIG- et al. (2013), but the limitation of using PIR controller is that it takes a
WECS (Murari et al., 2019). The computational burden and operating long time to eliminate the torque ripple and current tracking error (Zhu
cost of the LQRI are high. The robust active rejection disturbance et al., 2018). The design of current control loop is more complex due
control scheme is proposed to limit the transient rotor voltage and to the two parallel R (resonant) regulators used in Liang et al. (2013).
current during voltage sag (Beltran-Pulido, Cortes-Romero, & Coral- This negative and positive components decomposition complicates the
Enriquez, 2018). However, this scheme increases the system complexity design of PI and PIR controllers; also, this method creates a response
as well as enhances the computational burden. A feed-forward current in time delay and does not ensure system reliability (Djilali, Sanchez,
control scheme with PI controller is suggested for uninterrupted power & Belkheiri, 2019). Various research articles of DFIG reveal that type-1
supply to the grid during voltage sag in Liang, Qiao, and Harley fuzzy logic controller (FLC) has better performance than conventional
(2010) and feed-forward current compensation (FFTC) control with PIR PI controller in terms of tracking active and reactive power, torque

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

during voltage sag but the drawbacks of type-1 FLC is that it is unable • The proposed integrated control scheme is employed to reduce
to track the uncertainty of membership functions (deAlmeida, Lopes, the torque ripple and total harmonic distortion (THD) during
& Barreiros, 2004; Pichan, Rastegar, & Monfared, 2013). An interval voltage sag.
type-2 FLC is suggested in a research article (Raju & Pillai, 2016a)
DFIG modelling is described in Section 2. The proposed control
to improve the LVRT during grid disturbances but the drawbacks are
scheme for FFTCC with IT2-FLC-PI controller is presented in Section 3.
that power oscillation damping as well as torque ripple are increased
The proposed VSDA algorithm with integrated LVRT enhancement
during the voltage sag. An IT-2-FLC-PI is applied in the RSC to im- scheme is discussed in Section 4. Section 5 exhibits the experimental
prove the LVRT (Naik, Gupta, & Fernandez, 2020), but the suggested results followed by the conclusion in Section 6.
topology does not ensure uninterrupted active and reactive power
supplied to the grid and the improvement of torque ripple during the 2. Dfig modelling
voltage sag. The dynamic voltage restorer (DVR)-33 level Multi Level
Inverter (MLI) based fractional order Proportional–Integral–Derivative In this study, the DFIG modelling can be classified into three cate-
controller (𝑃 𝐼 𝜆 𝐷𝜇 )-Multi Object Bees Algorithm (MOBA) has been gories:
proposed to improve the LVRT of the grid connected DFIG, but the
proposed algorithm does not ensure uninterrupted active and reactive 2.1. Stator flux estimator
power supplied to the grid (Darvish Falehi & Rafiee, 2018). However,
the proposed controller has the drawback of being quite complex to Stator flux calculation is one of the important aspects for other
implement. parameters estimation of the DFIG. The stator flux and stator flux
This paper proposes a feed-forward transient current compensation angle are derived for the proposed FFTCC scheme. The three-phase
(FFTCC) scheme with a new IT2-FLC-PI-based adaptive controller to stator voltages and currents must be evaluated using the Clark trans-
formation to derive stator flux space vector values in Eqs.
( (1) )and (2).
enhance the LVRT capability of the DFIG under symmetrical grid fault.
The FFTCC with IT2-FLC-PI is proposed to feed the uninterrupted Instead of a pure integrator 1/s, a first-order element 1∕ 𝑠 + 𝑇1 is used
active and reactive power supply to the grid during voltage sag. The to eliminate the drift problem, identified in low frequency, as shown in
performance of the proposed FFTCC based IT2-FLC-PI is compared Fig. 2.
with steady state compensation PI controller and FFTCC based PIR ( )
𝜑𝛼𝑠 = 𝑣𝛼𝑠 − 𝑅𝑠 𝑖𝛼𝑠 𝑑𝜃 (1)
controller. ∫
Reduction of the torque ripple is another requirement during the ( )
𝜑𝛽𝑠 = 𝑣𝛽𝑠 − 𝑅𝑠 𝑖𝛽𝑠 𝑑𝜃 (2)
voltage sag. The sequence decomposition method (Santos-Martin, ∫
Rodriguez-Amenedo, & Arnaltes, 2009) and direct power control (Abad, The stator flux angle is defined as
Rodríguez, Iwanski, & Poza, 2010) are used to limit the torque ripple, 𝜑𝛽𝑠
but do not contemplate limiting rotor transient current. The proposed 𝜃𝑠 = arctan (3)
𝜑𝛼𝑠
integrated control algorithm in this work suppresses the torque ripple
The rotating speed of the stator flux is defined in (4). The rotating speed
as well as limits the transient rotor current during voltage sag.
of the stator flux is different from stator voltage space vector during the
transient.
1.3. Novelty and contribution of this paper 𝑣𝛽𝑠 𝜑𝛼𝑠 − 𝑣𝛼𝑠 𝜑𝛽𝑠
𝜔𝜑𝑠 = (4)
𝜑2𝛼𝑠 + 𝜑2𝛽𝑠
In this research work, the SOGI-QSG-FLL-based VSDA is integrated
with the novel FFTCC-based IT2-FLC-PI controller to detect the voltage 2.2. Transient modelling of DFIG
sag fast and accurately, enhancing the LVRT capability of the DFIG-
WECS. The proposed VSDA receives the signal from the three phase The stator voltage transient model of DFIG is derived for the pro-
stator voltages and sends the error signal to the FFTCC scheme. At posed FFTCC scheme. Stator and rotor voltages for the DFIG in the
normal condition, there will be no change of the stator voltage, so dq-axes reference frame are (Liang et al., 2013):
that the error signal, generated by proposed VSDA is zero. If the
𝑣𝑑𝑠 = 𝑅𝑠 𝑖𝑑𝑠 + 𝑝𝜑𝑑𝑠 − 𝜔𝜑𝑞𝑠
voltage sag occurs in the stator terminal, the proposed VSDA detects the
voltage sag and generates the error signal. The error signal between the 𝑣𝑞𝑠 = 𝑅𝑠 𝑖𝑞𝑠 + 𝑝𝜑𝑞𝑠 + 𝜔𝜑𝑑𝑠
measured and reference three phase stator voltages is passed through
the proposed FFTCC to improve the LVRT of the DFIG-WECS. The 𝑣𝑑𝑟 = 𝑅𝑠 𝑖𝑑𝑟 + 𝑝𝜑𝑑𝑟 − (𝜔 − 𝜔𝑟 )𝜑𝑞𝑟
novelty and contribution of this paper are summarized as follows:
𝑣𝑞𝑟 = 𝑅𝑠 𝑖𝑞𝑟 + 𝑝𝜑𝑞𝑟 + (𝜔 − 𝜔𝑟 )𝜑𝑑𝑟 (5)
• A novel application of SOGI-QSG-FLL-based voltage sag detection
𝑑
algorithm (VSDA) is proposed in this research work to detect the Here, 𝑝 is denoted by 𝑑𝑡
. The stator flux equations in dq-axes are
voltage sag fast and accurately and is experimentally compared defined in (6).
with existing VSDAs. 𝜑𝑑𝑠 = 𝐿𝑠 𝑖𝑑𝑠 + 𝐿𝑚 𝑖𝑑𝑟
• The proposed VSDA is integrated with FFTCC based IT2-FLC-PI
controller to improve the LVRT of the DFIG fast and accurately 𝜑𝑞𝑠 = 𝐿𝑠 𝑖𝑞𝑠 + 𝐿𝑚 𝑖𝑞𝑟
during voltage sag. A comparative transient response analysis of
the DFIG parameters is presented to show the performance of the 𝜑𝑑𝑟 = 𝐿𝑚 𝑖𝑑𝑠 + 𝐿𝑟 𝑖𝑑𝑟
proposed integrated control algorithm. The proposed integrated
algorithm is working properly during normal and fault condition. 𝜑𝑞𝑟 = 𝐿𝑚 𝑖𝑞𝑠 + 𝐿𝑟 𝑖𝑞𝑟 (6)
• The proposed integrated control scheme is applied in the RSC Stator flux equations (6) are substituted in the stator voltage equations
to supply the uninterrupted smooth active and reactive power in (5), the stator and rotor voltages in dq-axes are written in (7) and
to the grid during symmetrical voltage sag. It is experimentally (8) respectively.
compared with steady state compensation with PI controller- [ ] [ ] [ ][ ]
based wavelet VSDA (scheme 1) and FFTC-PIR controller-based 𝑣𝑑𝑠 𝑝 −𝜔𝜑𝑠 𝑝 −𝜔𝜑𝑠 𝑖𝑑𝑟
= 𝐿𝑠 + 𝐿𝑚 (7)
HTT VSDA (scheme 2). 𝑣𝑞𝑠 𝜔𝜑𝑠 𝑝 𝜔𝜑𝑠 𝑝 𝑖𝑞𝑟

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 2. Stator flux calculation and stator flux angle.

[ ] [ ][ ]
𝑣𝑑𝑟 𝑅𝑟 + 𝐿 𝑟 𝑝 −(𝜔𝜑𝑠 − 𝜔𝑟 )𝐿𝑟 𝑖𝑑𝑟 flux respectively. When the transients or unbalanced condition occurs
=
𝑣𝑞𝑟 (𝜔𝜑𝑠 − 𝜔𝑟 )𝐿𝑟 𝑅𝑟 + 𝐿 𝑟 𝑝 𝑖𝑞𝑟 in the system, 𝜔𝜑𝑠 is not equal to zero. To limit the torque ripples of
[ ][ ] DFIG due to voltage sag, both dq-axes rotor current and flux linkages
𝑝 −(𝜔𝜑𝑠 − 𝜔𝑟 ) 𝑖𝑑𝑠
+ 𝐿𝑚 (8) are to be examined.
(𝜔𝜑𝑠 − 𝜔𝑟 ) 𝑝 𝑖𝑞𝑠 The active and reactive powers of the stator during transient condi-
tion are calculated in (15) and (16) respectively.
Now (7) is used to eliminate 𝑖𝑑𝑠 and 𝑖𝑞𝑠 in (8), the following Eq. (9)
is obtained: 3 𝐿𝑚
𝑃𝑠 = − 𝜔𝑠 𝜑𝑑𝑠 𝜑 (15)
[ ][ ] [ ] [ ][ ] 2 𝜎𝐿𝑠 𝐿𝑟 𝑞𝑟
𝑝 −𝜔𝜑𝑠 𝑖𝑑𝑠 𝐿 𝑣𝑑𝑠 𝐿2 𝑝 −𝜔𝜑𝑠 𝑖𝑑𝑟 ( )
𝐿𝑚 = 𝑚 − 𝑚 (9) 3 𝐿𝑚 𝐿𝑟
𝜔𝜑𝑠 𝑝 𝑖𝑞𝑠 𝐿 𝑠 𝑣𝑞𝑠 𝐿 𝑠 𝜔𝜑𝑠 𝑝 𝑖𝑞𝑟 𝑄𝑠 = 𝜔𝑠 𝜑𝑑𝑠 𝜑𝑠 − 𝜑𝑑𝑟 (16)
2 𝜎𝐿𝑠 𝐿𝑟 𝐿𝑠
The (9) is further modified into (10). The (10) is written as √
[ ][ ] Where, 𝜑𝑠 = 𝜑𝑑𝑠 2 + 𝜑𝑞𝑠 2 and 𝜑𝑠 is the total stator flux.
𝑝 −(𝜔𝜑𝑠 − 𝜔𝑟 ) 𝑖𝑑𝑠
𝐿𝑚
(𝜔𝜑𝑠 − 𝜔𝑟 ) 𝑝 𝑖𝑞𝑠 2.3. Torque ripple calculation during harmonics
[ ] [ ] [ ]
𝐿 𝑣𝑑𝑠 + 𝜔𝑟 𝜑𝑞𝑠 𝐿 2 𝑝 −(𝜔𝜑𝑠 − 𝜔𝑟 ) 𝑖𝑑𝑟
= 𝑚 − 𝑚 × (10) Somehow, the torque ripple of the DFIG increases due to harmonics
𝐿𝑠 𝑣 − 𝜔 𝜑 𝐿𝑠 (𝜔 − 𝜔 ) 𝑝 𝑖𝑞𝑟 presents in the stator flux of the DFIG (Wu, Nian, Pang, & Cheng, 2019).
𝑞𝑠 𝑟 𝑑𝑠 𝜑𝑠 𝑟
The stator flux carrying harmonics in dq synchronous reference frame
The transient rotor current is expressed in (11) from (8) and (10):
is written as
[ ] [ ][ ] [ ]
𝑣𝑑𝑟 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 −(𝜔𝜑𝑠 − 𝜔𝑟 )𝐿𝑡𝑟 𝑖𝑑𝑟 𝐿𝑚 𝑣𝑑𝑠 + 𝜔𝑟 𝜑𝑞𝑠
= + 𝜑𝑑𝑞𝑠 = 𝜑𝑑𝑠1 + 𝜑𝑑𝑠6 + 𝑗(𝜑𝑞𝑠1 + 𝜑𝑞𝑠6 ) (17)
𝑣𝑞𝑟 (𝜔𝜑𝑠 − 𝜔𝑟 )𝐿𝑡𝑟 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 𝑖𝑞𝑟 𝐿𝑠 𝑣𝑞𝑠 − 𝜔𝑟 𝜑𝑑𝑠
The rotor current carrying harmonics in dq synchronous frame is writ-
(11) ten as
The rotor transient inductance, 𝐿𝑡𝑟 = 𝜎𝐿𝑟 in the (11) indicates the 𝑖𝑑𝑞𝑟 = 𝑖𝑑𝑟1 + 𝑖𝑑𝑟6 + 𝑗(𝑖𝑞𝑟1 + 𝑖𝑞𝑟6 ) (18)
instantaneous value of stator and rotor voltages for both steady-state
condition and transient period. Whenever the stator voltage sag occurs The torque ripple (𝑇𝑒′ ) is expressed in (19) using (17) and (18).
in the system, the rotor terminal voltage is directly generated up to 𝐿𝑚 [
RSC rating. So that, (11) produces correct compensation during stator 𝑇𝑒′ = − (𝜑𝑑𝑠1 𝑖𝑞𝑟1 ) + (𝜑𝑑𝑠1 𝑖𝑞𝑟6 + 𝜑𝑑𝑠6 𝑖𝑞𝑟1 − 𝜑𝑞𝑠6 𝑖𝑑𝑟1 )
𝐿𝑠
voltage sag for the current control loop. At steady-state conditions, the ]
+ (𝜑𝑑𝑠6 𝑖𝑞𝑟6 − 𝜑𝑞𝑠6 𝑖𝑞𝑟6 ) (19)
stator voltage is expressed as:
′ ) of the sixth-order frequency harmonic is only
The torque ripple (𝑇6𝑒
𝑣𝑑𝑠 + 𝜔𝑟 𝜑𝑞𝑠 = 0, 𝑣𝑞𝑠 − 𝜔𝑟 𝜑𝑑𝑠 = 𝑠.𝑣𝑞𝑠 (12)
considered in this work for the purpose of simplicity and it is expressed
Where s is the slip. Now substituting (12) into dq-axes rotor voltage in in (20).
(11). So that, the (11) is further modified into (13). 𝐿𝑚 𝐿
[ ] [ ][ ] [ ] ′
𝑇6𝑒 =− (𝜑 𝑖 ) − 𝑚 (𝜑𝑑𝑠6 𝑖𝑞𝑟1 − 𝜑𝑞𝑠6 𝑖𝑑𝑟1 ) (20)
𝑣𝑑𝑟 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 −𝑠𝜔𝑠 𝐿𝑡𝑟 𝑖𝑑𝑟 𝐿 0 𝐿𝑠 𝑑𝑠1 𝑞𝑟1 𝐿𝑠
= +𝑠 𝑚 (13)
𝑣𝑞𝑟 𝑠𝜔𝑠 𝐿𝑡𝑟 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 𝑖𝑞𝑟 𝐿 𝑠 𝑣𝑞𝑠 Where, (20) is the second term in (19) consists of stator flux harmonics
as well as rotor fundamental current. Torque ripple is adjusted to zero
Where, (13) represents the steady-state stator voltage compensation by controlling q-axis rotor harmonic current.
used in the current control loop. The electromagnetic torque 𝑇𝑒 during
transient period is defined in (14). The torque is written as
3. Modelling of FFTCC scheme by using an interval type-2 fuzzy
3 𝑃 𝐿𝑚 logic with proportional–integral controller (IT2-FLC-PI)
𝑇𝑒 = (𝜑 𝑖 − 𝜑𝑑𝑠 𝑖𝑞𝑟 ) (14)
2 2 𝐿𝑠 𝑞𝑠 𝑑𝑟
At steady-state conditions 𝜑𝑞𝑠 = 0, as a result, electromagnetic torque 3.1. Proposed FFTCC design for current control loop
depends upon the 𝑖𝑞𝑟 not in 𝑖𝑑𝑟 and 𝜔(𝑡) = 𝜔𝜑𝑠 (𝑡), where 𝜔𝜑𝑠 denotes
the rotating speed of the stator flux. At the steady-state condition of the The whole transient voltage generated on the stator side is feed-
DFIG, 𝜔𝜑𝑠 = 𝜔𝑠 , here 𝜔𝑠 and 𝜑𝑠 are the synchronous speed and stator forward injected into the rotor current control loop without considering

5
A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 3. Proposed FFTCC with IT2FLC-PI controller for RSC.

3.2. Interval type-2 fuzzy logic set

Primary and secondary are the typical interval type membership

functions (MF) of an IT2- FLC (Raju & Pillai, 2016b). The primary
membership function (PMF) grade of an IT2-FLC is a normal fuzzy,
i.e., type-1 FLC. Set in [0, 1], whereas the secondary membership is a
crisp number in [0, 1] according to Mendel, John, and Liu (2006). The
third dimension determines the secondary membership function (SMF)
of type-2 fuzzy sets, and the footprint of uncertainty (FOU) determines
the uncertainty range.
Fig. 4. Direct axis rotor reference current.
The type-2 fuzzy set, represented by A, is defined as Raju and Pillai
(2016a)
{ }
the steady-state balanced condition. The transient rotor voltages in the 𝐴 = (𝑥, 𝑢) , 𝜇𝐴 (𝑥, 𝑢) , ∀𝑥 ∈ 𝑋, ∀𝑢 ∈ 𝐽𝑥 ⊆ [0, 1] (23)
d and q-axis are: Where, 𝑥 ∈ 𝑋, 𝑢 ∈ 𝐽𝑥 ⊆ [0, 1] and 0 ≤ 𝜇𝐴 (𝑥, 𝑢) ≤ 1.
( ) ( ) 𝐿 ( ) An interval type 2 set is expressed as Raju and Pillai (2016a)
𝑣𝑑𝑟 = 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 𝑖𝑑𝑟 − 𝜔𝜑𝑠 − 𝜔𝑟 𝐿𝑡𝑟 𝑖𝑞𝑟 + 𝑚 𝑣𝑑𝑠 + 𝜔𝑟 𝜑𝑞𝑠 (21)
𝐿𝑠 1
( ) ( ) ( ) 𝐴̃ = , 𝐽 ⊆ [0, 1] (24)
𝐿𝑚 ∫𝑥∈𝑋 ∫𝑢∈𝐽𝑥 (𝑥, 𝑢) 𝑥
𝑣𝑞𝑟 = 𝑅𝑟 + 𝐿𝑡𝑟 𝑝 𝑖𝑞𝑟 + 𝜔𝜑𝑠 − 𝜔𝑟 𝐿𝑡𝑟 𝑖𝑑𝑟 + 𝑣𝑞𝑠 − 𝜔𝑟 𝜑𝑑𝑠 (22)
𝐿𝑠
𝐴̃ ∶ 𝑋 → {[𝑎, 𝑏]} ∶ 0 ≤ 𝑎 ≤ 𝑏 ≤ 1, The union of all primary
The second and third terms of (21) and (22) indicate the feed-forward memberships represents the uncertainty of is called the footprint of
current compensation. An advanced IT2-FLC-PI controller is proposed uncertainty (FOU), as shown in Fig. 5(a).
to regulate the current loop for the rotor side converter (RSC). The { }
̃ = ∪∀𝑥∈𝑋 𝐽𝑥 = (𝑥, 𝑢) ∶ 𝑢 ∈ 𝐽𝑥 ⊆ [0, 1]
𝐹 𝑂𝑈 (𝐴) (25)
proposed feed-forward transient current control (FFTCC) scheme with
IT2-FLC-PI for RSC is shown in Fig. 3. As the reactive power is FOU of IT-2 FLC is defined by two type-1 membership functions
dependent on voltage, if voltage sag occurs in the system due to fault, (MF) - lower membership function (LMF), denoted as 𝜇 𝐴̃(𝑥) and upper
the (𝑖∗𝑑𝑟 ) should be modified. Accordingly, it can be done by changing membership function (UMF), denoted as 𝜇 ̃(𝑥) in (26), (27) respec-
𝐴
the voltage gain (𝑘𝑣𝑐 ) of the voltage controller as shown in Fig. 4. The tively.
error between 𝑖𝑑𝑟 and 𝑖∗𝑑𝑟 are fed through the IT2-FLC-PI controller
̃ ∀𝑥∈𝑋
𝜇 𝐴̃(𝑥) = 𝐹 𝑂𝑈 (𝐴), (26)
to generate 𝑣′𝑑𝑟 . Finally, 𝑣𝑑𝑟 is determined by adding a feed-forward
compensation term according to (21). Similarly, q-axis feed-forward ̃ ∀𝑥∈𝑋
𝜇 ̃(𝑥) = 𝐹 𝑂𝑈 (𝐴), (27)
𝐴
compensation term is added to obtain the value of 𝑣𝑞𝑟 according to { [ ]}
𝐽𝑥 = (𝑥, 𝑢) ∶ 𝑢 ∈ 𝜇 ̃(𝑥), 𝜇 𝐴̃(𝑥) (28)
(22). 𝐴

The proportional and integral gains of PI are adjustable and tuned 𝐴̃𝑒 = [1∕𝑢]∕𝑥, 𝑢 ∈ 𝐽𝑥 (29)
∫𝑥∈𝑋
using the IT2-FLC technique when the system operating conditions
vary. IT2-FLC is used here to achieve better dynamic response from Where 𝐴̃𝑒 is called embedded fuzzy set for the continuous discourse of
the system. X and 𝜇 respectively.

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Table 2
Rule table for IT2-FLC-PI controller.
Change in error (𝛥𝜀) Error (𝜀)
Tuning rule for 𝛥𝑘𝑝 Tuning rule for 𝛥𝑘𝑖 Tuning rule for 𝛥𝑘𝑣𝑐
BN SN ZE SP BP BN SN ZE SP BP BN SN ZE SP BP
BN VSP VSP VSP SP MP VBP VBP VBP SP VSP VSP VSP VSP SP MP
SN VSP SP SP SP MP VBP BP MP MP VSP VSP SP SP SP MP
ZE VSP SP MP BP VBP BP BP BP SP VSP VSP SP MP BP VBP
SP MP BP BP BP VBP MP BP SP SP VSP MP BP BP BP VBP
BP MP BP VBP VBP VBP MP SP VSP VSP VSP MP BP VBP VBP VBP

2011). FLL can accurately track the grid frequency unlike PLL. FLL
improves the dynamic performance of the frequency estimation as
well as reduces the steady-state frequency ripples. The complete block
diagram of single-phase VSDA is shown in Fig. 7.
The transfer functions of SOGI are written in (30)–(32)
𝑣′ 𝜔𝑓
= (30)
𝑘𝜀𝑣 𝑠2 + 𝜔2𝑓
𝑣′ (𝑠) 𝑘𝜔𝑓 𝑠
= (31)
Fig. 5(a). Type 2 fuzzy set with FOU with embedded fuzzy set. 𝑣(𝑠) 𝑠 + 𝑘𝑠𝜔𝑓 + 𝜔2𝑓
2

𝑞𝑣′ (𝑠) 𝑘𝜔𝑓

= (32)
𝑣(𝑠) 𝑠2 + 𝑘𝑠𝜔𝑓 + 𝜔2𝑓
Fig. 5(b) shows that to account for expert knowledge uncertainties,
crisp inputs are first converted into fuzzy inputs using type-2 mem- The letter ‘q’ indicates this output in quadrature with 𝑣′ . Here, 𝜔𝑓
bership functions. Then, using logical operators, a set of fuzzy rules is the angular frequency (resonance frequency) of FLL block and k is
is designed to combine the fuzzy output sets into a single set through the gain of SOGI. 𝜔𝑐 is the cut off frequency of FLL block. Here, stator
an interference process. voltages are synchronized with the grid voltages, so that, 𝑣𝑎𝑠 = 𝑣𝑎 ,
According to Aisbett and Rickard (2014), Liang and Mendel (2000) 𝑣𝑏𝑠 = 𝑣𝑏 and 𝑣𝑐𝑠 = 𝑣𝑐 . As there are two input signals to two SOGIs and
the type-2 FLC can be regarded as a collection of different type-1 FLCs four output signals are obtained, it is called DSOGI (dual second-order
embedded in the type-2 FLC. As a result, the crisp outputs of the type- generalized integrator), shown in Fig. 8. This DSOGI is working under
2 FLC can be derived by aggregating the outputs of all the embedded 𝛼𝛽 arbitrary reference frame. It shows two input signals 𝑣𝑎𝛼 (𝑡), 𝑣𝑎𝛽 (𝑡)
type-1 FLCs. and four output signals are obtained as a consequence: 𝑣′𝑎𝛼 (𝑡), 𝑞𝑣′𝑎𝛼 (𝑡),
In this work, input variables of the IT2-FLC controller are error 𝑣′𝑎𝛽 (𝑡) and 𝑞𝑣′𝑎𝛽 (𝑡).
(𝜀) and change in error (𝛥𝜀) shown in Fig. 6(a). Similarly, the output 𝑣𝑎𝛼 (𝑡) and 𝑣𝑎𝛽 (𝑡) are in phase with 𝑣′𝑎𝛼 (𝑡) and 𝑣′𝑎𝛽 (𝑡); and quadrature
variables have been demonstrated in Fig. 6(b). The error signal of the with 𝑞𝑣′𝑎𝛼 (𝑡) and 𝑞𝑣′𝑎𝛽 (𝑡). The output signals are passed through positive–
input variables is fuzzified by five triangular membership functions. negative sequence calculator (PNSC) to separate out the positive and
The functions are SN—small negative, BN—big negative, ZE—zero negative sequence components as shown is Fig. 8. The (33) and (34)
error, BP—big positive, SP—small positive, VSP—very small positive represent the normalized positive sequence components.
and VBP—very big positive. The universe discourse of error and change ′
in error is determined between ranges from +1 to −1. Here, 25 rules 𝑣+ ′ ′
𝑎𝛼 (𝑡) = 𝑣𝑎𝛼 (𝑡) − 𝑞𝑣𝑎𝛽 (𝑡) (33)
have been developed for the 𝛥𝑘𝑝 , 𝛥𝑘𝑖 and 𝛥𝑘𝑣𝑐 respectively, in Table 2. 𝑣+
′
(𝑡) = 𝑞𝑣′𝑎𝛼 (𝑡) + 𝑣′𝑎𝛽 (𝑡) (34)
𝑎𝛽
The ‘height’ TR technique has been used in this work to compute
the centroid of IT2- FLCs because it involves fewer calculations than Similarly, the normalized positive sequence components for other
′ ′ ′ +′
other methods (Naik et al., 2020). The centroid of a Type-2 fuzzy set phases, 𝑣𝑏 (𝑡) and 𝑣𝑐 (𝑡) are derived as 𝑣+
𝑏𝛼
(𝑡), 𝑣+
𝑏𝛽
(𝑡) and 𝑣+
𝑐𝛼 (𝑡), 𝑣𝑐𝛽 (𝑡). The
is the sum of its embedded sets’ centroids. Defuzzification converts the aggregate values for the normalized positive sequence components for
fuzzy output value to a crisp value. each phase are given in (35), (36) and (37).
√ √
[ ]2 [ ]2
+′ +′ 2 +′ 2
4. Proposed integrated control algorithm for detecting voltage sag 𝑣𝑎𝛼𝛽(𝑎𝑔𝑔) = 𝑣𝑎𝛼 (𝑡) + 𝑣𝑎𝛽 (𝑡) = 𝑣+
𝑎(max)
sin(𝜔𝑡) + 𝑣+ 𝑎(max)
cos(𝜔𝑡)
with lvrt enhancement
= 𝑣+
𝑎(max)
(35)
√
Voltage sag detection is essential for grid-connected DFIG as the +′ ′ ′
𝑣𝑏𝛼𝛽(𝑎𝑔𝑔) = 𝑣+ 𝑏𝛼
(𝑡)2 + 𝑣+
𝑏𝛽
(𝑡)2 = 𝑣+
𝑏(max)
(36)
stator is directly connected to the grid. A short circuit or any fault of √
′ +′ 2 +′ 2
the grid may damage both the RSC and GSC of the DFIG. The VSDA 𝑣+ = 𝑣𝑐𝛼 (𝑡) + 𝑣𝑐𝛽 (𝑡) = 𝑣+ (37)
𝑐𝛼𝛽(𝑎𝑔𝑔) 𝑐(max)
is integrated with novel FFTCC scheme with IT2-FLC-PI controller for
LVRT enhancement to detect voltage sag fast and accurately. When When the system is running at standard working conditions, the
the voltage sag occurs in the grid or stator terminal of the DFIG, the aggregate values of each phase must be equal, i.e., 𝑣+ 𝑎(max)
= 𝑣+
𝑏(max)
=
+
proposed VSDA detects the instantaneous RMS (root means square) 𝑣𝑐(max) = 1 p.u. When the three-phase disturbances or voltage sag occurs
voltage of each phase. in the grid, then 𝑣+ 𝑎(max)
≠ 𝑣+
𝑏(max)
≠ 𝑣+
𝑐(max)
= 1 p.u.
The second-order generalized integrator (SOGI) employing a band- The resulting error signal is processed through the sine wave gen-
pass filter and quadrature signal generator (QSG) (Kleber de Araújo eration block with the help of both voltage controller and frequency
et al., 2022) is used to design the proposed VSDA in this work. A controller to produce three-phase reference rotor currents, i.e., 𝑖𝑎𝑟_𝑟𝑒𝑓 ,
frequency-locked loop (FLL) is used to calculate the input frequency 𝑖𝑏𝑟_𝑟𝑒𝑓 and 𝑖𝑐𝑟_𝑟𝑒𝑓 . The three-phase reference rotor currents as well as
instead of the phase locked loop (PLL). PLL is susceptible under abrupt the measured three phase rotor current are transformed into direct and
grid voltage sag, but FLL does not change suddenly and adaptive in quadrature axis components by abc to dq transform. During voltage sag,
nature (Rodríguez, Luna, Candela, Mujal, Teodorescu, & Blaabjerg, the resulting error is processed through the proposed FFTCC scheme

7
A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 5(b). Schematic diagram of IT2- FLC.

Fig. 6. Membership functions (MF) of type 2-FLC :(a) input (b) output.

To create a voltage sag, multiplied the reference voltages by the

respective values reflecting the type and amplitude of the disturbance,
which can be produced by setting two constants, k1 and k2, as shown
in (41) and (42).
√
𝑣∗𝛼 (𝑡) = 𝑘1 2𝑣𝛼(𝑟𝑚𝑠) cos(𝜔𝑡) (41)
√
∗
𝑣𝛽 (𝑡) = 𝑘2 2𝑣𝛽(𝑟𝑚𝑠) sin(𝜔𝑡) (42)

The input signal of SOGI-QSG-FLL is given by 𝑣 = 𝑉𝑚 sin(𝜔𝑡)

where 𝑉𝑚 is the maximum value of the input signal. Time response for
SOGI-QSG-FLL is expressed as (43) and (44).
𝑉𝑚 𝑘𝜔𝑓
𝑣′ (𝑡) = − sin (𝜆𝜔𝑡) .𝑒− 2 𝑡 + 𝑉𝑚 sin(𝜔𝑡) (43)
𝜆
𝑘𝜔𝑓
𝑘
𝑞𝑣′ (𝑡) = 𝑉𝑚 [cos(𝜆𝜔𝑡) + . sin(𝜆𝜔𝑡)].𝑒− 2 𝑡 − 𝑉𝑚 cos(𝜔𝑡) (44)
2𝜆
Fig. 7. SOGI-QSG-FLL, a single-phase voltage sag detection algorithm. The value of 𝑘 determines the frequency bandwidth of the SOGI-
QSG-FLL. A large value of k could make the SOGI-QSG-FLL function
fast, decreasing√ its susceptibility to harmonics in the input signal.
Here, 𝜆 = 4 − 𝑘2 ∕2, and thus k < 2.
(Fig. 3), which regulates the current control loop and limits the tran-
The settling time for the proposed SOGI-QSG-FLL is given in (45)
sient rotor current of DFIG. Thus, the current control loop of DFIG
generates the direct and quadrature axis rotor voltages that provide 10
𝑡𝑠(𝑆𝑂𝐺𝐼) = (45)
pulses from PWM for RSC. The proposed integrated LVRT enhancement 𝑘𝜔𝑓
scheme for DFIG is shown in Fig. 9.
In the propose method, FPGA based real time controller is used as a 5. Experimental results
grid simulator that generates the reference phase voltages at unbalance
condition in (38), (39) and (40). 5.1. Experimental setup
√
2 ∗ To assess the performance of the proposed scheme in a real-time en-
𝑣∗𝑎 (𝑡) = 𝑣 (𝑡) (38)
3 𝛼 vironment, a suitable laboratory setup is considered with the following
∗
𝑣∗𝛼 (𝑡) 𝑣𝛽 (𝑡) components shown in Fig. 10:
𝑣∗𝑏 (𝑡) = − √ + √ (39)
6 2 (i) A Xilinx FPGA based real time controller with Dual ARM® Cortex
∗ A9 MP Core with capability up to 667 MHz operations.
𝑣∗𝛼 (𝑡) 𝑣𝛽 (𝑡)
𝑣∗𝑐 (𝑡) = − √ − √ (40) (ii) A DC shunt motor of 220 V DC, 2.5 KW, 1500 rpm emulating as
6 2 wind turbine, armature and field are connected through adjustable dc

8
A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 8. DSOGI-QSG-FLL algorithm.

Fig. 9. Proposed LVRT enhancement scheme with SOGI-QSG-FLL based VSDA.

voltage source. RSC controls the speed of the wind emulator (DC shunt synchronous speed of 1200 rpm (slip = −0.2). The modelling of novel
motor). FFTCC based IT2-FLC-PI controller with proposed VSDA in real time
(iii) A Three-phase slip ring induction motor (DFIG) 2.2 kW, 415 V AC, algorithm is demonstrated in Fig. 11.
1000 rpm with speed encoder of 1024 ppr.
(iv) LC filter and 3-phase reactor along with two back-to-back convert- 5.2. Experimental results during symmetrical voltage sag (three phase to
ers (RSC and GSC). ground fault)
The symmetrical voltage sag (three phase to ground fault) is created
in this experimental set up for the duration of 0.8 s (𝑡 = 0.2 s to To validate the efficiency of the proposed SOGI-QSG-FLL based
𝑡 = 1.0 s) by a three-phase auto transformer. DFIG is operating at super VSDA, it is compared experimentally with HTT and wavelet transform.

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 10. Experimental setup of the DFIG grid integration with wind emulator.

Fig. 11. Modelling of proposed combined algorithm (FFTCC-based IT2-FLC-PI with VSDA) in real time controller.

Fig. 12. Voltage Sag detection (a) using wavelet transform (b) using HTT (c) using SOGI-QSG-FLL.

It has been observed that the detection time of the voltage sag using implementation is easy with high accuracy and takes minimum time to
the proposed SOGI-QSG-FLL is 2.1 ms; on the other hand, the detec- detect the voltage sag, as shown in Table 3.
tion time of the voltage sag using wavelet and HTT are 6.5 ms and If the voltage sag occurs in the system, the proposed VSDA detects
5.1 ms respectively, as shown in Fig. 12(a), Fig. 12(b) and Fig. 12(c) the voltage sag and error signal between actual three-phase stator volt-
respectively. A comparison chart of the voltage sag detection time is age and three-phase reference voltage stator voltage is passed through
shown in Table 3 for all the existing algorithms. The proposed VSDA the proposed FFTCC scheme for LVRT improvement of the DFIG. In

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Fig. 14. FFTC-PIR controller based HTT VSDA (scheme 2).

Fig. 13. Steady state compensation with PI controller-based wavelet VSDA (scheme 1).

observed from Fig. 13(b) that when steady state compensation with PI
this work, the performance of the proposed controller is validated controller-based wavelet VSDA (scheme 1) is applied into the system,
by comparing with that of a PI with wavelet VSDA controller and the detection time voltage sag is 6.5 ms and as a result, the transient
FFTCC-PIR with HTT VSDA controller. rotor current increases. In this case, LVRT protection is not applied.
The voltage sag response of each integrated control algorithm is When the FFTC-PIR controller-based HTT VSDA (scheme 2) is applied
shown in Fig. 13(a), Fig. 14(a), and Fig. 15(a), respectively. It has been into the system, the transient overshoot current is limited but not fully

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Table 3
Performance-comparison of voltage sag detection algorithms (VSDAs).
Voltage sag detection algorithm Detection time Implementation Accuracy
HHT (Hasan et al., 2020) 5.1 ms Difficult High
SRRF(Sillapawicharn & Kumsuwan, 2011) 7.3 ms Difficult Moderate
DFT (Abd-Elkader et al., 2014) 8.2 ms Moderate Moderate
ISRF (Inci et al., 2016) 8.9 ms Easy Low
Fourier transform (Naidoo & Pillay, 2007) 9.5 ms Moderate Low
Kalman filter (Xi et al., 2018) 6.9 ms Difficult High
Park transformation (Fan & Liu, 2012) 9.6 ms Moderate Low
Wavelet transform (Costa & Driesen, 2013) 6.5 ms Difficult High
Proposed VSDA (SOG-QSG-FLL) 2.1 ms Easy High

suppressed due to the high degree of uncertainty of IT2-FLC for the

proposed scheme, as shown in Fig. 15(c). It is not sensitive to parameter
variation. Large torque ripple is generated due to high inrush stator
current for scheme 1 (Fig. 13(d), partially suppressed for scheme 2
(Fig. 14(d), because PI and PIR controller are having high steady
state error. The transient response of the proposed scheme is improved
and the torque ripple is entirely suppressed (Fig. 15(d). The proposed
scheme can track the transient rotor current accurately because the
membership function and FOU are more effective to control the un-
certainties, and the SOGI-QSG-FLL algorithm eliminates dc offset and
harmonics at a wide range of frequency. Power oscillation damping
is improved using the proposed integrated algorithm. Uninterrupted
power is supplied by both scheme 2 and proposed scheme, but it is
observed that power oscillation is increased due to stator voltage sag
when the scheme 1 and scheme 2 are applied, as shown in Figs. 13(e)
and 14(e). Power oscillation is caused by harmonics and temporary dc
components, which are mitigated by the proposed scheme. Fig. 15(e)
shows that the uninterrupted power with less power oscillation is fed
to the grid by the proposed scheme. It is observed that the dc-link
voltages overshoot in scheme 1 and scheme 2 as shown in Figs. 13(f)
and 14(f), whereas in the proposed scheme, IT2-FLC provides better
damping effect (Fig. 15(f). A comparison of transient performance for
all the three schemes is presented in Table 4.
This proposed IT2-FLC-PI-based adaptive controller has excellent
dynamic as well as steady-state response compared with the other
controller. The membership function and FOU (footprint of uncer-
tainties) of the IT2-FLC provide additional degree of freedom for the
proposed FFTCC scheme to handle the uncertainties. The proposed
FFTCC scheme based IT2-FLC-PI can improve power oscillation damp-
ing and torque ripples compared to PIR controller. The comparative
analysis of the proposed scheme with existing methods in the literature
is presented in Table 5.
It is clear from above Table 5; the proposed scheme enhances the
LVRT capability of the grid-connected during symmetrical voltage sag.
The PI controller is unable to handle the nonlinear dynamics system
and unable to track the frequency. PIR controller is working on a
particular frequency, and it is unable to mitigate the harmonics content
under the wide range of frequency. SOGI-QSG-FLL is working in a
wide range of frequency; as a result, THD is reduced in the proposed
integrated algorithm. THD analysis during sub and super synchronous
speed is shown in Fig. 16(a) and Fig. 16(b) respectively.

6. Conclusion

Fig. 15. FFTCC with IT2-FLC-PI based SOGI-QSG-FLL VSDA (proposed scheme).
A SOGI-QSG-FLL based VSDA is proposed in this research work
to detect the voltage sag fast and accurately. The proposed VSDA is
compared with the other VSDA, and it has been seen that the detection
suppressed, as shown in Fig. 14(b). The transient rotor current is fully time of the voltage sag using the proposed scheme is 2.1 ms, which
suppressed by the FFTCC-based IT2-FLC-PI with SOGI-QSG-FLL VSDA is less than other VSDA. The proposed VSDA is integrated into the
proposed scheme, as shown in Fig. 15(b). novel FFTCC scheme-based IT2-FLC-PI controller to improve the LVRT
Stator inrush currents due to voltage sag are not suppressed as of grid-connected DFIG based WECS during symmetrical voltage sag.
shown in Figs. 13(c) and 14(c) because PI and PIR controllers are The third dimension of the IT2-FLC is capable of handling the uncertain
sensitive to parameter variation. The transient stator current is fully situation like wind speed fluctuation and power oscillation damping.

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

Table 4
Transient response comparison.
Scheme Rotor current DC- link voltage Active power of Reactive power Stator terminal Stator Torque
(A) (V) the DFIG (W) of DFIG (VAR) voltage (V rms) current (A) (N-m)
𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠 𝑡𝑠 %𝑀𝑝 𝐸𝑠𝑠
Scheme 1 1.4 87 0.05 1.35 0.43 0.006 1.25 95.9 0.04 1.35 26.85 0.020 1.25 86 0.05 1.8 96 0.05 1.39 95 0.07
Scheme 2 1.2 84 0.02 1.25 0.40 0.003 1.20 94.9 0.02 1.30 25.56 0.015 1.20 84 0.02 1.6 94 0.03 1.34 93 0.05
Proposed 1.1 80 0 1.20 0.35 0.001 1.15 94.3 0.01 1.25 24.12 0.001 1.10 80 0 1.2 90 0.01 1.20 90 0.01
scheme

Settling time = 𝑡𝑠 (s), Steady-state error = 𝐸𝑠𝑠 , Peak overshoot = %𝑀𝑝 .

Table 5
Comparative analysis of the proposed scheme with existing methods.
Control topology Crowbar dc-chopper dc reactor type SMES Steady state FFTC-PIR Proposed
circuit (Morren & (Pannell et al., fault current (Xiao et al., 2019) compensation controller scheme
DeHaan, 2005) 2013) limiter (Shahbabaei with PI based (Liang et al.,
Kartijkolaie et al., controller (Liang 2013)
2018) et al., 2010)
Type Hardware Hardware Hardware Hardware software Software Software
Transient rotor current High Poor High Medium Low Medium High
reduction capability during
voltage sag
Transient stator current Poor Poor Poor No Low Medium High
reduction capability during
voltage sag
Torque ripple suppression No No Medium Medium Low Medium High
capability during voltage sag
Uninterrupted active and No No No No No Yes Yes
relative power supply
Smooth active and No No No No No No Yes
reactive power supply
dc-link overvoltage reduction No Yes No Poor Poor Moderate High
capability during voltage sag
Voltage sag detection No No No No No No Yes
capability
THD reduction capability No No No No No No Yes

Fig. 16(a). THD calculation using PI, PIR and proposed SOGI-QSG-FLL algorithms (left to right) under sub-synchronous speed.

Fig. 16(b). THD calculation using PI, PIR and proposed SOGI-QSG-FLL algorithms (left to right) under super-synchronous speed.

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A. Chakraborty and T. Maity Control Engineering Practice 131 (2023) 105393

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THD is also reduced for the proposed scheme. The proposed integrated Hasan, S., Muttaqi, K. M., & Sutanto, D. (2020). Detection and characterization of
time-variant nonstationary voltage sag waveforms using segmented hilbert-huang
algorithm is applied in this work for symmetrical voltage sag but this
transform. IEEE Transactions on Industry Applications, 56, 4563–4574. http://dx.doi.
can be used in case of asymmetrical voltage sag also. org/10.1109/TIA.2020.2982850.
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Declaration of competing interest method based on multi-dimension characterisation. IET Generation, Transmission &
Distribution, 14, 486–493. http://dx.doi.org/10.1049/iet-gtd.2019.1038.
The authors declare that they have no known competing finan- Inci, M., Bayındır, KÇ, & Tümay, M. (2016). Improved synchronous reference frame
based controller method for multifunctional compensation. Electric Power Systems
cial interests or personal relationships that could have appeared to
Research, 141, 500–509. http://dx.doi.org/10.1016/j.epsr.2016.08.033.
influence the work reported in this paper. Kleber de Araújo, Lima F., Guerrero, J. M., Tofoli, F. L., Branco, CGC., & Dantas, J.
L. (2022). Fast and accurate voltage sag detection algorithm. International Journal
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Liang, J., Howard, D., Restrepo, J., & Harley, R. (2013). Feedforward transient
This work was supported by the Ministry of Human Resource Devel-
compensation control for DFIG wind turbines during both balanced and unbalanced
opment (MHRD), Government of India, through the Project, Establish- grid disturbances. IEEE Transactions on Industry Applications, 49, 1452–1463. http:
ment of Centre of Excellence for Training and Research under FAST: //dx.doi.org/10.1109/TIA.2013.2253439.
Centre of Excellence in Renewable Energy at IIT(ISM), Dhanbad, India, Liang, Q., & Mendel, J. M. (2000). Interval type-2 fuzzy logic systems: Theory and
under Grant F.No. 5-6/2013-TS-VlI. design. IEEE Transactions on Fuzzy Systems, http://dx.doi.org/10.1109/91.873577.
Liang, J., Qiao, W., & Harley, R. G. (2010). Feed-forward transient current control for
low-voltage ride-through enhancement of DFIG wind turbines. IEEE Transactions on
Appendix Energy Conversion, 25, 836–843. http://dx.doi.org/10.1109/TEC.2010.2048033.
LÓpez, J., Sanchis, P., Roboam, X., & Marroyo, L. (2007). Dynamic behavior of the
See Table 6. doubly fed induction generator during three-phase voltage dips. IEEE Transactions
on Energy Conversion, 22, 709–717. http://dx.doi.org/10.1109/TEC.2006.878241.
Mendel, J. M., John, R. I., & Liu, F. (2006). Interval type-2 fuzzy logic systems made
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