Digital Electronics MCQs

1.
A de-multiplexer is a combinational circuit that has

A) One input – B)One input – C) Many outputs - D)None of these
many outputs one output one input
2. A multiplexer is a combinational circuit that has
A) One input – B)One input – C) Many outputs - D)None of these
many outputs one output one input
3. The number of selection lines required for 1 to 32 DeMultiplexer ____5________

4. The number of selection lines required for 16 to 1 Multiplexer______4______
5. ____Op-Amp______is a basic comparator.
6. For even parity the number of 1’s in the data should be
A) Odd B) Even C) both D) None
7. For odd parity the number of 1’s in the data should be

A) Odd B) Even C) both D) None
8. What is a parity bit?

A) Adding an extra bit B) Removing extra bit C) Bit generation D) Total number of bits
9. Comparator has ____1______no.of outputs

10. If two inputs are active on a priority encoder, which will be coded on the output?
A) The higher value B) The lower value C) Neither of the inputs D) Both of the inputs
11. How many possible outputs would a decoder have with a 6-bit binary input?
A) 32 B) 64 C) 128 D) 16
12. How many possible outputs would a decoder have with a 4-bit binary input?
A) 32 B) 64 C) 128 D) 16
13. In a multiplexer, the selection of a particular input line is controlled by _________

A) Data controller B) Selection lines C) Logic gates D) Both data
controller & Gates
14. The logic circuits whose outputs at any instant of time depends only on the present input
are called _____Combinational Circuits___________
15. . A decimal counter has ___10___ states.
16. The logic circuits whose outputs at any instant of time depends on the present input and
also on the past outputs are called ____Sequential circuits____________
17. Synchronous counters are faster than ripple counters because
A) All flip flops are B) propagation delay C) they use faster flip D) all the above
clocked in parallel is additive flops
18. In the toggle mode, a JK flip-flop has J=_1__,K=_1__
19. ___________flipflop is used as latch
a) D b) T c) JK d) SR
20. ______Edge_____Triggering is used in flipflop .
21. The Characteristic equation of a T Flipflop is ______T XOR Q_________________
22. The Characteristic equation of a SR Flipflop is ________S+R’Q_______________
23. In the RESET mode, a SR flip-flop has S=_0__,R=_1__
24. Ripple counter is
A) Synchronous B) Asynchronous C) Clocked D ) Combinational
25. Race around condition occurs in ___JK________ flipflop.

26. The full form of SIPO is _____Serial in Parllel out______
A) Serial-in Parallel-out B) Parallel-in Serial-out
C)Serial-in Serial-out D) Serial-In Peripheral-Out
27. BCD counter is also known as ____________
A) Parallel counter B) Decade counter C) Synchronous counter D) VLSI counter
28. In 4-bit up-down counter, how many flip-flops are required?
a) 2 b) 3 c) 4 d) 5
29. Master-slave flipflop is used to overcome _______race-around ________condition in JK Flipflop
30.The minimum number of flipflops required for a mod 12 counter is___4____
31.The minimum number of flipflops required for a mod 6 counter is____3___

32.___3____ number of flipflops required to design 3 bit synchronous counter.
33.In____asynchronous______ sequential circuit all the flipflops are not clocked simultaneously.
34.To convert S-R to D flip flop________________ is used

A) AND Gate B) NOT Gate C) Shorted D) Grounded
35.What is the distinctive feature of PLA

A) Programmable B) Programmable AND C)Fixed AND array and D) None.
AND and OR array and fixed OR array programmable OR array
36.What is the istinctive feature of PAL

A)Programmable B) Programmable AND C)Fixed AND array and D) None.
37 . What is the distinctive feature of PROM

A)Programmable B) Programmable AND C)Fixed AND array and D) None.
38. . The full form of EPROM is __________

a) Easy Programmable Read Only Memory
b) Erasable Programmable Read Only Memory
c) Eradicate Programmable Read Only Memory
d) Easy Programmable Read Out Memory
39 . FPGA stands for __________
a) Full Programmable Gate Array
b) Full Programmable Genuine Array
c) First Programmable Gate Array
d) Field Programmable Gate Array
40. The inputs in the PLD is given through ____________
a) NAND gate b) OR gates c) NOR gates d) AND gates
41 Three major types of PLDs
are___SPLD________,____CPLD____,____FPGA____________(Field Programmable Gate
array
42. A _____flipflop_________ is called a single bit register
43.In 4 bit johnson ring counter ____8_______ number of states are used .
44. No.of flipflops required for decade counter is ___4______
45. ______D________ flip-flop is commonly used in the design of shift registers.
46.. Synchronous counters are ____faster_______ than asynchronous counters.
47.. Ripple counters are also called as _______asynchronous counters___________
48.Flip flop has __2__stable states.
49... A set of flipflops used to store binary data is called ____registers_____

_____RAM________is the example of Volatile memory.
50. Various types of ROMs are

____PROM______,__MPROM_____________________,_EPROM_,EEPROM_____________
____

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1.

A de-multiplexer is a combinational circuit that has

3. The number of selection lines required for 1 to 32 DeMultiplexer 5____

7. For odd parity the number of 1’s in the data should be

8. What is a parity bit?

9. Comparator has 1__no.of outputs

13. In a multiplexer, the selection of a particular input line is controlled by _________

25. Race around condition occurs in _JK______ flipflop.

31.The minimum number of flipflops required for a mod 6 counter is__3_

34.To convert S-R to D flip flop________________ is used

35.What is the distinctive feature of PLA

36.What is the istinctive feature of PAL

37 . What is the distinctive feature of PROM

38. . The full form of EPROM is __________

49... A set of flipflops used to store binary data is called registers_

50. Various types of ROMs are

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