SUS6160MN

Low Profile Overvoltage

Protection IC with
Integrated MOSFET
This device represents a new level of safety and integration by
combining an overvoltage protection circuit (OVP) with a dual 20 V http://onsemi.com
P−channel power MOSFET. The OVP is specifically designed to
protect sensitive electronic circuitry from overvoltage transients and MARKING
power supply faults. During such events, the IC quickly disconnects DIAGRAM
the input supply from the load, thus protecting it. The integration of
the additional transistor and power MOSFET reduces layout space and
1 SUS
promotes better charging performance.
6160
The IC is optimized for applications that use an external AC−DC QFN22
ALYWG
adapter or a car accessory charger to power a portable product or CASE 485AT
G
recharge its internal batteries.
SUS6160 = Device Code
Features A = Assembly Location
• Overvoltage Turn−Off Time of Less Than 1.5 ms L = Wafer Lot
• Undervoltage Lockout Protection; 3.0 V, Nominal Y = Year
W = Work Week
• High Accuracy Undervoltage Threshold of 5.0% G = Pb−Free Package
• −20 V Integrated P−Channel Power MOSFET (Note: Microdot may be in either location)
• Low RDS(on) = 64 mW @ −4.5 V
• Compact 3.0 x 4.0 mm QFN Package
• Maximum Solder Reflow Temperature @ 260°C ORDERING INFORMATION
• This is a Pb−Free Device Device Package Shipping†

Benefits SUS6160MNTWG QFN22 3000 /

(Pb−Free) Tape & Reel
• Provide Battery Protection
• Integrated Solution Offers Cost and Space Savings †For information on tape and reel specifications,
including part orientation and tape sizes, please
• Integrated Solution Improves System Reliability refer to our Tape and Reel Packaging Specification
• Optimized for Commercial PMUs from Top Suppliers Brochure, BRD8011/D.

Applications
• Portable Computers and PDAs
• Cell Phones and Handheld Products
• Digital Cameras

© Semiconductor Components Industries, LLC, 2008 Publication Order Number:

December, 2008 − Rev. 1 SUS6160MN/D

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 SUS6160MN

GND
N/C

N/C

En
In
22 18

Out 1 17 N/C

N/C
N/C N/C

Gate1 Flag

Drain1 Gate2

FETREG Drain2
Drain1 FETSW
Drain2
Drain1

Drain1 6 12 N/C

7 Source2 11
Source1

Drain2

Drain2
Drain1

(Top View)

Figure 1. Pinout

Vbat

15 1 8

FLAG 3
ChargeSW
20 FETSW
Wall Adaptor 4, 5, 6, 7
IN OUT

10
EN GND
ChargeREG
SUS6160 14
FETREG

18 19 9, 11, 13

Battery

Figure 2. Typical Charging Solution

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 SUS6160MN

MAXIMUM RATINGS (TJ = 25°C, unless otherwise stated)

Rating Symbol Min Max Unit
VIN to Ground VIN −0.3 21 V
OUT, EN, FLAG Pins Voltage to Ground VOUT, VEN, VFLAG −0.3 7.0 V
Maximum Current from VIN to VOUT (PMOS) Imax 600 mA
Drain−to−Source Voltage VDSS −20 V
Gate−to−Source Voltage VGS −8.0 8.0 V
Continuous Drain Current, Steady State ID −2.0 A
Pulsed Drain Current, tp = 10 ms IDM −4.0 A
Source Current IS −1.1 A
Operating Ambient Temperature TA −40 85 °C
Storage Temperature TSTG −55 150 °C
Operating Junction Temperature TJ 150 °C
Thermal Resistance (Note 1) qJA °C/W
1 in2 (645 mm2) (All devices fully enhanced)
OVP FET 68
FETSW 42
FETREG 46
1 in2 (645 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET 43
FETSW 39
FETREG 80
0.25 in2 (161 mm2) (All devices fully enhanced)
OVP FET 79
FETSW 53
FETREG 56
0.25 in2 (161 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET 53
FETSW 49
FETREG 92

ESD Performance (Human Body Model) Pins 1, 15, 18, 19, 20 − 2.5 kV
Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 1 oz. copper, double sided board. Thermal impedance requires total for DT calculations. See example in thermal description.

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 SUS6160MN

PIN DESCRIPTION
Pin Name Description
1 Out This pin is the output of the internal OVP chip. It must be connected to the source of the upper
FET (Pin 8).

3 Gate FETSW This pin is the gate of the upper FET which is normally used for a switch in series with the battery.
It is controlled by the PMU.

4, 5, 6, 7 Drain FETSW These pins are the drain of the upper FET. For the lowest on resistance connect all pins together.
This set of pins must be connected to the source of the lower (regulator) FET, Pin 10.

8 Source FETSW This pin is the source of the upper FET and must be connected to the output pin of the internal
OVP chip (Pin 1).

9, 11, 13 Drain FETREG These pins are the drain of the lower FET which is normally used for the regulation function. It
connects to the positive terminal of the battery.

10 Source FETREG This pin is the source of the lower FET and must be connected to the drain pins of the upper FET.
12 N/C This pin has no internal connections and is isolated from all internal circuitry within the chip.
14 Gate FETREG This pin is the gate of the lower FET which is normally used for the regulation function in series
with the battery. It is controlled by the PMU.

15 FLAG The fault flag is an open drain output and therefore requires a pullup resistor. The FLAG pin will be
driven low when the input voltage exceeds the OVLO trip level.

2, 16, 17, N/C These pins are connected to the ground of the analog chip. This is a medium impedance
21, 22 connection and should not be used for the ground signal. These pins should either be left floating
or connected to ground, but not any other potential. If these pins are connected to ground, the
ground pin (19) must still be used.
18 EN The ENABLE pin must be held low for normal operation. When this pin is tied high the unit will be
shut down. The state of the enable pin has no impact on the FAULT pin.

19 Gnd This is the ground reference pin for the internal OVP chip.
20 In This pin is the input to the internal OVP chip and connects to the wall, or car adaptor.

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 SUS6160MN

OVP ELECTRICAL CHARACTERISTICS

(Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic Symbol Conditions Min Typ Max Unit
Input Voltage Range Vin 1.2 20 V
Undervoltage Lockout UVLO Vin falls down UVLO threshold 2.85 3.0 3.15 V
Threshold

Undervoltage Lockout UVLOhyst 30 50 70 mV

Hysteresis

Overvoltage Lockout Threshold OVLO Vin rises up OVLO threshold 6.9 7.07 7.4 V
Overvoltage Lockout Hysteresis OVLOhyst 50 100 125 mV
Vin versus Vout Dropout Vdrop Vin = 5 V, I charge = 500 mA 105 200 mV
Supply Quiescent Current Idd No Load, Vin = 5.25 V 24 35 mA
OVLO Supply Current Iddovlo Vin = 8 V 50 85 mA
Output Off State Current Istd Vin = 5.25 V, EN = 1.2 V 26 37 mA
FLAG Output Low Voltage Volflag Vin > OVLO, Sink 1 mA on FLAG pin 400 mV
FLAG Leakage Current FLAGleak FLAG level = 5 V 5.0 nA
EN Voltage High Vih Vin from 3.3 V to 5.25 V 1.2 V
EN Voltage Low Vol Vin from 3.3 V to 5.25 V 0.4 V
EN Leakage Current ENleak EN = 5.5 V or GND 170 nA
TIMINGS
Start Up Delay ton From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9 4.0 15 ms
FLAG going up Delay tstart From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 3.0 ms
10

Output Turn Off Time toff From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11 0.8 1.5 ms
Vin increasing from normal operation to >OVLO at
1V/ms. No output capacitor.
Alert Delay tstop From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 & 1.0 2.0 ms
12
Vin increasing from normal operation to >OVLO at
1V/ms
Disable Time tdis From EN 0.4 to 1.2V to Vout ≤ 0.3V, See Fig 5 & 2.0 ms
13
Vin = 4.75 V. No output capacitor.
Thermal Shutdown Temperature Tsd 150 °C
Thermal Shutdown Hysteresis Tsdhyst 30 °C
NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design.

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 SUS6160MN

MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted, all parameters apply to both FETSW and
FETREG)

Characteristic Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(Br)DSS VGS = 0 V, ID = −250 mA −20 V
Drain−to−Source Breakdown Voltage V(Br)DSS/TJ −15 mV/°C
Temperature Coefficient
Zero Gate Voltage Drain Current IDSS VGS = 0 V TJ = 25°C −1.0 mA
VDS = −16 V TJ = 85°C −5.0
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = "8.0 V "100 nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA −0.45 −1.5 V
Gate Threshold Temperature Coefficient VGS(TH)/TJ 2.7 mV/°C
Drain−to−Source On Resistance RDS(ON) VGS = −4.5 V, ID = −1.0 A 64 80 mW
VGS = −4.5 V, ID = −0.6 A 62 80
Forward Transconductance gFS VDS = −10 V, ID = −2.9 A 7.0 S
CHARGES, CAPACITANCES, AND GATE RESISTANCE
Input Capacitance CISS 750 pF
VGS = 0 V, f = 1.0 MHz,
Output Capacitance COSS VDS = −16 V 100
Reverse Transfer Capacitance CRSS 45
Total Gate Charge QG(TOT) 7.6 8.6 nC
Gate−to−Source Charge QGS VGS = −4.5 V, VDS = −16 V, 1.3
ID = −2.6 A
Gate−to−Drain Charge QGD 2.6
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time td(ON) 5.5 ns
Rise Time tr VGS = −4.5 V, VDD = −16 V, 12
Turn−Off Delay Time td(OFF) ID = −2.6 A, RG = 2.0 W 32
Fall Time tf 23
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V, IS = −1.1 A −0.8 −1.2 V
Reverse Recovery Time tRR 20 ns
Charge Time ta VGS = 0 V, dIS/dt = 100 A/ms, 15
Discharge Time tb IS = 1.0 A 5
Reverse Recovery Charge QRR 0.01 mC
2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures

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 SUS6160MN

<OVLO
Vin UVLO OVLO
Vin
ton toff
Vin − RDS(on) x I Vout
0.8 Vin
Vout Vin − (RDS(on) I)
0.3
tstart V
FLA
FLAG 1.2 V G tstop
0.4
V
Figure 3. Start Up Sequence Figure 4. Shutdown on Over Voltage
Detection

EN 1.2 V EN 1.2 V

tdis OVLO
Vout Vin UVLO
0.3 V
Vin − RDS(on) x I
3 ms
FLAG
FLAG

Figure 5. Disable on EN = 1 Figure 6. FLAG Response with EN = 1

CONDITIONS
IN OUT
VIN > OVLO or VIN < UVLO

Voltage Detection

Figure 7.

CONDITIONS
IN OUT
UVLO < VIN < OVLO

Voltage Detection

Figure 8.

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 SUS6160MN

TYPICAL OPERATING CHARACTERISTICS

Figure 9. Startup Figure 10. FLAG Going Up Delay

Vin = Ch1, Vout = Ch3 Vout = Ch3, FLAG = Ch2

Figure 11. Output Turn Off Time Figure 12. Alert Delay
Vin = Ch1, Vout = Ch2 Vout = Ch1, FLAG = Ch3

Figure 13. Disable Time Figure 14. Thermal Shutdown

EN = Ch1, Vout = Ch2, FLAG = Ch3 Vin = Ch1, Vout = Ch2, FLAG = Ch3

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 SUS6160MN

TYPICAL OPERATING CHARACTERISTICS

450

400

350 Vin = 3.6 V

300

RDS(on) (mW)
250
Vin = 5 V
200

150

100
50
0
−50 0 50 100 150
TEMPERATURE (°C)

Figure 15. Direct Output Short Circuit Figure 16. RDS(on) vs. Temperature
(Load = 500 mA)

180
IQ, SUPPLY QUIESCENT CURRENT (mA)

160

140
120
100
125°C
80 25°C
60

40 −40°C
20
0
1 3 5 7 9 11 13 15 17 19 21
Vin, INPUT VOLTAGE (V)

Figure 17. Supply Quiescent Current vs. Vin

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 SUS6160MN

TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)

10 9
VGS = −10 V to −2.8 V TJ = 25°C
9 8

−ID, DRAIN CURRENT (AMPS)

−ID, DRAIN CURRENT (AMPS)

8 7
−2.4 V
7
6
6
5
5
4
4
3
3
125°C
2 −1.8 V 2
−1.6 V 1 25°C
1 TJ = −55°C
−1.4 V
0 0
0 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 4
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 18. On−Region Characteristics Figure 19. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.2 1.5
0.18 VGS = −4.5 V

RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE
0.16 1.3
0.14 VGS = −2.5 V

0.12 1.1
0.1
0.08 VGS = −4.5 V 0.9
0.06
0.04 0.7
0.02
0 0.5
2 3 4 5 6 −50 −25 0 25 50 75 100 125 150
−ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)

Figure 20. On−Resistance vs. Drain Current Figure 21. On−Resistance Variation with
and Gate Voltage Temperature

10000
VGS = 0 V

1000 TJ = 125°C
−IDSS, LEAKAGE (nA)

TJ = 100°C
100

10

1
TJ = 25°C

0.1
2 3 4 5 6 7 8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 22. Drain−to−Source Leakage Current

vs. Voltage

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TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)

−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1000 5
TJ = 25°C QT
900
800 4
C, CAPACITANCE (pF)

700 Ciss
600 3
500
Q1 Q2
400 2
300
200 1
Coss ID = −2.7 A
100 Crss TJ = 25°C
0 0
0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8
−VGS −VDS Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 24. Gate−to−Source and
Figure 23. Capacitance Variation Drain−to−Source Voltage vs. Total Gate Charge

1000 5
VDD = −10 V VGS = 0 V
−IS, SOURCE CURRENT (AMPS)

ID = −1.0 A TJ = 25°C
VGS = −4.5 V 4

100
t, TIME (ns)

td(off)
tf 2
10 tr
td(on)
1

1 0
1 10 100 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
RG, GATE RESISTANCE (OHMS) −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 25. Resistive Switching Time Variation Figure 26. Diode Forward Voltage vs. Current
vs. Gate Resistance

100
−I D, DRAIN CURRENT (AMPS)

10 10 ms
100 ms
1 ms
1 10 ms
VGS = −8 V
SINGLE PULSE
TC = 25°C
0.1
RDS(on) LIMIT dc
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 1 10 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 27. Maximum Rated Forward Biased

Safe Operating Area

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 SUS6160MN

Operational Description in the event of an overvoltage condition to protect the output

The SUS6160 provides overvoltage protection for from a positive overvoltage condition. The low Rds(on),
positive voltages up to 20 V. A P−Channel FET protects the during normal operation will minimize the voltage drop
load connected on the Vout pin, against positive overvoltage across the device. (See Figure 16).
conditions. The Output follows the VBUS level until OVLO
ESD Tests
threshold is reached.
The SUS6160 meets the requirements of the
Undervoltage Lockout (UVLO) IEC61000*4*2, level 4 (Input pin, 1 mF mounted on
To ensure proper operation under all conditions, the board). For the air discharge condition, Vin is protected up
device has a built−in undervoltage lock out (UVLO) circuit. to $15 kV. In the contact condition, Vin is protected up to
As the input ramps from 0 V, the output remains ±8 kV ESD. Please refer to Figure 29 to see the IEC
disconnected from input until the Vin voltage is above 3.2 V 61000−4−2 electrostatic discharge waveform.
nominal. The FLAG output is pulled to low as long as Vin
does not reach the UVLO threshold. This circuit
incorporates hysteresis on the UVLO pin to provide noise
immunity to transient condition.

Figure 29. IEC 61000−4−2 Curve

Figure 28. Output Characteristic vs. Vin Thermal Impedance

Due to cross heating of the three dice in the package, the
Overvoltage Lockout (OVLO) equivalent thetas are given for this device rather than the
To protect connected systems on Vout Pin from individual thetas. To calculate the junction temperatures of
overvoltage, the device has a built−in overvoltage lock out a single die, the total power must be used. For example,
(OVLO) circuit. During an overvoltage condition, the given the following parameters, the die temperatures will be
output remains disabled until the input voltage is reduced to as shown:
below the OVLO hysteresis level. The FLAG output is tied Idc = 500 mA
to low until Vin is higher than OVLO. This circuit RDS(on) OVP = 305 mW
incorporates hysteresis on the OVLO pin to provide noise RDS(on) FETsw = 72 mW
immunity from transient conditions. FETreg has a 1.0 V Drop
FLAG Output Board copper area = 161 mm2
The SUS6160 provides a FLAG output, which alerts Calculate the individual power dissipations:
external systems that a fault has occurred. This pin goes low POVP = (0.50 A)2 x .305 W = 0.076 W
as soon as the OVLO threshold is exceeded. When Vin level PSW = (0.50 A)2 x .072 W = 0.018 W
recovers to its normal range the FLAG is set high. PREG = 0.50 A x 1.0 V = 0.50 W
The FLAG Pin is an open drain output, thus a pullup PTOT = 0.076 + 0.018 + 0.50 = 0.594 W
resistor (typically 1 MW − Minimum 10 kW) must be From the Maximum ratings table for thetas, 161 mm2 and
provided to Vbattery. 1 V drop across FETREG:
EN Input OVP FET 53°C/W
To enable normal operation, the EN pin shall be forced FETSW 49°C/W
low or connected to ground. A high level on the pin FETREG 92°C/W
disconnects the OUT Pin from IN Pin. EN does not override The die temperature rises above ambient are:
an OVLO or UVLO fault. TOVP = 53°C/W x 0.594 W = 32°C
Internal PMOS FET TSW = 49°C/W x 0.594 W = 29°C
The SUS6160 includes an internal PMOS FET which TREG = 92°C/W x 0.594 W = 55°C
connects the input to the output pin. This FET is turned off

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 SUS6160MN

PACKAGE DIMENSIONS

QFN22, 3x4, 0.5P

CASE 485AT−01
ISSUE B

D A L L NOTES:
1. DIMENSIONING AND TOLERANCING PER

ÈÈÈ
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
L1

ÈÈÈ
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.

ÈÈÈ
PIN 1 DETAIL A
REFERENCE 4. COPLANARITY APPLIES TO THE EXPOSED
OPTIONAL
PADS AS WELL AS THE TERMINALS.

ÈÈÈ
CONSTRUCTIONS
MILLIMETERS

ÉÉ ÉÉÉ
E DIM MIN NOM MAX
A3 A 0.80 0.90 1.00
EXPOSED Cu MOLD CMPD

ÉÉ ÉÉÉ
ÇÇÇ
A1 0.00 0.025 0.05
A3 0.20 REF
2X b 0.20 0.25 0.30
D 3.00 BSC
0.15 C D2 1.45 1.50 1.55
A1 D3 0.52 0.57 0.62
2X
DETAIL B D4 1.02 1.07 1.12
0.15 C OPTIONAL E 4.00 BSC
TOP VIEW CONSTRUCTIONS E2 1.05 1.10 1.15
E3 1.30 1.35 1.40
DETAIL B E4 1.40 1.45 1.50
0.10 C e 0.50 BSC
K 0.25 −−− −−−
A L 0.30 0.325 0.35
25X
L1 −−− −−− 0.15
0.08 C G 1.35 1.40 1.50
NOTE 4
A3 SEATING
G1 0.95 1.05 1.15
SIDE VIEW A1 C PLANE
G2 0.855 0.885 0.915

SOLDERING FOOTPRINT*
G1
3.30
D3
22X L 1.55
D4
DETAIL A 7
0.50 0.925
PITCH
12 PACKAGE
OUTLINE
G E3 E4 1

1.47 1.21

G 22X b
E2 4.30
1 0.10 C A B
0.05 C NOTE 3 1.47 1.47 1.58
16X K 18
e
G2
D2
22X
BOTTOM VIEW 0.52 0.39
1.14
22X 0.30
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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