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    Programmable Logic Devices(PLDs)

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    Thirumala Naik Meghavath

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    © All Rights Reserved
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    Programmable Logic Devices(PLDs)

    Uploaded by

    Thirumala Naik Meghavath
    8 views14 pages

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    8 views14 pages

    Programmable Logic Devices(PLDs)

    Uploaded by

    Thirumala Naik Meghavath

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    Programmable Logic

    Devices(PLDs)
    ROM-based Designs:
    Combinational Circuits
    Example 2: X^2 look-up table, X is 3-bit binary number
     Specification: Use a ROM to implement a combinational circuit that accepts a 3-bit
    binary number at the input and generates its square at the output.

     Formulation:
    8 x 6 bits ROM, Truth Table 
     Observations on the truth table:
    1. Output B0 = Input A0
    2. Output B1 = Always 0
    No need to ‘store’ data for B0 and B1 8
    This reduces the size of the ROM required from 8 x 6 bits to 8 x 4 bits
    Locations

    6 bits
    ROM-based Designs:
    Combinational Circuits
    Example 2, Continued

    Truth Table for Reduced ROM

    8
    Locations

    4 bits
    Implementations of the X2 Look-up Table:
    PROGRAMMABLE LOGIC ARRAY (PLA)
    • In PLAs, instead of using a decoder as in PROMs, a number (k) of AND
    gates is used where k < 2^ n, (n is the number of inputs).
    • Each of the AND gates can be programmed to generate a product term of
    the input variables and does not generate all the minterms as in the ROM.
    • The AND and OR gates inside the PLA are initially fabricated with the links
    (fuses) among them.
    • The specific Boolean functions are implemented in sum of products form
    by opening appropriate links and leaving the desired connections.
    • A block diagram of the PLA is shown in the figure. It consists of n inputs,
    m outputs, and k product terms. The product terms constitute a group of k
    AND gates each of 2^n inputs.
    • Links are inserted between all n inputs and their complement values to
    each of the AND gates. Links are also provided between the outputs of the
    AND gates and the inputs of the OR gates.
    PROGRAMMABLE ARRAY LOGIC (PAL):
    • Example: Implement the following Boolean functions using
    the PAL device,
    W(A, B, C, D) = Σm(2, 12, 13)
    X(A, B, C, D) = Σm(7, 8, 9, 10, 11, 12, 13, 14, 15)
    Y(A, B, C, D) = Σm(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
    Z(A, B, C, D) = Σm(1, 2, 8, 12, 13)
    Simplifying the 4 functions to a minimum number of terms
    results in the following Boolean functions:
    W = ABC’ + A’B’CD’
    X = A + BCD
    Y = A’B + CD + B’D’
    Z = ABC’ + A’B’CD + AC’D’ + A’B’C’D =W +AC’D’ + A’B’C’D
    2. Programmable Array Logic (PAL)
    Sum of a fixed number of products
    • 4-input, 4-output PAL Product
    term
    AND gates inputs
    A A B B C C D D W W

    with fixed, 3-input OR 1

    2 W
    terms 3 X

    A
    All fuses intact
    4 (always 5 0)

    5 F1

    8 F2

    10

    11

    12
    X Fuse intact
    D
    1 Fuse blown

    A A B B C C D D W W

    0 1 2 3 4 5 6 7 8 9
    PAL programming table

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