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SGLS160B − APRIL 2003 − REVISED SEPTEMBER 2008


    
 


 

FEATURES DESCRIPTION
D Qualified for Automotive Applications The TPS791xx family of low-dropout (LDO)
D ESD Protection Exceeds 2000 V Per low-power linear voltage regulators features high
MIL-STD-883, Method 3015; Exceeds 200 V power supply rejection ratio (PSRR), ultralow
Using Machine Model (C = 200 pF, R = 0) noise, fast start-up, and excellent line and load
D 100-mA Low-Dropout Regulator With EN transient responses in a small outline, SOT23,
package. Each device in the family is stable with
D Available in 1.8-V, 3.3-V, 4.7-V, and Adj. a small 1-µF ceramic capacitor on the output.
D High PSRR (70 dB at 10 kHz)
The family uses an advanced, proprietary
D Ultralow Noise (15 µVRMS) BiCMOS fabrication process to yield extremely
D Fast Start-Up Time (63 µs) low dropout voltages (e.g., 38 mV at 100 mA,
D Stable With Any 1-µF Ceramic Capacitor TPS79147). Each device achieves fast start-up
times (approximately 63 µs with a 0.001 µF
D Excellent Load/Line Transient
bypass capacitor) while consuming very low
D Very Low Dropout Voltage quiescent current (170 µA typical). Moreover,
(38 mV at Full Load, TPS79147) when the device is placed in standby mode, the
D 5-Pin SOT23 (DBV) Package supply current is reduced to less than 1 µA. The
D TPS792xx Provides EN Options TPS79118 exhibits approximately 15 µVRMS of
output voltage noise with a 0.1 µF bypass
capacitor.
APPLICATIONS
Applications with analog components that are
D VCOs
noise sensitive, such as portable RF electronics,
D RF benefit from the high PSRR and low noise
D Bluetooth, Wireless LAN features as well as the fast response time.

ORDERING INFORMATION
TJ VOLTAGE PACKAGE PART NUMBER SYMBOL
1.2 to 5.5 V TPS79101DBVRQ1(1) PEU1
1.8 V SOT23 TPS79118DBVRQ1(1) PER1
−40°C to 125°C
3.3 V (DBV) TPS79133DBVRQ1(1) PES1
4.7 V TPS79147DBVRQ1(1)(2) PET1
(1) The DBVR indicates tape and reel of 3000 parts.
(2) This part is Product Preview.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark owned by the Bluetooth SIG, Inc.

 
 !"#$! % &'""($ #% ! )'*+&#$! ,#$(- "!,'&$% Copyright  2008, Texas Instruments Incorporated
&!!" $! %)(&&#$!% )(" $.( $("% !
(/#% %$"'($% %$#,#", 0#""#$1-
"!,'&$! )"!&(%%2 ,!(% !$ (&(%%#"+1 &+',( $(%$2 ! #++ )#"#($("%-

 
  

  
  
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SGLS160B − APRIL 2003 − REVISED SEPTEMBER 2008

DBV PACKAGE TPS79133 TPS79133

(TOP VIEW) RIPPLE REJECTION OUTPUT SPECTRAL NOISE DENSITY
vs vs
IN 1 5 OUT
FREQUENCY FREQUENCY
100 0.4
GND 2

Hz
VI = 4.3 V
90 Co = 10 µF 0.35 VO = 4.3 V

µ V/
EN 3 4 BYPASS C(byp) = 0.01 µF Co = 1 µF
80 IO = 100 mA 0.3 C(byp) = 0.1 µF

Ripple Rejection − dB

Output Spectral Noise Density −

Fixed Option
70 0.25
DBV PACKAGE IO = 100 mA
60 0.2
(TOP VIEW)
50 IO = 10 mA 0.15
IN 1 6 OUT IO = 1 mA
40 0.1
GND 2 5 FB
30 0.05
EN 3 4 BYPASS
20 0
10 100 1k 10 k 100 k 1M 10 M 100 1k 10 k 100 k
Adjustable Option f − Frequency − Hz f − Frequency − Hz

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
TPS79101, TPS79118
TPS79133, TPS79147
Input voltage range(2) −0.3 V to 6 V
Voltage range at EN −0.3 V to VI + 0.3 V
Voltage on OUT −0.3 V to 6 V
Peak output current Internally limited
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
Continuous total power dissipation See Dissipation Rating Table
Operating virtual junction temperature range, TJ −40°C to 150°C
Operating ambient temperature range, TA −40°C to 85°C
Storage temperature range, Tstg −65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

PACKAGE DISSIPATION RATING

DERATING FACTOR TA ≤ 25°C TA = 70°C TA = 85°C
BOARD PACKAGE RθJC RθJA
ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
Low K(1) DBV 63.75°C/W 256°C/W 3.906 mW/°C 391 mW 215 mW 156 mW
High K(2) DBV 63.75°C/W 178.3°C/W 5.609 mW/°C 561 mW 224 mW 308 mW
(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
Input voltage, VI (1) 2.7 5.5 V
Continuous output current, IO (2) 0 100 mA
Operating junction temperature, TJ −40 125 °C
(1) To calculate the minimum input voltage for your maximum output current, use the following formula:
VI(min) = VO(max) + VDO (max load)
(2) Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.

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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, (TJ = −40 to 125 °C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF,
Co(byp)= 0.01 µF (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TJ = 25°C, 1.22 V ≤ VO ≤ 5.2 V VO
TPS79101 0 µA< IO < 100 mA(1),
0.98 VO 1.02 VO
1.22 V ≤ VO ≤ 5.2 V
TJ = 25°C 1.8
TPS79118
Output voltage 0 µA < IO < 100 mA, 2.8 V < VI < 5.5 V 1.764 1.836 V
TJ = 25°C 3.3
TPS79133
0 µA < IO < 100 mA, 4.3 V < VI < 5.5 V 3.234 3.366
TJ = 25°C 4.7
TPS79147
0 µA < IO < 100 mA, 5.2 V < VI < 5.5 V 4.606 4.794
0 µA < IO < 100 mA, TJ = 25°C 170
Quiescent current (GND current) µA
A
0 µA < IO < 100 mA 250
Load regulation 0 µA < IO < 100 mA, TJ = 25°C 5 mV
VO + 1 V < VI ≤ 5.5 V, TJ = 25°C 0.05
Output voltage line regulation (∆VO/VO)(2) %/V
VO + 1 V < VI ≤ 5.5 V 0.12
C(byp) = 0.001 µF 32
BW = 100 Hz to 100 kHz, C(byp) = 0.0047 µF 17
Output noise voltage (TPS79118) µV
VRMS
IO = 100 mA, TJ = 25
25°C
C C(byp) = 0.01 µF 16
C(byp) = 0.1 µF 15
C(byp) = 0.001 µF 53
RL = 33 Ω, Co = 1 µF,
F,
Time, start-up (TPS79133) C(byp) = 0.0047 µF 67 µs
TJ = 25°C
C(byp) = 0.01 µF 98
Output current limit VO = 0 V(1) 285 600 mA
UVLO threshold VCC rising 2.25 2.65 V
UVLO hysteresis TJ = 25°C, VCC rising 100 mV
(1) The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum output current
is 100 mA.
(2) If VO ≤ 1.8 V then VImin = 2.7 V, VImax = 5.5 V:

V
O
ǒV Imax * 2.7 VǓ
Line regulation (mV) + ǒ%ńVǓ 1000
100

If VO ≥ 2.5 V then VImin = VO + 1 V, VImax = 5.5 V:

ǒ ǒ
VO V Imax * VO ) 1 V ǓǓ
Line regulation (mV) + ǒ%ńVǓ 1000
100

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ELECTRICAL CHARACTERISTICS continued

over recommended operating free-air temperature range, (TJ = −40 to 125 °C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF,
Co(byp)= 0.01 µF (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Standby current EN = VI, 2.7 V < VI < 5.5 V 0.07 1 µA
High level enable input voltage 2.7 V < VI < 5.5 V 2 V
Low level enable input voltage 2.7 V < VI < 5.5 V 0.7 V
Input current (EN) EN = VI −1 1 µA
f = 100 Hz, TJ = 25°C, IO = 10 mA 80
f = 100 Hz, TJ = 25°C, IO = 100 mA 75
TPS79118
f = 10 kHz, TJ = 25°C, IO = 100 mA 72
f = 100 kHz, TJ = 25°C, IO = 100 mA 45
Power supply ripple rejection dB
f = 100 Hz, TJ = 25°C, IO = 10 mA 70
f = 100 Hz, TJ = 25°C, IO = 100 mA 75
TPS79133
f = 10 kHz, TJ = 25°C, IO = 100 mA 73
f = 100 kHz, TJ = 25°C, IO = 100 mA 37
IO = 100 mA, TJ = 25°C 50
TPS79133
IO = 100 mA 90
Dropout voltage(1) mV
IO = 100 mA, TJ = 25°C 38
TPS79147
IO = 100 mA 70
(1) IN voltage equals VO(typ) − 100 mV; The TPS79118 dropout voltage is limited by the input voltage range limitations.

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FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION

VIN VOUT

UVLO Current
Sense
ILIM SHUTDOWN
R1
GND _ +
FB
EN
R2
UVLO

Thermal
Shutdown External to
the Device

Bandgap 250 kΩ Vref

VIN Bypass
Reference

FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION

VIN VOUT

UVLO Current
Sense
GND SHUTDOWN
ILIM
R1
_ +
EN

UVLO
R2
Thermal
Shutdown

Bandgap 250 kΩ Vref

VIN Bypass
Reference

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME ADJ FIXED
BYPASS 4 4 An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates
a low-pass filter to further reduce regulator noise.
EN 3 3 I The EN terminal is an input which enables or shuts down the device. When EN is a logic high, the device
will be in shutdown mode. When EN is a logic low, the device will be enabled.
FB 5 N/A I This terminal is the feedback input voltage for the adjustable device.
GND 2 2 Regulator ground
IN 1 1 I The IN terminal is the input to the device.
OUT 6 5 O The OUT terminal is the regulated output of the device.

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TYPICAL CHARACTERISTICS

TPS79118 TPS79133 TPS79118

OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE
vs vs vs
OUTPUT CURRENT OUTPUT CURRENT JUNCTION TEMPERATURE
1.803 3.303 1.82
VI = 2.8 V VI = 4.3 V VI = 2.8 V
Co = 10 µF 1.815 Co = 10 µF
1.802 3.302 Co = 10 µF
TJ = 25° C TJ = 25° C

V O − Output Voltage − V
1.81
V O − Output Voltage − V

V O − Output Voltage − V
1.801 3.301
1.805
IO = 1 mA
1.8 3.3 1.8

1.795
1.799 3.299
IO = 100 mA
1.79
1.798 3.298
1.785

1.797 3.297 1.78

0 20 40 60 80 100 0 20 40 60 80 100 −40 −25 −10 5 20 35 50 65 80 95 110 125
IO − Output Current − mA IO − Output Current − mA TJ − Junction Temperature − °C

Figure 1 Figure 2 Figure 3

TPS79133 TPS79133 TPS79118

OUTPUT VOLTAGE GROUND CURRENT OUTPUT SPECTRAL NOISE DENSITY
vs vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
3.32 260 FREQUENCY
VI = 4.3 V 0.2

Hz
VI = 4.3 V
Co = 10 µF 240 Co = 10 µF 0.18 VI = 2.8 V
µ V/
3.31 Co = 1 µF
0.16
V O − Output Voltage − V

220
Ground Current − µ A

C(byp) = 0.1 µF
Output Spectral Noise Density −

IO = 1 mA 0.14
3.3 200 IO = 1 mA
0.12 IO = 100 mA
180
0.1
3.29 IO = 100 mA IO = 100 mA
160 0.08 IO = 1 mA
140 0.06
3.28
0.04
120
0.02
3.27 100
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125 0
100 1k 10 k 100 k
TJ − Junction Temperature − °C TJ − Junction Temperature − °C
f − Frequency − Hz
Figure 4 Figure 5 Figure 6

TPS79118 TPS79118 TPS79133

OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
0.25 1.2 0.4
Hz
Hz

Hz

IO = 0.001 µF VI = 2.8 V
VI = 2.8 V IO = 100 mA 0.35 VI = 4.3 V
µ V/
µ V/

µ V/

0.2 Co = 10 µF 1 Co = 10 µF Co = 1 µF
IO = 1 mA C(byp) = 0.1 µF 0.3 C(byp) = 0.1 µF
Output Spectral Noise Density −
Output Spectral Noise Density −

Output Spectral Noise Density −

0.8 IO = 0.0047 µF 0.25

0.15
IO = 100 mA
IO = 100 mA 0.2
0.6 IO = 0.1 µF
0.1 0.15
0.4 IO = 0.01 µF IO = 1 mA
0.1
0.05
0.2 0.05

0 0 0
100 1k 10 k 100 k 100 1k 10 k 100 k 100 1k 10 k 100 k
f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz
Figure 7 Figure 8 Figure 9

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TYPICAL CHARACTERISTICS

TPS79133 TPS79133
OUTPUT SPECTRAL NOISE DENSITY OUTPUT SPECTRAL NOISE DENSITY ROOT MEAN SQUARED OUTPUT NOISE
vs vs vs

µ V (RMS)
FREQUENCY FREQUENCY BYPASS CAPACITANCE
0.4 2 70

Hz
Hz

VI = 4.3 V BW = 100 Hz to 100

VI = 4.3 V 1.8 IO = 0.001 µF
0.35 IO = 100 mA 60 kHz

RMS − Root Mean Squared Output Noise −

µ V/
µ V/

Co = 10 µF 1.6 Co = 10 µF
0.3 C(byp) = 0.1 µF
50

Output Spectral Noise Density −

Output Spectral Noise Density −

1.4
0.25 IO = 0.0047 µF
1.2 VO = 3.3 V
IO = 100 mA 40
0.2 1 IO = 0.1 µF
30
0.15 0.8
IO = 1 mA IO = 0.01 µF
0.6 20 VO = 1.8 V
0.1
0.4
0.05 10
0.2
0 0 0
100 1k 10 k 100 k 100 1k 10 k 100 k 0.001 0.01 0.1
f − Frequency − Hz f − Frequency − Hz C(bypass) − Bypass Capacitance − µF
Figure 10 Figure 11 Figure 12

TPS79133 TPS79133 TPS792133

OUTPUT IMPEDANCE DROPOUT VOLTAGE DROPOUT VOLTAGE
vs vs vs
FREQUENCY JUNCTION TEMPERATURE OUTPUT CURRENT
3 80 100
VI = 4.3 V VI = 3.2 V
VI = 3.2 V,
Co = 10 µF 70 90
2.5 Co = 10 µF CO = 10 µF
Z o − Output Impedance − Ω

V DO − Dropout Voltage − mV

TJ = 25°C

V DO − Dropout Voltage − mV
80
60
2 70 TJ = 125°C
50 IO = 100 mA
IO = 1 mA 60
1.5 40 50 TJ = 25°C

30 40
1
30
IO = 100 mA 20
0.5 IO = 10 mA 20
10 TJ = −40°C
10
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 0
10 100 1k 10 k 100 k 1M 10 M 0 0.02 0.04 0.06 0.08 0.1
f − Frequency − Hz TJ − Junction Temperature − °C
IO − Output Current − A
Figure 13 Figure 14 Figure 15

TPS79101 TPS79118
DROPOUT VOLTAGE MINIMUM REQUIRED INPUT VOLTAGE RIPPLE REJECTION
vs vs vs
INPUT VOLTAGE OUTPUT VOLTAGE FREQUENCY
120 5.2 90
VI = 3.2 V IO = 1 mA
IO = 100 mA 80
Minimum Required Input Voltage − V

Co = 10 µF
100 4.7
V DO − Dropout Voltage − mV

70
Ripple Rejection − dB

TJ = 125°C
80 4.2 60
TJ = 125°C
50 IO = 100 mA
60 3.7
TJ = 25°C TJ = −40°C 40

40 3.2 30
TJ = 25°C
TJ = −40°C
20 VI = 2.8 V
20 2.7 Co = 10 µF
10 C(byp) = 0.01 µF

0 2.2 0
2.5 3 3.5 4 4.5 5 1.5 2 2.5 3 3.5 4 4.5 5 100 1k 10 k 100 k 1M 10 M
VI − Input Voltage − V VO − Output Voltage − V f − Frequency − Hz

Figure 16 Figure 17 Figure 18

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TYPICAL CHARACTERISTICS
TPS79118 TPS79118 TPS79133
RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
90 90 100
VI = 4.3 V
80 IO = 10 mA 80 90 Co = 10 µF
IO = 10 mA C(byp) = 0.01 µF
70 70 80 IO = 100 mA

Ripple Rejection − dB
Ripple Rejection − dB

Ripple Rejection − dB
60 60
70
50 50
60
40 40
IO = 100 mA 50 IO = 10 mA
30 30 IO = 100 mA
40
20 20
VI = 2.8 V VI = 2.8 V
Co = 1 µF Co = 1 µF 30
10 10
C(byp) = 0.01 µF C(byp) = 0.1 µF
0 0 20
100 1k 10 k 100 k 1M 10 M 100 1k 10 k 100 k 1M 10 M 10 100 1k 10 k 100 k 1M 10 M
f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz
Figure 19 Figure 20 Figure 21

TPS79133 TPS79133 TPS79133

RIPPLE REJECTION RIPPLE REJECTION OUTPUT VOLTAGE, ENABLE VOLTAGE
vs vs vs
FREQUENCY FREQUENCY TIME (START-UP)
100 100 3

Enable Voltage − V
VI = 4.3 V VI = 4.3 V VI = 4.3 V
90 CO = 1 µF 90 Co = 1 µF 2 VO = 3.3 V
C(byp) = 0.01 µF C(byp) = 0.1 µF IO = 100 mA
80
Ripple Rejection − dB

80 1 Co = 1 µF
Ripple Rejection − dB

IO = 100 mA IO = 100 mA
TJ = 25°C
70 70 0

60 C(byp) = 0.001 µF
60
V O − Output Voltage − V

IO = 10 mA 50 IO = 10 mA 3
50

40 2 C(byp) = 0.0047 µF
40

30 30 1 C(byp) = 0.01 µF

20 20 0
10 100 1k 10 k 100 k 1M 10 M 10 100 1k 10 k 100 k 1M 10 M 0 20 40 60 80 100 120 140 160 180 200
f − Frequency − Hz t − Time − µs
f − Frequency − Hz

Figure 22 Figure 23 Figure 24

TPS79118 TPS79118 TPS79133

− Output Voltage − mV

V O − Output Voltage − mV

LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

Output Voltage − mV
∆ VO − Change In

IO = 100 mA VI = 2.8 V
Co = 1 µF 20 Co = 10 µF 20
C(byp) = 0.01 µF
10 0 0

0 −20 −20
O
− Input Voltage − V V

−10 −40
Current Load − mA

V I − Input Voltage − V

5.3

3.8 100 4.3

IO = 100 mA
0 Co = 1 µF dv 0.4 V
+
C(byp) = 0.01 µF dt µs
2.8
I
V

0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1 k 12 k 14 k 16 k 18 k 2 k 0 5 10 15 20 25 30 35 40 45 50

t − Time − µs t − Time − µs t − Time − µs
Figure 25 Figure 26 Figure 27

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TYPICAL CHARACTERISTICS
TPS79118
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
TPS79133 vs
LOAD TRANSIENT RESPONSE OUTPUT CURRENT
∆ V − Change In
I O − Output Current − mA Output Voltage − mV

100

Ω
VI = 4.3 V Co = 0.47 µF
20 Co = 10 µF VI = 5.5 V

ESR − Equivalent Series Resistance −

TJ = −40 °C to 125°C
0 10
O

Region of Instability
−20

−40 1

100

0.1

0 Region of
Instability
0.01
0 50 100 150 200 250 300 350 400 450 500 0 0.02 0.04 0.06 0.08 0.1
t − Time − µs IO − Output Current − A
Figure 28
Figure 29

TPS79118
TPS79118
TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR) EQUIVALENT SERIES RESISTANCE (ESR)
vs vs
OUTPUT CURRENT OUTPUT CURRENT
100
100
Ω
Co = 10 µF
Ω

Co = 1 µF
VI = 5.5 V
ESR − Equivalent Series Resistance −

VI = 5.5 V
ESR − Equivalent Series Resistance −

TJ = −40 °C to 125°C
TJ = −40 °C to 125°C 10
10
Region of Instability Region of Instability

1
1

0.1
0.1 Region of Stability
Region of Stability

0.01
0.01
0 0.02 0.04 0.06 0.08 0.1
0 0.02 0.04 0.06 0.08 0.1
IO − Output Current − A
IO − Output Current − A
Figure 30 Figure 31

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APPLICATION INFORMATION

The TPS791xx family of low-dropout (LDO) regulators have been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170 µA typically), and enable-input to reduce supply currents to less than 1 µA
when the regulator is turned off.

A typical application circuit is shown in Figure 32.

TPS791xx

1
VI IN 4
BYPASS

5
OUT VO
0.1 µF 3 0.01 µF
EN
+
1 µF
GND
2

Figure 32. Typical Application Circuit

EXTERNAL CAPACITOR REQUIREMENTS
A 0.1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS791xx, is required for stability and to improve transient response, noise rejection, and ripple rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.

Like all low dropout regulators, the TPS791xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 1 µF. Any 1 µF or larger ceramic
capacitor is suitable. The device is also stable with a 0.47 µF ceramic capacitor with at least 75 mΩ of ESR.

The internal voltage reference is a key source of noise in an LDO regulator. The TPS791xx has a BYPASS pin
which is connected to the voltage reference through a 250-kΩ internal resistor. The 250-kΩ internal resistor,
in conjunction with an external bypass capacitor connected to the BYPASS pin, creates a low pass filter to
reduce the voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator
to operate properly, the current flow out of the BYPASS pin must be at a minimum because any leakage current
creates an IR drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor
must have minimal leakage current.

For example, the TPS79118 exhibits approximately 15 µVRMS of output voltage noise using a 0.1 µF ceramic
bypass capacitor and a 1 µF ceramic output capacitor. Note that the output starts up slower as the bypass
capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250 kΩ
resistor and external capacitor.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at
the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly
to the ground pin of the device.
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POWER DISSIPATION AND JUNCTION TEMPERATURE

Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
T max * T
P + J A (1)
D(max) R
qJA
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, see the dissipation rating table.

TA is the ambient temperature.

The regulator dissipation is calculated using:

P
D
ǒ
+ V *V
I O
Ǔ I
O
(2)

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.

PROGRAMMING THE TPS79101 ADJUSTABLE LDO REGULATOR

The output voltage of the TPS79101 adjustable regulator is programmed using an external resistor divider as
shown in Figure 33. The output voltage is calculated using:

V
O
+V
ref
ǒ1 ) R1
R2
Ǔ (3)

Where:
Vref = 1.2246 V typ (the internal reference voltage)

Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should
be avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VO. The recommended
design procedure is to choose R2 = 30.1 kΩ to set the divider current at 50 µA, C1 = 15 pF for stability, and
then calculate R1 using:

R1 + ǒ V
V
O *1
ref
Ǔ R2 (4)

In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor
be placed between OUT and FB. For voltages <1.8 V, the value of this capacitor should be 100 pF. For voltages
>1.8 V, the approximate value of this capacitor can be calculated as:
(3 10*7) (R1 ) R2)
C1 + (5)
(R1 R2)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8 V is chosen, then the minimum
recommended output capacitor is 2.2 µF instead of 1 µF.
11

 
  

  
  
www.ti.com
SGLS160B − APRIL 2003 − REVISED SEPTEMBER 2008

TPS79101
OUTPUT VOLTAGE
VI PROGRAMMING GUIDE
IN
1 µF
OUTPUT
R1 R2 C1
VOLTAGE
EN OUT VO
≥2V C1 2.5 V 31.6 kΩ 30.1 kΩ 22 pF
R1
1 µF 3.3 V 51 kΩ 30.1 kΩ 15 pF
≤ 0.7 V
BYPASS FB 3.6 V 59 kΩ 30.1 kΩ 15 pF
0.01 µF GND
R2

Figure 33. TPS79101 Adjustable LDO Regulator Programming

REGULATOR PROTECTION
The TPS791xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might
be appropriate.
The TPS791xx features internal current limiting and thermal protection. During normal operation, the TPS791xx
limits output current to approximately 400 mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum
voltage ratings of the device. If the temperature of the device exceeds approximately 165°C, thermal-protection
circuitry shuts it down. Once the device has cooled down to below approximately 140°C, regulator operation
resumes.

12
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS79101DBVRQ1 ACTIVE SOT-23 DBV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PEU1 Samples

TPS79118DBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PER1 Samples

TPS79133DBVRG4Q1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 PES1 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Apr-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS791-Q1 :

• Catalog : TPS791

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS79101DBVRQ1 SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS79118DBVRQ1 SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS79133DBVRG4Q1 SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS79101DBVRQ1 SOT-23 DBV 6 3000 182.0 182.0 20.0
TPS79118DBVRQ1 SOT-23 DBV 5 3000 182.0 182.0 20.0
TPS79133DBVRG4Q1 SOT-23 DBV 5 3000 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

2X 0.95
3.05
2.75
1.9 5
2

4
3
0.50
6X
0.25
0.15
0.2 C A B 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
6X (1.1)
1

6X (0.6)
6

SYMM
2 5
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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