VIDYA VIKAS INSTITUTE OF ENGINEERING &

TECHNOLOGY
#127 - 128, Mysuru Bannur Road, Alanahally Post
MYSURU – 570028

Department of Electronics & Communication Engineering

ANALOG AND DIGITAL SYSTEMS DESIGN

LABORATORY MANUAL [BECL305]
 VISION

“To emerge as a premier center empowering students with creativity and technical
competency that caters to the ever-changing needs of industry and society”.

MISSION

M1: Provide collaborative learning environment that promotes creative thinking and
team work.
M2: Impart sound theoretical knowledge and skill sets required to be industry ready.
M3: Acquaint students with technological developments through Industry-Institute
interaction.

PROGRAMME EDUCATIONAL OBJECTIVES

PEO 1: Create innovative solutions through critical thinking.

PEO 2: Solve real-life problems by employing the knowledge and skills of Electronics
and Communication Engineering.
PEO 3: Exhibit leadership qualities in developing and applying technology for societal
needs and a sustainable world.

PROGRAMME SPECIFIC OUTCOMES

PSO 1: Employ the concepts of Electronics and Communication Engineering to

develop innovative solutions using modern tools and techniques.
PSO 2: Develop critical thinking, scientific inquiry in the field of Electronics and
Communication Engineering to analyze, design and create solutions for real
world problems.
Analog & Digital Systems Design Laboratory Lab- BECL305 VVIET, MYSURU

SYLLABUS

Subject Code BECL305 CIE Marks 50

Teaching Hours/ Week 0:0:2 Exam Hours 03
Credits 01 Exam Marks 50
Examination Type Practical

LABORATORY EXPERIMENTS

All Experiments have to be conducted using discrete components:

1. Design and set up the BJT common emitter voltage amplifier with and without feedback
and determine the gain- bandwidth product, input and output impedances.
2. Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator
3. Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator
and iv) Comparator
4. Design 4-bit R – 2R Op-Amp Digital to Analog Converter (i) for a 4-bit binary input
using toggle switches (ii) by generating digital inputs using mod-16
5. Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates,
(b) Half subtractor & Full subtractor using NAND gates, (c) 4-variable function using
IC74151(8:1MUX).
6. Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-
3 code conversion and vice versa
7. a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and
iii) T Flip-Flop
b) Realize the shift registers using IC7474/7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO
(v) Ring counter and (vi) Johnson counter.
8. Realize a) Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop
b) Mod-N Counter using IC7490 / 7476 c) Synchronous counter using IC74192
DEMONSTRATION EXPERIMENTS
9. Design and Test the second order Active Filters and plot the frequency response,
i) Low pass and Highpass Filter
ii) Bandpass and Bandstop Filter
10. Design and test the following using 555 timer

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Analog & Digital Systems Design Laboratory Lab- BECL305 VVIET, MYSURU

i)Monostable Multivibraator
ii)Astable Multivibrator
11. Design and Test a Regulated Power supply
12. Design and test an audio amplifier by connecting a microphone input and observe the
output using a loudspeaker.

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COURSE OBJECTIVES AND OUTCOMES

Course Objectives
This laboratory course enables students to:
1. Understand the electronic circuit schematic and its working
2. Realize and test amplifier and oscillator circuits for the given specifications
3. Realize the Opamp circuits for the applications such as DAC, and implement
mathematical functions
4. Design and test the combinational and sequential logic circuits for their functionalities
5. Use the suitable ICs based on the specifications and functions
6. Study the working of 555 timer circuits

Course Outcomes
At the end of this course, the student will be able to:
C205.1: Design and analyze the BJT/FET amplifier and oscillator circuits.
C205.2: Design and test Opamp circuits to realize the mathematical computations and DAC.
C205.3: Design and test the combinational logic circuits for the given specifications.
C205.4: Test the sequential logic circuits for the given functionality.
C205.5: Demonstrate the basic electronic circuit experiments using 555 timer.

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CONTENTS
Sl. Page
Name of the Experiment
No. No.
i Cycle of Experiments 5
ii Do‟s and Don‟ts 6
I Introduction to Analog and Digital Electronics Laboratory 7
III PART – A (Using Python)
Design and set up the BJT common emitter voltage amplifier with and without
1 feedback and determine the gain- bandwidth product, input and output 15
impedances.
2 Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator 19
Design and set up the circuits using opamp: i) Adder, ii)Integrator, iii)
3 23
Differentiator and iv) Comparator
Design 4-bit R – 2R Op-Amp Digital to Analog Converter i) for a 4-bit binary
4
input using toggle switches ii)by generating digital inputs using mod-16
29
Design and implement i) Half Adder & Full Adder using basic gates and
5 NAND gates ,ii)Half subtractor & Full subtractor using NAND gates, iii) 34
4-variable function using IC74151(8:1MUX).
Realize (i) Binary to Gray code conversion & vice-versa(IC74139), (ii)
6 40
BCD to Excess-3 code conversion and vice versa
a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and
7 iii) T Flip-Flop b) Realize the shift registers using IC7474/7495:(i) SISO (ii) 45
SIPO (iii) PISO (iv) PIPO (v) Ring counter and (vi)Johnson counter.
Realize a) Design Mod – N Synchronous Up Counter & Down Counterusing
8 7476 JK Flip-flop b) Mod-N Counter using IC7490 / 7476 c)Synchronous 55
counter using IC74192
IV PART B [using DSP Kit]
Design and Test the second order Active Filters and plot the frequency response,
9
i) Low pass and Highpass Filter ii) Bandpass and Bandstop Filter
59
Design and test the following using 555 timer i)Monostable Multivibraator
10
ii)Astable Multivibrator
65
11 Design and Test a Regulated Power supply 70
V Viva Questions 73

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CYCLE OF EXPERIMENTS
CYCLE – I
1. Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator and iv)
Comparator
2. Design and implement i) Half Adder & Full Adder using basic gates and NAND gates, ii) Half
subtractor & Full subtractor using NAND gates, iii) 4-variable function using
IC74151(8:1MUX).
3. Design 4-bit R – 2R Op-Amp Digital to Analog Converter i) for a 4-bit binary input using
toggle switches ii) by generating digital inputs using mod-16
4. Realize i)Binary to Gray code conversion & vice-versa (IC74139), ii) BCD to Excess-3 code
conversion and vice versa
CYCLE – II
5. Design and set up the BJT common emitter voltage amplifier with and without feedback and
determine the gain- bandwidth product, input and output impedances.
6. Realize using NAND Gates: (i)Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii) T Flip-Flop
Realize the shift registers using IC7474/7495: (i)SISO (ii) SIPO (iii) PISO (iv) PIPO (v) Ring
counter and (vi) Johnson counter.
7. Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator and iii) RC Phase shift
oscillator
8. Realize i) Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop ii)
Mod-N Counter using IC7490 / 7476 iii)Synchronous counter using IC74192

CYCLE – III (DEMONSTRATION EXPERIMENTS)

9. Design and test Monostable and Astable Multivibrator using 555 Timer
10. Design and Test the second order Active Filters and plot the frequency response,
i) Low pass Filter
ii) High pass Filter
11. Design and Test a Regulated Power supply
12. Design and test an audio amplifier by connecting a microphone input and observe the
output using loud speaker

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DO’s and DON’Ts

Do’s
 Students should be in proper uniform and dress code with identity cards in the laboratory.
 Students should bring their observation, manual and record compulsorily.
 Students should maintain discipline in the laboratory.
 Students are required to handle all the equipment‟s/Computers properly.
 Students are required to follow the safety precautions.
 Enter the lab in time as per the given time table.
 Enter time-in and time-out in log book.
 Comply with the instructions given by faculty and instructor.
 Arrange the chairs/ equipment‟s before leaving the lab.
 Take signature in the observation, before leaving the lab.

Don’ts
 Mobile phones are strictly banned.
 Ragging is punishable.
 Do not operate any peripherals or accessories without supervision.
 Avoid stepping on computer cables and electrical wires.
 Do not walk around in the lab unnecessarily.
 Do not go out of the lab without permission.

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Chapter 1
INTRODUCTION TO ANALOG & DIGITAL ELECTRONICS LABORATORY
Analog Electronics as the name suggests deals mainly with Analog signals.
Analog electronic circuit design is one of the important and challenging fields in
Electronics. The area of analog electronics is one of the vast and complex areas in VLSI
circuits design. A signal which is having different values at different instants of time is
referred to as an analog signal. Analog electronic circuits can be designed and tested for
their performance using the tools like PSPICE, Cadence, etc.. Many analog circuits are
available in the form of IC chips.

During this Lab course simple analog electronic circuits are designed using
discrete components like Resistors, Capacitors, Inductors, PN junction diodes and
Transistors (BJT‟s, FET‟s, etc.), etc.. These designed circuits are tested and verified for
their performance under the laboratory conditions using power sources like DC Power
supply, AC sources like function generators. Their input and output parameters like input
waveforms, output waveforms, input and output current and voltage readings, the
impedance or resistance offered by the circuit, etc. are analyzed by using measuring
instruments like multimeter and CRO‟s. The captured values from the instruments are
noted and used for further calculations.
1.1. Analog Electronic Components
Transistor

1: Pin Diagram and Symbol of Transistor

2 Diode representation of transistor

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1. A transistor is a miniature semiconductor that regulates or controls current or

voltage flow in addition to amplifying and generating these electrical signals and
acting as a switch/gate for them.
2. Typically, transistors consist of three layers, or terminals, of semiconductor
material, each of which can carry a current.
3. A transistor is made up of three terminals which are called the emitter, base, and
collector.
4. An electrical signal is applied to the base, and the current flow between the
emitter and collector.
5. A transistor basically acts as a switch and an amplifier.
6. The standard units of a transistor for electrical measurement are Ampere (A),
Volt (V), and Ohm (Ω), respectively.
7. The word transistor is a combination of transfer and resistance.
8. This is because it transfers the resistance from one end of the device to the other
end or we can say, transfer of resistance.
9. Hence, the name transistor. Transistors have very high input resistance and very
low output resistance.
Types of transistors:

3Types of transistors

Transistors are broadly divided into these types:

Bipolar transistors (bipolar junction transistors: BJTs). They are further classified into two
categories
1. An NPN transistor has a piece of P-type silicon (the base) sandwiched between two
pieces of N-type (the collector and emitter).
2. In a PNP transistor, the type of the layers is reversed.
Field-effect transistors (FETs) are further classified into two categories:

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1. Insulated-gate bipolar transistors (IGBTs).

2. Metal-oxide-semiconductor field-effect transistor(MOSFET)
Thus, a transistor is a miniature semiconductor that regulates or controls current or voltage
flow.
Opamp µA741

The µA741 is a monolithic op-amp with high-performance, and it is designed on an only Si

(Silicon) chip. This IC is used in a broad variety of analog applications. The operating
voltage of broad range as well as high-gain provides better performances within the
applications like integrators, general feedback, and summing amplifier applications.

4: OPAMP Pin Diagram

The UA741 IC consists of 8-pins, and the function of each pin as follows:
Pin1 & Pin5 (Offset N1 & N2): These pins are used to set offset voltage if necessary
Pin2 (IN-): Inverting pin of the operational amplifier
Pin3 (IN+): Non-inverting pin of the Op-Amp
Pin4 (Vcc-): This pin is connected to ground otherwise negative rail
Pin6 (Output): Operational amplifier‟s o/p pin
Pin7 (Vcc+): This pin is connected to a +ve rail of the voltage supply
Pin8 (NC): No connection

Quartz Crystal Oscillators

Quartz crystal oscillators overcome some of the factors that affect the frequency
stability of an oscillator. These generally include: variations in temperature, variations

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in the load, as well as changes to its DC power supply voltage to name a few.
Frequency stability of the output signal can be greatly improved by the proper selection
of the components used for the resonant feedback circuit, including the amplifier. But
there is a limit to the stability that can be obtained from normal LC and RC tank
circuits.

5:Quartz Crystal Osccilator

To obtain a very high level of oscillator stability a Quartz Crystal is generally used as
the frequency determining device to produce another types of oscillator circuit known
generally as a Quartz Crystal Oscillator, (XO).

6:Quartz Crystal Equivalent Model

The equivalent electrical circuit for the quartz crystal shown in figure 6 consists of a
series RLC circuit, which represents the mechanical vibrations of the crystal, in
parallel with a capacitance, Cp which represents the electrical connections to the
crystal. Quartz crystal oscillators tend to operate towards their “series resonance”. The
equivalent impedance of the crystal has a series resonance where Cs resonates with

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inductance, Ls at the crystals operating frequency. This frequency is called the crystals
series frequency, ƒs. As well as this series frequency, there is a second frequency point
established as a result of the parallel resonance created when Ls and Cs resonates with
the parallel capacitor Cp as shown.

1.2: Digital Electronic Components

The basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC
gates are classified not only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit upon which more
complex digital circuits and functions are developed.
AND, OR and NOT are called as basic gates. AND, OR logic gates can have „n‟ inputs (n≥ 2)
and gives single output. NOT gate also called as “inverter”, has single input and produces single
output.
AND gate: It is a basic logic gate that produces high state output only when all the inputs are
logic high or at logic „1‟ state. It performs logical multiplication.
OR gate: It is a basic logic gate that produces high state output if any one of the inputs is logic
high. It performs logical addition.
NOT gate: It is a basic logic gate that produces an inverted output for a given input. There are
two universal gates: NAND and NOR gates.
NAND gate: It is an universal logic gate that produces high state output if any one of the
inputs is at logic „1‟ state. It is the complement of AND gate.
NOR gate: It is a universal logic gate that produces high output only when all the inputs are logic
high. It is the complement of OR gate.
There are two other types of digital logic gates which although are not the basic gates in their
own , however, as they are constructed by combining together with other logic gates, their output
Boolean function is important enough to be considered as complete logic gates. These two
“hybrid” logic gates are called the Exclusive-OR (Ex-OR) Gate and its complement the
Exclusive-NOR (Ex-NOR) Gate.
Ex-OR gate: It is a logic gate that that produces high state output if it has odd number of ones.

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Ex-NOR gate: It is a logic gate that that produces high state output if it has even number of ones.
It is the complement of Ex-OR gate
Realization of basic gates using NOR and NAND gates
NOT GATE NOT GATE

OR GATE
AND GATE

AND GATE
OR GATE

NOR GATE
NAND GATE

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LOGIC GATES
2 INPUT QUADRAUPLE AND GATE
Symbol Truth Table PIN Diagram

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

2 INPUT QUADRUPLE OR GATE

Symbol Truth Table PIN Diagram

A B F
0 0 0
0 1 1
1 0 1
1 1 1

2 INPUT QUADRUPLE NOR

GATE
Symbol Truth Table PIN
Diagram

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A B F
0 0 1
0 1 0
1 0 0
1 1 0

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Chapter 2
EXPERIMENT 1

Aim: Design and set up the BJT common emitter amplifier using voltage divider bias with and
without feedback and determine the gain- bandwidth product from its frequency response.

Components and equipment’s required: Transistor – SL100, Resistors - 470 Ω, 1KΩ, 10KΩ -
2nos, and 33KΩ, Capacitors 100µf, 0.22µf and 0.47µf, Power Supply, 10Hz – 3MHz Signal
generator, CRO, Connecting wires and Bread board/Spring board with spring terminals.

Design:
Transistor: SL100
Given, VCE = 6 V and IC = 4.5mA Assume  = 100(For SL100)
VCC = 2VCE = 2 X 6 = 12 V
Let VRE = 10% VCC = 1.2 VRE = VRE / ( IC + IB )
IB = IC /  = 4.5 mA / 100 = 45 ARE = 1.2 / ( 4.5 m + 45 ) = 264 
Choose RE = 270 
Apply KVL to collector loop: VCC – IC RC – VCE – VE = 0
RC = ( VCC – VCE – VE ) / IC = ( 12 – 6 – 1.2 ) / 4.5 m
RC = 1.06 k Choose RC = 1k
Let IR1 = 10 IB = 10 X 45 A = 450 A
VR2 = VBE + VE = 0.6 + 1.2 = 1.8 V(Since transistor is silicon make VBE = 0.6 V )
R2 = VR2 / (IR1 – IB) = 1.8 / (450 A - 45 A)
R2 = 4.4 k Choose R2 = 4.7 k
R1 = ( VCC – VR2 ) / IR1 = ( 12 – 1.8 ) / 450 A
R1 = 22.6 K Choose R1 = 27 k
XCE << RE
XCE = RE / 10
1 / ( 2  f CE ) = 270 / 10 Let f = 100 Hz
CE = 59 F Choose CE = 47 F, Choose CC1 = CC2 = 0.47 F

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Circuit Diagram of amplifier without feedback:

CE amplifier without feedback

Circuit Diagram of amplifier with feedback:
(Introduce a resistor in the emitter circuit)

CE amplifier with feedback

Procedure:
Follow the same procedure for both circuits

1. After making the connections, switch on the D.C. power supply and check the D.C.
conditions without any input signal and record in table below:

2. Select sine wave input and set the input signal frequency ≥10f1 (Say = 10 KHz. This will
be a convenient „Mid – frequency‟).

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3. Observe the input wave form and output wave form on a dual channel CRO.

4. Adjust the input amplitude such that the output waveform is just undistorted (or in the
verge of becoming distorted). Measure the amplitude of the Input Signal now. This
amplitude is the Maximum Signal Handling Capacity of your amplifier.
5. Decrease the input voltage to a convenient value such that the output is undistorted. Say
20mV. Measure the corresponding o/p voltage. Calculate mid-band gain, AM = Vo (p-p) /
Vin(p-p).
6. Keeping the input voltage constant, go on reducing the frequency until the output voltage
reduces to 0.707 times its value at 10 KHz. The frequency at which this happens gives you
theLower Cut-off frequency (f1).
7. Keeping the input voltage constant, go on increasing the frequency until the output voltage
decreases to 0.707 times its value at 10 KHz. The frequency at which this happens gives
you the Upper Cut-off frequency (f2).
8. Thus you have pre-determined f1 and f2. Find the amplifier band width, BW = f2 – f1

9. Determine Gain Bandwidth product (GBW product) which is a Figure of Merit of your
amplifier as GBW = AM x BW.
10. Now repeat the experiment by recording values of output voltage versus frequency keeping
the input voltage at a constant value convenient to you. You should take at least 5 readings
below f1 and 5 readings above f1, at least 5 readings in the mid band, at least 5 readings
below f2 and 5 readings above f2.
11. Plot graphs of AV versus Frequency, f and /or M, dB versus Frequency, f on a semi log
graph paper. From the graph determine: Mid –band - gain, Lower and Upper Cut-off
frequencies and Band width. Compute the GBW product and verify with answer obtained
earlier.

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Observation:
Use the tabular column separately for each circuitVin (P-P) = mV
AV= VO (P-P)/Vin (P-P)
M = 20log (AV), dB
Frequency
In Hz 100 200 300 350 400 500 600 700 800 1K 2K 3K 5K 8K
VO(P-P)
In Volts

AV

M, dB,
(AV in dB)

Frequency
10K 20K 30K 50K 100K 200K 300K 400K 500K 600K 700K 800K 900K 1M
In Hz

VO(P-P)
in Volts

AV

M, dB,
(AV in dB)

Expected graph

Frequency Response of CE amplifier

Result:

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Analog & Digital Systems Design Laboratory Lab- BECL305 VVIET, MYSURU

EXPERIMENT 2
Aim: Design and set-up the following tuned oscillator circuits using BJT/FET
(i) Colpitts Oscillator (ii) Crystal Oscillator

2a. Design and set-up BJT/FET Colpitts Oscillator

Components and equipment’s required: Transistor SL 100, Resistors 470Ω, 1KΩ 10KΩ and
33 KΩ; Capacitors 0.1µf - 3nos, Discrete inductances 100 µH – 2 nos, Capacitor 470 pF – 2nos,
Power supply, CRO, Connecting wires etc.

Circuit Diagram:

Colpitt’s Oscillator circuit

Theory:
An oscillator is a circuit which produces an output signal of any desired frequency without any
input signal. A Colpitt‟s oscillator, named after its inventor Edwin H. Colpitt‟s, is one of a
number of designs for electronic oscillator circuits. One of the key features of this type of
oscillator is its simplicity and robustness. It is not difficult to achieve satisfactory results with
little effort. A Colpitt‟s oscillator is the electrical dual of a Hartley oscillator. In the Colpitt‟s
circuit, two capacitors and one inductor determine the frequency of oscillation. The feedback
needed for oscillation is taken from a voltage divider made by the two capacitors, where in the
Hartley circuit the feedback is taken from a voltage divider made by two inductors (or a tapped
single inductor). (Note: the capacitor can be a variable device by using a varactor).Colpitt‟s
oscillator is a radio frequency LC (inductor-capacitor) sinusoidal oscillator used to generate high

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frequency (radio frequency) signals. This circuit used two capacitors and one inductor in the
feedback circuit.
Design:
BJT- Amplifier design is same as given in Common Emitter Amplifier.
Tank Circuit Design: where
√

Given Oscillation frequency : f =100 KHz

Assume C1=C2 = 0.01 pF then Ceq=______________F, then ( )
= μH

Use L = µH, For this value of L, f =

Procedure:
1. Switch on the Power Supply and check the D.C conditions by removing the
coupling capacitor CC1 or CC2.
2. Connect the coupling capacitors and obtain an output waveform on the CRO. If the
o/p is distorted adjust 1- KΩ Potentiometer (R3) to get perfect SINE wave.
3. Measure the period of oscillation and calculate the frequency of oscillation.
4. Compare the measured frequency with re-computed theoretical value for the
component values connected.

Observation:
Parameter VRC VCE VE ICQ = VRC / RC VBE VB

Assumed

Practical

Result: The frequency of oscillation is …..

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2b. Design and set-up BJT/FET Crystal Oscillator

Components and equipment’s required: Transistor SL 100, Crystal – 2MHz, Resistors 470Ω,
1KΩ 10KΩ and 33 KΩ; Capacitors 0.1µf - 2nos, Power supply, CRO, Connecting wires etc.

Theory:

Crystal oscillators are used in order to get stable sinusoidal signals despite of variations in
temperature, humidity, transistor and circuit parameters. A piezo electric crystal is used in this
oscillator as resonant tank circuit. Crystal works under the principal of piezo-electric effect. i.e.,
when an AC signal applied across the crystal, it vibrates at the frequency of the applied voltage.
Conversely if the crystal is forced to vibrate it will generate an AC signal. Commonly used
crystals are Quartz, Rochelle salt etc.

0.01µ

Crystal Oscillator circuit

Design:

Let VCC = 12V;

ICQ = 4mA;
VE = (1/10) VCC to (1/5) VCC;
VCE=________________= 6V;
hFE = 100.

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To find RE: Let us choose VE = 2 V

RE = VE / IE; VE / IC =2 V/ 4 mA =500 ; let RE =470Ω
VCC = ICRC + VCEQ + VEQ
RC = (VCC – VCEQ– VEQ) / ICQ = 4.0 V/ 4mA =1.0K; RC= 1K

Assume: R2=10kΩ.
VB = VE + VBE = 2 + 0.6 = 2.6V
I2 = Current through R2= VB /R2 = 0.26mA or 260µA
The base current IB = IC / hFE= 4mA / 100= 0.04mA= 40µA
(hFE = βDC = 100, a working value; It varies from 50 to 280 for SL 100)
I1 = Current through R1 = IB+I2 = 300 µA
VR1=VCC– VB=12 – 2.6 =9.4V
R1 =VR1/ I1= 9.4V/300 µA =9400/300 KΩ =31.33KΩ; R1 = 33K
CE = CC =0.1µF (Arbitrary, any value which gives a reactance < 10 Ω at Crystal frequency may
be used. reactance of a Capacitor XC = (1/2πfC); For C = 0.1 µF, XC = 0.8Ω at 2 MHz)
Procedure:
1. Switch on the Power Supply and before inserting the crystal check the D.C conditions by
removing the coupling capacitor CC1 or CC2.
2. Insert the crystal and the coupling capacitors and obtain the output waveform on the CRO. If
the o/p is distorted vary 1- KΩ Potentiometer (R3)to get perfect SINE wave.
3. Measure the period of oscillation and calculate the frequency of oscillation.
4. Compare with frequency marked on the crystal.

Observation:

Parameter VRC VCE VE ICQ = VRC / RC VBE VB

Assumed

Practical

Result:

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EXPERIMENT 3
Aim: Design and set up the circuits using opamp: i) Adder, ii) Integrator, iii) Differentiator
and iv) Comparator

Components Required:

 Resistors - As per design

 Op-amp - µA741
 DC Power supply - ±12V
 Breadboard
Theory:
The Adder (Summing Amplifier) is another type of operational amplifier circuit configuration
that is used to combine the voltages present on two or more inputs into a single output voltage.

The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC
content so there is no current flow to the amplifier summing point, X resulting in zero output
voltage. The capacitor only allows AC type input voltage changes to pass through and whose
frequency is dependent on the rate of change of the input signal.

As its name implies, the Op-amp Integrator is an operational amplifier circuit that performs
the mathematical operation of Integration that is we can cause the output to respond to
changes in the input voltage over time as the op-amp integrator produces an output voltage
which is proportional to the integral of the input voltage.

a) Adder
Design:
Consider the current flowing through the input resistors are,

Then by Kirchhoff‟s current law, the current flowing through the feedback resistor
Rf isgiven by the sum of these 3 currents.

By Considering

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This current will flow through the feedback resistor Rf, because the point „K‟ acts as the virtual
ground point. So the voltage drop at Rf is given by

V0 = -IRf = - (1/R)[V1+V2+V3] R V0 = -[V1+V2+V3]

-ve sign is due to the op amp connected in inverting mode.

This circuit is called a summing amplifier because it can provide gain. By adjusting the value of
Rf the gain can be changed.

Circuit Diagram:

Adder using Op-Amp 741IC

Adder using Op-Amp 741IC

Procedure:
1. Here the input voltages V1, V2 are given in to the adder circuit at pin 2.
2. This is an inverting summing amplifier because output is the sum of input with a
signchange.
3. To construct a non-inverting adder, cascade one „Inverting Amplifier‟ with unity
gainalong with the Circuit.
4. Output of this adder circuit is given by – [V1 + V2 ] is checked at pin 6.

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b) Differentiator
Design:
Let fa = 50 Hz;
C1 = 0.1μF
fa = 1 / 2πRfC1; Rf = 31.8KΩ ; Rf = 10R1
R1 = 3.1 KΩ

Circuit Diagram:

Differentiator using Op-Amp 741IC

Procedure:
1. The connections are given as per the experimental setup.
2. The supply is switched ON after checking the circuit connections.
3. The input wave form is applied from the function generator and the corresponding output
waveform is noted from the CRO.

Output Waveform:

Result:

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c) Integrator
Design:
Let fb = 100 Hz;
Cf = 0.1μF
fb = 1 / 2πR1 Cf
R1 = 15.9KΩ
Rf = 10R1
Rf = 1.59 MΩ
Circuit Diagram:

Integrator using Op-Amp 741IC

Procedure:
1. The connections are given as per the experimental setup.
2. The supply is switched ON after checking the circuit connections.
3. The input wave form is applied from the function generator and the corresponding output
waveform is noted from the CRO.
Output Waveform:

Result:

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d) Comparator
A non-inverting 741 IC op-amp comparator circuit is shown in the figure below. It is called a
non-inverting comparator circuit as the sinusoidal input signal Vin is applied to the non-inverting
terminal. The fixed reference voltage Vref is give to the inverting terminal (-) of the op-amp.
When the value of the input voltage Vin is greater than the reference voltage Vref the output
voltage Vo goes to positive saturation. This is because the voltage at the non-inverting input is
greater than the voltage at the inverting input.

Circuit Diagram

Comparator circuit diagram

When the value of the input voltage Vin is lesser than the reference voltage Vref, the output
voltage Vo goes to negative saturation. This is because the voltage at the non-inverting input is
smaller than the voltage at the inverting input. Thus, output voltage Vo changes from positive
saturation point to negative saturation point whenever the difference between Vin and Vref
changes. This is shown in the waveform below. The comparator can be called a voltage level
detector, as for a fixed value of Vref, the voltage level of Vin can be detected.

The circuit diagram shows the diodes D1and D2. These two diodes are used to protect the op-
amp from damage due to increase in input voltage. Thes diodes are called clamp diodes as
they clamp the differential input voltages to either 0.7V or -0.7V. Most op-amps do not need
clamp diodes as most of them already have built in protection. Resistance R1 is connected in
series with input voltage Vin and R is connected between the inverting input and reference
voltage Vref. R1 limits the current through the clamp diodes and R reduces the offset problem.

Output Waveform

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EXPERIMENT 4
Aim: Design 4-bit R – 2R Op-Amp Digital to Analog Converter i) using 4-bit binary input from
toggle switches (ii) by generating digital inputs using mod-16

Components Required:

Theory:

Now a day‟s digital systems are used in many applications because of their increasingly
efficient, reliable and economical operation. Since digital systems such as microcomputers use
a binary system of ones and zeros, the data to be put into the microcomputer have to be
converted from analog form to digital form. The circuits that perform this conversion and
reverse conversion are called A/D and D/A converters respectively. D/A converter in its
simplest form uses an op-amp and resistors either in the binary weighted form or R-2R form.
The fig. below shows D/A converter with resistors connected in R-2R form. It is so called as
the resistors used here are R and 2R. The binary inputs are simulated by switches b0 to b3 and
the output is proportional to the binary inputs. Binary inputs are either in high (+5V) or low
(0V) state.The analysis can be carried out with the help of Thevenin‟s theorem. The output
voltage corresponding to all possiblecombinations of binary inputs can be calculated as below.
V 0 = - R F [ (b3 /2R) + (b2 /4R) + (b1 /8R) + (b0 /16R) ]
Where each inputs b3 , b2 , b1 and b0 may be high (+5V) or low (0V). The great advantage of
D/A converter of R-2R type is that it requires only two sets of precision resistance values. In
weighted resistor type more resistors are required and the circuit is complex. As the number of
binary inputs is increased beyond 4 even D/A converter circuits get complex and their accuracy
degenerates. Therefore in critical applications IC D/A converter is used. Some of the parameters
must be known with reference to converters. They are resolution, linearity error, settling time etc.
Resolution = 0.5V / 2 8 = 5 / 256 = 0.0195

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i ) using 4-bit binary input from toggle switches

Circuit Diagram:

R-2R DAC

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Procedure:
1. Test the op-amp and other components before rigging up the circuit.
2. Rig up the circuit as shown in the fig.
3. Apply different combination of binary inputs using switches.
4. Observe the output at pin no. 6 of op-amp using multimeter or CRO.
5. Tabulate the readings as shown.
6. Calculate the resolution of the converter.
Tabular Column:
( )

For B0=1, B1=0, B2=1 B3=0

( )

Observation
Digital Inputs Analog Equivalent Output(Volts)
B3 B2 B1 B0 Theoretical Practical
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Result: The theoretical and practical output voltages are verified

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ii) By generating digital inputs using mod-16

COMPONENTS REQUIRED:

Theory:

A 4-bit DAC using R-2R ladder network and an Op-amp is shown in Fig . The D/A converter
converts digital or binary data into its equivalent analog value The input digital data for a D/A
converter is an n-bit binary word. Here Qa, Qb, Qc and Qd3 are the digital inputs. In R-2R ladder
D/A converter, resistors of only two values are used. Hence it is suitable for integrated circuit
fabrication. Each digital input may be low (0) or high (1). VR (0) = 0 and VR (1) = VR =
5V.Reference voltage can be selected depending on maximum Analog o/p voltage required. If
the digital inputs are obtained from a Digital IC trainer, then VR = + 5 V = constant/ DC
reference voltage .
IC Pin Diagram

( )

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Circuit Diagram

Digital inputs using mod-16 counter

Procedure:

1. Connections are made as shown in the fig. 9.2.

2. The 4 bits are increased in steps from 0000 to 1111. And at each step output voltage is
measured using multimeter.
3. The 74193 IC provides digital inputs to DAC
4. The digital outputs are connected using digital trainer kit.
5. By applying clock pulses to74193 IC , output voltage is measured using multimeter.
6. The readings are tabulated and verified against theoretical output. And a graph is
plotted for input V/S output voltage.
Result:

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EXPERIMENT 5
Aim: Design and implement (a) Half Adder & Full Adder using basic gates and NAND gates,
(b) Half subtractor & Full subtractor using NAND gates, (c) 4-variable function using
IC74151(8:1MUX).

(a) Half Adder & Full Adder using basic gates and NAND gates

Components Required:

Sl no Component Specification Qty

1 NOT GATE IC 7404 1

2 AND GATE IC 7408 1
3 OR GATE IC 7436 1
5 NAND GATE IC 7400 2
7 Patch Cords -
8 IC Trainer Kit. -
Theory:

Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit, S,
and the other is the carry bit, C. The Boolean functions describing the half-adder are:

S =A ⊕ B, C = A B

Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
addstwo data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:

S = (A ⊕ B) ⊕ Cin C = AB + Cin (A ⊕ B)

Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A - B) produces
a difference bit D and a borrow out bit Br. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the half-
Subtractor are:

D =A ⊕ B Br =A B

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Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full-subtractor are:

D = (A ⊕ B) ⊕ Cin Br= A ‟ B + A‟ (Cin) + B (Cin)

a) Half Adder

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1 SUM = A‟B + AB‟ CARRY = AB

Realization using basic gate

Realization using NAND gate

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Full Adder
Truth Table K-Map for SUM: K-Map for CARRY
B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0 SUM = A‟B‟ Cin + A‟B Cin‟ + AB Cin‟ + AB Cin CARRY = AB + B Cin + ACin
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Realization using BASIC gates

Realization using NAND gates

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b) Half Subtractor
Truth Table K-Map for DIFFERENCE: K-Map for BORROW:
B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0 DIFFERENCE = A‟B + AB‟ BORROW = A‟B

Realization using NAND gates

d) Full Subtractor
Truth Table
B Cin DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-MAP FOR DIFFERENCE: K-MAP FOR BORROW:

Difference = A‟B‟Cin + A‟BCin‟ + AB‟Cin‟ + ABCin Borrow = A‟B + BCin + A‟Cin

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Realization using NAND gates

Procedure:
1. T he components should be checked for their working.
2. The appropriate IC should be inserted into the IC base.
3. T h e connections are made as shown in the circuit diagram.
4. Provide the input data is provided via the input switches and the output are observed on
output LEDs.
5. The truth table is verified.

Result: The truth table of the above circuits is verified.

d) 4-variable function using IC 74151(8:1MUX):
Components Required:

Sl no Component Specification Qty

1 Multiplexer IC IC 74153 1
2 Multiplexer IC IC 74151 1
3 Patch Cords -
4 IC Trainer Kit -
Theory:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control
of selection signals. Multiplexer means many to one. A multiplexer is a circuit with many
inputs but only one output. By usingcontrol signals (select lines) we can select any input to
the output. Multiplexer is also called as data selector because the output bit depends on the
input data bit that is selected. The general multiplexer circuit has 2ninput signals, n
control/select signals and 1 output signal

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Circuit Diagram of 8:1 Multiplexer

Truth Table

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the Truth Table and observe the outputs.

Result: Adder and subtractor circuits and Boolean Equations are realized using multiplexer
IC74151.

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EXPERIMENT 6
Aim: Realize (i) Binary to Gray code conversion & vice-versa (IC74139), (ii) BCD to Excess-3
code conversion and vice versa

i) BCD to Excess 3 Code Conversion and Vice Versa

Components Required:
Sl no Component Specification Qty
1 Parallel Adder IC 7483 1
2 XOR gate IC 7486 1
3 Patch Cords -
4 IC Trainer kit -

Theory:
Code converter is a combinational circuit that translates the input code word into a new
corresponding word. The excess-3 code digit is obtained by adding three to the corresponding
BCD digit. To Construct a BCD-to-excess-3-code converter with a 4-bit adder feed BCD code
to the 4-bit adder as the first operand and then feed constant 3 as the second operand. The
output is the corresponding excess-3 code. To make it work as a excess-3 to BCD converter,
we feed excess-3 code as the first operand and then feed 2's complement of 3 as the second
operand. The output is the BCD code.

IC 7483 Pin diagram

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Circuit Diagram

Truth Table
BCD EXCESS-3 EXCESS- 3 BCD

0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0

0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1

0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0

0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 1

0 1 0 0 0 1 1 1 0 1 1 1 0 1 0 0

0 1 0 1 1 0 0 0 1 0 0 0 0 1 0 1

0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

0 1 1 1 1 0 1 0 1 0 1 0 0 1 1 1

1 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0

1 0 0 1 1 1 0 0 1 1 0 0 1 0 0 1

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Procedure:

1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram
4. Apply BCD code as first operand(A) and binary 3 as second operand(B)and cin=0 for
Realizing BCD-to-Excess-3-code
5. Apply Excess-3-code code as first operand(A) and binary 3 as secondoperand(B) and
Cin=1 for realizing Excess-3-code to BCD.
6. Verify the Truth Table and observe the outputs.

Results: Verified the working of IC 7483 as parallel adder and subtractor

ii) Binary to gray code conversion and Vice versa USING IC74139

Aim: Realize Binary to gray code conversion and Vice versa USING IC74139 (2-4 Decoder).
Theory:
Binary to gray code conversion: Following are the steps for conversion.
1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2. Other bits of the output gray code can be obtained by XOR ing binary code bit at that
index and previous index.

Gray code to binary conversion: Following are the steps for conversions.
(1) The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the
given gray code.

(2) Other bits of the output binary code can be obtained by checking the gray code bit at that
index. If the current gray code bit is 0, then copy the previous binary code bit, else copy

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the invert of the previous binary code bit.

Truth Table:
Binary to Gray Code Converter

Circuit Diagram:

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Equations:
G0= m(1,2,5,6)
G1= m(2,3,4,5)
G2=B2
Gray to Binary Code Converter
Truth Table Circuit Diagram

Equations:
B2=G2
B1= m(2,3,4,5)
B0= m(1,2,4,7)
Procedure:
1. The components should be checked for their working.
2. The appropriate IC should be inserted into the IC base.
3. The connections are made as shown in the circuit diagram.
4. Provide the input data is provided via the input switches and the output are
observed on output LEDs
5. The truth table is verified.

Result: Realized Binary to gray code conversion and Vice versa using IC 74139
circuit.

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EXPERIMENT 7
Aim: a) Realize using NAND Gates: i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and
iii) T Flip-Flop
b) Realize the shift registers using IC7474/7495: (i) SISO (ii) SIPO (iii) PISO (iv) PIPO (v)
Ring counter and (vi) Johnson counter.
Components Required:

Theory:
Logic circuits that incorporate memory cells are called sequential logic circuits; their output
depends not only upon the present value of the input but also upon the previous values.
Sequential logic circuits often require a timing generator (a clock) for their operation.
Master-Slave JK Flip-Flop
 The Master-Slave Flip-Flop has two gated SR flip-flops connected with the slave having
an inverted clock pulse.
 The outputs from the "Slave" flip-flop are fed back to the inputs of the "Master" with the
outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-
flop. This feedback configuration gives the characteristic toggle of the JK flip-flop
 The input signals J and K are connected to the gated "master" SR flip-flop which "locks"
the input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock
input of the "slave" flip-flop is the inverse (complement) of the "master" clock input, the
"slave" SR flip-flop does not toggle. The outputs from the "master" flip-flop are only
"seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0".
When the clock is "LOW", the outputs from the "master" flip-flop are latched and any
additional changes to its inputs are ignored. The gated "slave" flip-flop now responds to
the state of its inputs passed over by the "master" section. Then on the "Low-to-High"
transition of the clock pulse the inputs of the "master" flip-flop are fed through to the
gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same inputs

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are reflected on the output of the "slave" making this type of flip-flop edge or pulse-
triggered.
 Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data
to the output on the falling-edge of the clock signal.
D Flip-flop:
 For a positive-edge triggered master–slave D flip-flop, when the clock signal is low
(logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is
high (logical 1). This allows the "master" latch to store the input value when the clock
signal transitions from low to high.
 As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1
to 0) and the value seen at the input to the master latch is "locked". Nearly
simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions
from low to high (0 to 1) with the clock signal. This allows the signal captured at the
rising edge of the clock by the now "locked" master latch to pass through the "slave"
latch.
 When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked",
and the value seen at the last rising edge of the clock is held while the "master" latch
begins to accept new values in preparation for the next rising clock edge.
 By removing the leftmost inverter in the circuit at side, a D-type flip flop that strobes on
the falling edge of a clock signal can be obtained.
T-Flip-flop:
 If T input is high, flip-flop changes state ("toggles") whenever the clock input is stored. If
T input is low, the flip-flop holds the previous value.
 A T flip-flop can also be built using an edge-triggered D flip-flop with its D input fed
from its own inverted output

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a)Flip Flops
i) Master Slave JK Flip-Flop
Truth Table

Circuit Diagram

ii) D Flip Flop

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iii) T Flip Flop

Procedure:
1. All the components are checked for their working.
2. IC is inserted into the IC base.
3. Connections are made as per the circuit diagram
4. Truth Table is verified and the outputs are observed.

Result: Flip Flop Circuits are Verified with the corresponding truth table

b) Shift Registers and Counters

Components Required:

Theory:
Cascade of flip flops, sharing the same clock, which has the output of anyone but the last flip-
flop connected to the "data" input of the next one in the chain, resulting in a circuit that shifts by
one position the one-dimensional "bit array" stored in it, shifting in the data present at its input
and shifting out the last bit in the array, when enabled to do so by a transition of the clock input.
There are also bi-directional shift registers which allow shifting in both directions: L→R or
R→L. The serial input and last output of a shift register can also be connected together to create
a circular shift register. Shift registers can have both parallel and serial inputs and outputs. There
are also types that have both serial and parallel input and types with serial and parallel output.
Ring counter

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Ring counter is a basic register with direct feedback such that the contents of the register simply
circulate around the register when the clock is running. Here the last output that is QD in a shift
register is connected back to the serial input. It is made by connecting Q&Q‟ output of one JK
FF to J&K input of next FF respectively. The output of final FF is connected to the input of first
FF. To start the counter the first FF is set by using preset facility and the remaining FF are reset

input. When the clock arrives the set condition continues to shift around the ring. As it can be
seen from the truth table there are four unique output stages for this counter. The modulus value
of a ring counter is n, where n is the number of flip flops. Ring counter is called divided by N
counter where N is the number of FF.
Johnson counter (Twisted ring counter)
A basic ring counter can be slightly modified to produce another type of shift register counter
called Johnson counter. Here complement of last output is connected back to the not gate input
and not gate output is connected back to serial input. A four bit Johnson counter gives 8 state
output. The modulus value of a ring counter can be doubled by making a small change in the ring
counter circuit. The Q‟ and Q of the last FFS are connected to the J and K input of the first FF
respectively. This is the Johnson counter. Initially the FFs are reset. After first clock pulse FF0 is
set and the remaining FFs are reset. After the eight clock pulse all the FFS are reset. There are
eight different conditions creating a mode 8 Johnson counter. Johnson counter is called a twisted
ring counter or divide by 2N counter.
Pin Configuration

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i) Serial in serial out (SISO) (Right Shift)

SISO:-
1. M=0, clks -> CP,
2. Input is given at DS[give 1 or 0 at DS press the mono pulsar]
3. The o/p shifts right QA, to QD.
4. After the 4th clock pulse o/p is seen at QA, QB, QC,QD.
5. Continue pressing the mono pulse , o/p is seen at QD.

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ii) Serial in parallel out (SIPO)

SIPO:-
After the 4th clock pulse o/p is seen at. QA, QB, QC,QD.
Example if i/p is 1011 o/p is 1101.

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iii) Parallel in serial out (PISO)

PISO:-
1. M=1, clk-> CP, clks- >1.
2. Load the parallel data ABCD , which gets stored in QA, QB, QC,QD.
3. Clks- >CP, M=0.
4. Output is observed at QD.

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iv) Parallel in parallel out (PIPO)

PIPO:-
1. M=1, clk-> CP
2. Give the data through ABCD , give CP
3. The o/p is stored in . QA, QB, QC,QD.

v) Ring Counter

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vi) Johnson Counter

Procedure:
1) Check all the components for their working.
2) Insert the appropriate IC into the IC base.
3) Make connections as shown in the circuit diagram.
4) Load data parallely with clock pulse and M=1
5) Interconnect Clk1 & Clk2
6) Verify the Truth Table and observe the outputs.

Result: The various operations of a shift register, Ring and Johnson Counter is verified.

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EXPERIMENT 8
Aim :

a) Design Mod – N Synchronous Up Counter & Down Counter using 7476 JK Flip-flop
b) Mod-N Counter using IC7490 / 7476
c) Synchronous counter using IC74192

Components Required:

Theory:
Circuits for counting events are frequently used in computers and other digital systems. Since a
counter circuit must remember its past states, it has to possess memory. The number of flip flops
used and how they are connected determine the number of states and the sequence of the states
that the counter goes through in each complete cycle. Counters can be classified into two broad
categories according to the way they are clocked:
Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock pulse, and
then each successive flip -flop is clocked by the Q or Q' output of the previous flip -flop.
Asynchronous counters are those whose output is free from the clock signal. Because the flip
flops in asynchronous counters are supplied with different clock signals, there may be delay in
producing output. The required number of logic gates to design asynchronous counters is very
less. So they are simple in design. Another name for Asynchronous counters is “Ripple
counters”. The number of flip flops used in a ripple counter is depends up on the number of
states of counter (ex: Mod 4, Mod 2 etc). The number of output states of counter is called
“Modulus” or “MOD” of the counter. The maximum number of states that a counter can have is
2n where n represents the number of flip flops used in counter. For example, if we have 2 flip
flops, the maximum number of outputs of the counter is 4 i.e. 22. So it is called as “MOD-4
counter” or “Modulus 4 counter” 2. Synchronous Counters - all memory elements are

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simultaneously triggered by the same clock. A mod N counter is a counter that has N states. Its
output frequency is f/N.
Synchronous Counter: the external clock signal is connected to the clock input of EVERY
individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. In other words,
changes in the output occur in “synchronization” with the clock signal. The result of this
synchronization is that all the individual output bits changing state at exactly the same time in
response to the common clock signal with no ripple effect and therefore, no propagation delay.
Pin Configuration: (7490- Decade Counter)

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Pin Configuration: (74192- Decade Up/down Counter)

Circuit Diagram:
Case 1: (a) 7490 AS MOD-2 / MOD-5 COUNTER

Case 2: 7490 AS MOD-10 Counter

Case 3: 7490 AS MOD-8 Counter

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Case 4: 7490 AS MOD-6 Counter

Case 5: MOD-6 UP COUNTER: Invalid state 0110 (Using IC- 74192)

Case 6 :3 to 9 Counter (Using IC- 74192)

Procedure:
1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.

Result: Counter circuits are designed and verified.

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EXPERIMENT 9
Aim: Design and Test the second order Active Filters and plot the frequency response,
i) Low pass and Highpass Filter
ii) Bandpass and Bandstop Filter
i) Low Pass and Highpass Filter
Components Required
APPARATUS SPECIFICATION QUANTITY
SIGNAL (0-10)mHz 1
GENERATOR
Op amp IC741 3
Resistors 1kΩ,1.5kΩ 2,1,2,4
5kΩ,10kΩ
Capacitor 0.1μf 4
linear power supply ±15V 1
DSO - 1
Theory

Electronic filters are circuits which perform signal processing functions, specifically
to remove unwanted frequency components from the signal, to enhance wanted ones,
or both. Electronic filter high-pass, low-pass, band-pass, band-stop (band-rejection;
notch), or all- pass.

Active Low Pass Filter:

The most common and easily understood active filter is the Active Low Pass Filter. Its
principle of operation and frequency response is exactly the same as those for the
previously seen passive filter, the only difference this time is that it uses an op-amp for
amplification and gain control. The simplest form of a low pass active filter is to
connect an inverting or non-inverting amplifier.

High Pass Filter :

A first-order (single-pole) Active High Pass Filter as its name implies, attenuates low
frequencies and passes high frequency signals. It consists simply of a passive filter
section followed by a non-inverting operational amplifier. The frequency response of
the circuit is the same as that of the passive filter, except that the amplitude of the
signal is increased by the gain of the amplifier and for a non-inverting amplifier the

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value of the pass band voltage gain is given as 1 + R2/R1, the same as for the low pass
filter circuit.

Band Pass Filter:

The cut-off frequency or ƒc point in a simple RC passive filter can be accurately

controlled using just a single resistor in series with a non-polarized capacitor, and
depending upon which way around they are connected, we have seen that either a Low
Pass or a High Pass filter is obtained.By connecting or “cascading” together a single
Low Pass Filter circuit with a High Pass Filter circuit, we can produce another type of
passive RC filter that passes a selected range or “band” of frequencies that can be
either narrow or wide while attenuating all those outside of this range. This new type
of passive filter arrangement produces a frequency selective filter known commonly as
a Band Pass Filter or BPF for short.

Unlike a low pass filter that only pass signals of a low frequency range or a high pass
filter which pass signals of a higher frequency range, a Band Pass Filters passes signals
within a certain “band” or “spread” of frequencies without distorting the input signal or
introducing extra noise. This band of frequencies can be any width and is commonly
known as the filters Bandwidth.

Band reject Filter:

The Band Stop Filter, (BSF) is another type of frequency selective circuit that
functions in exactly the opposite way to the Band Pass Filter we looked at before. The
band stop filter, also known as a band reject filter, passes all frequencies with the
exception of those within a specified stop band which are greatly attenuated.

If this stop band is very narrow and highly attenuated over a few hertz, then the band
stop filter is more commonly referred to as a notch filter, as its frequency response
shows that of a deep notch with high selectivity (a steep-side curve) rather than a
flattened wider band.

The function of a band stop filter is too pass all those frequencies from zero (DC) up to
its first (lower) cut-off frequency point ƒL, and pass all those frequencies above its

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second (upper) cut-off frequency ƒH, but block or reject all those frequencies in-
between. Then the filters bandwidth, BW is defined as: (ƒH – ƒL).
Design

( )

Circuit Diagram
Low Pass Filter

High Pass Filter

Band Pass Filter

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Band Reject Filter

Frequency Response

Low Pass Filter

High Pass Filter

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Band Pass Filter

Band Reject Filter

TABULATION:

LPF:

INPUT OUTPUT GAIN GAIN IN dB

VOLTAGE(V)
FREQUENCY(HZ)

HPF:

INPUT OUTPUT GAIN GAIN IN dB

VOLTAGE(V)
FREQUENCY(HZ)

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BPF:

INPUT OUTPUT GAIN GAIN IN dB

VOLTAGE(V)
FREQUENCY(HZ)

BRF:

INPUT OUTPUT GAIN GAIN IN dB

VOLTAGE(V)
FREQUENCY(HZ)

PROCEDURE

1. Connect the circuit as shown in diagram.

2. Connect the DSO to the probes and switch it on.

3. Check the graph for both positive and negative voltage and write down the output.

RESULT:

Thus the various active filter circuits, low pass, high pass, band pass was designed and the
frequency response was analyzed.

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EXPERIMENT 10
Aim: Design and test Monostable and Astable Multivibrator using 555 Timer
a) Monostable Multivibrator
Components Required: Timer - 555 Resistors 10kὩ Capacitors – 0.01pF, 0.1 Pf
Theory:

Monostable multivibrator has a stable state and a quasi stable state, the output of it is normally
low and it corresponds to reset of the flip flop in the timer, on the application of external
negative trigger pulse at pin 2 the circuit is triggered and the flip flop in the timer is set which in
turn releases the short across C and pushes the output high, At the same time the voltage across
C rises exponentially with the time constant RAC and remains in this state for a period RAC
even if it is triggered again during this interval, When the voltage across the capacitor reaches
2/3 Vcc, the threshold comparator resets the flip flop in the timer which discharges C and the
output is driven low the circuit will remain in this state until the application of the next trigger
pulse.
Circuit Diagram:

Monostable Multivirator using 555 IC

Procedure:
1. Rig up the circuit as shown in the circuit diagram.
2. Apply the supply voltage of +5V
3. Observe the output waveform at Pin 3.
4. Calculate the pulse width & compare with theoretical valve.
5. Observe the capacitor voltage at Pin 7

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Output Waveform:

Result:

b) Astable Multivibrator:

Components Required: Timer - 555 Resistors- 4.7KΩ, 10KΩ, 5.86 KΩ Capacitors -0.01pF,
680 pF

Theory:

Astable multivibrator is a free running oscillator has two quasi stable state in one state o/p
voltage remains low for a time interval of Toff and then switches over to other state in which the
o/p remains high for an interval of Ton the time interval Ton and Toff are determined by the
external resistors a capacitor and it does not require an external trigger, when the power is
switched on the timing capacitor begins to charge towards 2/3 Vcc through RA & RB, when the
capacitor voltage has reached this value, the upper comparator of the timer triggers the flip flop
in it and the capacitor begins to discharge through RB when the capacitor voltage reaches 1/3

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Vcc the lower comparator is triggered and another cycle begins, the charging and discharging
cycle repeats between 2/3 Vcc and 1/3Vcc for the charging and discharging periods t1and t2
respectively. Since the capacitor charges through RA and RB and discharges through RB only
the charge and discharge are not equal as a consequence the output is not a symmetrical square
wave and the multivibrator is called an asymmetric astable multivibrator
Circuit Diagram:

Asymmetric Astable Multivibrator

Symmetric Astable Multivibrator

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Design:
Assume C = 0.01 μF

TL=0.693xRBxC , then RB = ……..

TH  0.693x(RA+RB) then RA =……….

The resistance RA and RB should be in the range of 1k to 10k to limit the collector current of
theinternal transistor.

Procedure:
1. Connections are made as shown in the circuit diagram
2. Switch on the DC power supply unit
3. Observe the wave form on CRO at pin 3 and measure the o/p pulse amplitude
4. Observe the wave form on CRO at pin 6 and measure Vcmax and Vc min
5. Verify that Vcmax=2/3Vcc and Vc min=1/3 Vcc
6. Calculate the duty cycle D, o/p frequency and verify with specified value
Tabular Column:

Output Waveform:

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Result:

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EXPERIMENT 11
Aim: Design and Test a Regulated Power supply
Components Required:
30 MHz Dual Channel Cathode Ray Oscilloscope
3 MHz Function Generator
0-30 V dc dual regulated power supply
4 ½ digit Digital Multimeter
230 V/ 9 V, 1A Step down transformer
1N4007 Diode
IC 7805
Resistor 100Ω,
¼W Electrolytic Capacitor 1000µF/25V
Ceramic Capacitor 0.33 µF, 0.1 µF
Breadboard and Connecting wires BNC Cables and Probes
THEORY
 Every electronic circuit is designed to operate off of supply voltage, which is
usually constant.
 A regulated power supply provides this constant DC output voltage and
continuously holds the output voltage at the design value regardless of
changes in load current or input voltage.
 The power supply contains a rectifier, filter, and regulator.
 The rectifier changes the AC input voltage to pulsating DC voltage.
 The filter section removes the ripple component and provides an unregulated
DC voltage to the regulator section.
 The regulator is designed to deliver a constant voltage to the load under
varying circuit conditions.

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 The two factors that can cause the voltage across the load to vary are
fluctuations in input voltage and changes in load current requirements.
 Load regulation is a measurement of power supply, showing its capacity to
maintain a constant voltage across the load with changes in load current.
Line regulation is a measurement of power supply, showing its capacity to
maintain a constant output voltage with changes in input voltage.
The filter section should have a voltage of at least 7.5V as input to regulator IC.
That is Vdc = 7.5 V

Output wave shape from a full-wave

filtered rectifier Ripple voltage = ΔV = Vr

Two figures of merit for power supplies are the ripple voltage, Vr, and the
ripple factor, RF. RF = Vr(rms) / Vdc

Vdc = 2Vm/π = 0.636 Vm

Vr = IL x Toff/C can be solved for the value of C.

The ripple frequency of the full-wave ripple is 100 Hz. The off-time of the diodes for 100 Hz
ripple is assumed to be 85%. Toff = 8.5mS.

C = IL x Toff / Vr =

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CIRCUIT DIAGRAM

Load Regulation
1. Observe the No load voltage and Full load voltage
2. Calculate the load regulation.

Load Regulation = ((VNL – VFL)/VFL) x 100 %

Theoretical efficiency of linear voltage regulator =

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VIVA QUESTIONS
Analog Electronics
1. What is a rectifier?
2. Why do you need a rectifier?
3. What is the meaning of ripple?
4. What are the different filter configurations available to remove these ripples?
5. What is the value of ripple factor for a Full wave rectifier? Is this different for a Bridge
rectifier?
6. What is the value of efficiency for a Full wave rectifier? Is this different for a Bridge
rectifier?
7. Write the equation for the ripple factor of a full wave rectifier with C – filter.
8. Write the equation for Vdc of a full wave rectifier with C – filter.
9. Explain the concept of Zener breakdown?
10. How depletion region gets thin by increasing doping level in Zener diode?
11. State the reason why an ordinary diode suffers avalanche breakdown rather than Zener
breakdown?
12. Give the reasons why Zener diode acts as a reference element in the voltage regulator
circuits.
13. What type of biasing must be used when a Zener diode is used as a regulator?
14. What are the advantages of the Series feedback regulator?
15. Why do you need high input impedance?
16. What is the input impedance of an ordinary emitter follower?
17. Indicate the methods by which you can increase the input impedance of the emitter
follower.
18. State Miller‟s theorem. How does this theorem help you in your circuit?
19. Draw the AC equivalent circuit of the Boot strapped emitter follower and show how the
effect of the bias resistors is altered.
20. What is an amplifier?
21. What kind of bias should be applied for the transistor to act as an amplifier?
22. What are the bias conditions for transistor to be in (a) Saturation region? (b) Cut off
region? (c) Active region?
23. What is early effect? Is it an advantage or a disadvantage?
24. Mention different types of transistor biasing methods.
25. Which biasing method provides stabilization against variations in ICO, β, VBE?
26. What are the different methods of coupling amplifier stages?
27. What is the advantage of RC Coupling?
28. Write an expression for the mid – band voltage gain for a single stage RC coupled
amplifier.
29. Which are the components that affect the lower cut – off frequency?
30. Which are the components that affect the upper cut – off frequency?
31. Does the Emitter by – pass capacitor have any effect on the cut – off frequencies? Which
cut – off frequency will it affect?

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32. Write an expression for the voltage gain of the amplifier in the low frequency region in
terms of mid-band gain and lower cut – off frequency
33. Write an expression for the voltage gain of the amplifier in the high frequency region in
terms of mid-band gain and upper cut – off frequency.
34. What are the merits and de-merits of the R – C Coupled amplifier?
35. Write equations for the Gain, Input Impedance, Output Impedance, Upper Cut-off
frequency and Lower Cut-off frequency of a feedback amplifier in terms of these
quantities without feedback.
36. What makes the Input impedance with feedback to be different than the theoretical
value?
37. What are the effects of „Negative feedback‟? Just mention the effects by writing relevant
equations.
38. What are the classifications of Field effect transistors?
39. Write the symbols for an N – Channel JFET and a P – Channel JFET.
40. What are the advantages of Field effect transistors?
41. What decides the maximum signal handling capacity of the FET RC coupled amplifier?
42. What are MOSFET‟s?
43. What is the difference between MOSFET and BJT?
44. What are the types of MOSFET?
45. What is the difference between depletion mode and enhancement mode MOSFET‟s?
46. How does n-drift region affect MOSFET?
47. How MOSFET‟s are suitable for low power high frequency applications?
48. What are the requirements of gate drive in MOSFET?
49. What is rise time and fall time?
50. What is pinch off voltage?
51. In which region the MOSFET is used as a switch?
52. Which parameter defines the transfer characteristics?
53. Why MOSFET‟s are mainly used for low power applications?
54. How MOSFET is turned off?
55. What are the advantages of vertical structure of MOSFET?
56. What are the merits of MOSFET?
57. What are demerits of MOSFET?
58. What are the applications of MOSFET?
59. What are power amplifiers?
60. How are power amplifiers different from conventional Voltage or Current amplifiers?
61. Define the efficiency of a power amplifier.
62. What are the efficiencies of R-C Coupled Class A, Single ended Class A and Class B
power amplifiers?
63. What are the disadvantages of Class B power amplifiers with center tapped transformer?
64. What is cross –over distortion? What is the reason for this distortion?
65. How this distortion can be eliminated? Explain.
66. What are „complimentary symmetry‟ transistors?

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67. Write the applications of Power amplifiers.

68. What is an oscillator? What kind of feedback is used in oscillator circuits?
69. What are the conditions to be satisfied in order to produce oscillations? What are these
conditions called?
70. Write other versions of Hartley oscillator circuits.
71. What are Relaxation Oscillators?
72. Why LC oscillators are not suitable for Audio frequencies?

Digital Electronics

73. Define gates.

74. Define IC.
75. Why NAND & NOR gates are called universal gates?
76. Realize the EX – OR gates using minimum number of NAND gates.
77. Give the truth table for EX-NOR and realize using NAND gates?
78. What are the logic low and High levels of TTL IC‟s and CMOS IC‟s?
79. Compare TTL logic family with CMOS family?
80. Which logic family is fastest and which has low power dissipation?
81. Define Universal Gates
82. Why NAND and NOR Gates are called as Universal Gates
83. What is a half adder?
84. What is a full adder?
85. What are the applications of adders?
86. What is a half subtractor?
87. What is a full subtractor?
88. What are the applications of subtractors?
89. Obtain the minimal expression for above circuits.
90. Realize a full adder using two half adders
91. Realize a full subtractors using two half subtractors
92. What is the internal structure of 7483 IC?
93. What do you mean by code conversion?
94. What are the applications of code conversion?
95. How do you realize a subtractor using full adder?
96. What is a ripple Adder? What are its disadvantages?
97. What is a comparator?
98. What are the applications of comparator?
99. Derive the Boolean expressions of one bit comparator and two bit comparators.
100. How do you realize a higher magnitude comparator using lower bit comparator
101. Design a 2 bit comparator using a single Logic gates?
102. What is a multiplexer?
103. What are the applications of multiplexer?

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104. Derive the Boolean expression for multiplexer.

105. How do you realize a given function using multiplexer In 2n to 1 multiplexer how
many selection lines are there?
106. What is the difference between Flip-Flop & latch?
107. Give examples for synchronous & asynchronous inputs?
108. What are the applications of different Flip-Flops?
109. What is the advantage of Edge triggering over level triggering?
110. What is the relation between propagation delay & clock frequency of flip-flop?
111. What is race around in flip-flop & how to overcome it?
112. Convert the J K Flip-Flop into D flip-flop and T flip-flop?
113. List the functions of asynchronous inputs?
114. What is the definition of a register in the context of digital circuitry? Also, define and
115. compare/ contrast what a shift register is.
116. Explain the difference between serial digital data and parallel digital data.
117. Draw the schematic diagram for a five-bit serial-in/serial-out shift register circuit, and
be prepared to give a brief explanation of how it functions.
118. Applications of Shift Registers
119. Explain what a universal shift register is.
120. Switch contact bounce is often a problem when connecting mechanical contact
switches or relays to the inputs of digital semiconductor circuits. When a switch
transitions from open to closed, or from closed to open, there is usually a burst of
on/off pulses rather than a single, crisp, change of logic state:
121. What is counter? What are Synchronous and Asynchronous counters
122. What are the implements of counter?
123. Explain Asynchronous (ripple) counter?
124. Explain Johnson counter?
125. Explain Decade counter?
126. What is the difference between a counter and a register?
127. What is a counter?
128. What is the difference between a synchronous counter and asynchronous counter?
129. What type of flip flop is used to design a asynchronous counter?
130. In a mod-16 counter, each of the flip flop used has a delay of 20ns. To get an output
at the MSB how long does it take in a synchronous counter and in a asynchronous
counter?
131. Why is an asynchronous counter called as a ripple counter?
132. Define modulus of a counter.
133. What type of counter is 7490?
134. What type of counter is 74192 and 74193?
135. What type of flip flop is used to design a synchronous counter?
136. What is data lockout in a counter?
137. How is data lockout overcome?
138. Is the output of a counter always a square wave?

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139. If the maximum clock frequency of a JK flip flop is 45Mhz, what happens if 100 Mhz
is given
140. What is the necessity for sequence generation?
141. What are PISO, SIPO, and SISO with respect to shift register?
142. Differentiate between serial data & parallel data
143. What is the significance of Mode control bit
144. How many Flip-flops are present in IC 7495

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