Question Bank

Logic Circuit Design

Sequential Circuits

1. A latch is an example of a ___________

a) Monostable multivibrator
b) Astable multivibrator
c) Bistable multivibrator
d) 555 timer

Answer: c
Explanation: A latch is an example of a bistable multivibrator. A Bistable multivibrator is one
in which the circuit is stable in either of two states. It can be flipped from one state to the
other state and vice-versa.
2. Latch is a device with ___________
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states

Answer: b
Explanation: Since a latch works on the principal of bistable multivibrator. A Bistable
multivibrator is one in which the circuit is stable in either of two states. It can be flipped from
one state to the other state and vice-versa. So a latch has two stable states.
3. Why latches are called memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data

Answer: c
Explanation: Latches can be memory devices, and can store one bit of data for as long as the
device is powered. Once device is turned off, the memory gets refreshed.
4. Two stable states of latches are ___________
a) Astable & Monostable
b) Low input & high output
c) High output & low output
d) Low output & high input

Answer: c
Explanation: A latch has two stable states, following the principle of Bistable Multivibrator.
There are two stable states of latches and these states are high-output and low-output.
5. How many types of latches are ___________
a) 4
b) 3
c) 2
d) 5

Answer: a
Explanation: There are four types of latches: SR latch, D latch, JK latch and T latch. D latch
is a modified form of SR latch whereas, T latch is an advanced form of JK latch.
6. The full form of SR is ___________
a) System rated
b) Set reset
c) Set ready
d) Set Rated

Answer: b
Explanation: The full form of SR is set/reset. It is a type of latch having two stable states.
7. The SR latch consists of ___________
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs

Answer: b
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states.
The diagram of SR latch is shown below:

8. The outputs of SR latch are ___________

a) x and y
b) a and b
c) s and r
d) q and q’

Answer: d
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:

.
9. The NAND latch works when both inputs are ___________
a) 1
b) 0
c) Inverted
d) Don’t cares

Answer: a
Explanation: The NAND latch works when both inputs are 1. Since both of the inputs are
inverted in a NAND latch.
10. The first step of the analysis procedure of SR latch is to ___________
a) label inputs
b) label outputs
c) label states
d) label tables

Answer: b
Explanation: All flip flops have at least one output labeled Q (i.e. inverted). This is so
because the flip flops have inverting gates inside them, hence in order to have both Q and Q
complement available, we have atleast one output labelled.
11. The inputs of SR latch are ___________
a) x and y
b) a and b
c) s and r
d) j and k

Answer: c
Explanation: SR or Set-Reset latch is the simplest type of bistable multivibrator having two
stable states. The inputs of SR latch are s and r while outputs are q and q’. It is clear from the
diagram:
12. When a high is applied to the Set line of an SR latch, then ___________
a) Q output goes high
b) Q’ output goes high
c) Q output goes low
d) Both Q and Q’ go high

Answer: a
Explanation: S input of an SR latch is directly connected to the output Q. So when a high is
applied Q output goes high and Q’ low.
13. When both inputs of SR latches are low, the latch ___________
a) Q output goes high
b) Q’ output goes high
c) It remains in its previously set or reset state
d) it goes to its next set or reset state

Answer: c
Explanation: When both inputs of SR latches are low, the latch remains in it’s present state.
There is no change in output.
14. When both inputs of SR latches are high, the latch goes ___________
a) Unstable
b) Stable
c) Metastable
d) Bistable

Answer: c
Explanation: When both gates are identical and this is “metastable”, and the device will be in
an undefined state for an indefinite period.
15. Latches constructed with NOR and NAND gates tend to remain in the latched condition
due to which configuration feature?
a) Low input voltages
b) Synchronous operation
c) Gate impedance
d) Cross coupling

Answer: d
Explanation: Latch is a type of bistable multivibrator having two stable states. Both inputs of
a latch are directly connected to the other’s output. Such types of structure is called cross
coupling and due to which latches remain in the latched condition.
16. One example of the use of an S-R flip-flop is as ___________
a) Transition pulse generator
b) Racer
c) Switch debouncer
d) Astable oscillator

Answer: c
Explanation: The SR flip-flop is very effective in removing the effects of switch bounce,
which is the unwanted noise caused during the switching of electronic devices.
17. The truth table for an S-R flip-flop has how many VALID entries?
a) 1
b) 2
c) 3
d) 4

Answer: c
Explanation: The SR flip-flop actually has three inputs, Set, Reset and its current state. The
Invalid or Undefined State occurs at both S and R being at 1.
18. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle

Answer: c
Explanation: After one cycle the value of each input comes to the same value. Eg: Assume
J=0 and K=1. After 1 cycle, it becomes as J=0->1->0(1 cycle complete) and K=1->0->1(1
cycle complete). The J & K flip-flop has 4 stable states: Latch, Reset, Set and Toggle.
19. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH

Answer: a
Explanation: In D flip flop, when the clock is high then the output depends on the input
otherwise reminds previous output. In a state of clock high, when D is high the output Q also
high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an
invalid state at both inputs being 1.
20. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates

Answer: c
Explanation: The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND
gates. Cross coupling means the output of second gate is fed to the input of first gate and
vice-versa.
21. The logic circuits whose outputs at any instant of time depends only on the present input
but also on the past outputs are called ________________
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Answer: b
Explanation: In sequential circuits, the output signals are fed back to the input side. So, The
circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called sequential circuits. Unlike sequential circuits, if output depends only
on the present state, then it’s known as combinational circuits.
22. Whose operations are more faster among the following?
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops

Answer: a
Explanation: Combinational circuits are often faster than sequential circuits. Since the
combinational circuits do not require memory elements whereas the sequential circuits need
memory devices to perform their operations in sequence. Latches and Flip-flops come under
sequential circuits.
23. How many types of sequential circuits are?
a) 2
b) 3
c) 4
d) 5

Answer: a
Explanation: There are two type of sequential circuits viz., (i) synchronous or clocked and (ii)
asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of
a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock
signal.
24. The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder

Answer: b
Explanation: The sequential circuit is also called a latch because both are a memory cell,
which are capable of storing one bit of information.
25. The basic latch consists of ___________
a) Two inverters
b) Two comparators
c) Two amplifiers
d) Two adders

Answer: a
Explanation: The basic latch consists of two inverters. It is in the sense that if the output Q =
0 then the second output Q’ = 1 and vice versa.
26. In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state

Answer: b
Explanation: In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

27. The output of latches will remain in set/reset untill ___________

a) The trigger pulse is given to change the state
b) Any pulse given to go into previous state
c) They don’t get any pulse more
d) The pulse is edge-triggered

Answer: a
Explanation: The output of latches will remain in set/reset untill the trigger pulse is given to
change the state.
28. What is a trigger pulse?
a) A pulse that starts a cycle of operation
b) A pulse that reverses the cycle of operation
c) A pulse that prevents a cycle of operation
d) A pulse that enhances a cycle of operation

Answer: a
Explanation: Trigger pulse is defined as a pulse that starts a cycle of operation.
29. The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
a) Because of inverted outputs
b) Because of triggering functionality
c) Because of cross-coupled connection
d) Because of inverted outputs & triggering functionality

Answer: c
Explanation: The cross-coupled connections from the output of one gate to the input of the
other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch
classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous
because they function in the absence of a clock pulse.
30. What is an ambiguous condition in a NAND based S’-R’ latch?
a) S’=0, R’=1
b) S’=1, R’=0
c) S’=1, R’=1
d) S’=0, R’=0

Answer: d
Explanation: In a NAND based S-R latch, If S’=0 & R’=0 then both the outputs (i.e. Q & Q’)
goes HIGH and this condition is called an ambiguous/forbidden state. This state is also
known as an Invalid state as the system goes into an unexpected situation.
31. In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
a) No change
b) Set
c) Reset
d) Forbidden

Answer: a
Explanation: In a NAND based S’-R, latch if S’=1 & R’=1 then there is no any change in the
state. It remains in its prior state. This state is used for the storage of data.
32. A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
a) A D latch at each of its input
b) An inverter at each of its input
c) It can never be converted
d) Both a D latch and an inverter at its input

Answer: d
Explanation: A NAND based S’-R’ latch can be converted into S-R latch by placing either a
D latch or an inverter at its input as it’s operations will be complementary.
33. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is
____________
a) The inputs of NOR latch are 0 but 1 for NAND latch
b) The inputs of NOR latch are 1 but 0 for NAND latch
c) The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch
d) The output of NOR latch is 1 but 0 for NAND latch

Answer: a
Explanation: Due to inverted input of NAND based S’-R’ latch, the inputs of NOR latch are 0
but 1 for NAND latch.
34. The characteristic equation of S-R latch is ____________
a) Q(n+1) = (S + Q(n))R’
b) Q(n+1) = SR + Q(n)R
c) Q(n+1) = S’R + Q(n)R
d) Q(n+1) = S’R + Q'(n)R

Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific
output in order to satisfy the truth table. The characteristic equation of S-R latch is Q(n+1) =
(S + Q(n))R’.
35. The difference between a flip-flop & latch is ____________
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one

Answer: c
Explanation: Flip-flop is a modified version of latch. To determine the changes in states, an
additional control input is provided to the latch.
36. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5

Answer: c
Explanation: There are 4 types of flip-flops, viz., S-R, J-K, D, and T. D flip-flop is an
advanced version of S-R flip-flop, while T flip-flop is an advanced version of J-K flip-flop.
37. The S-R flip flop consist of ____________
a) 4 AND gates
b) Two additional AND gates
c) An additional clock input
d) 3 AND gates

Answer: b
Explanation: The S-R flip flop consists of two additional AND gates at the S and R inputs of
S-R latch.
38. What is one disadvantage of an S-R flip-flop?
a) It has no Enable input
b) It has a RACE condition
c) It has no clock input
d) Invalid State

Answer: d
Explanation: The main drawback of s-r flip flop is invalid output when both the inputs are
high, which is referred to as Invalid State.
39. One example of the use of an S-R flip-flop is as ____________
a) Racer
b) Stable oscillator
c) Binary storage register
d) Transition pulse generator

Answer: c
Explanation: S-R refers to set-reset. So, it is used to store two values 0 and 1. Hence, it is
referred to as binary storage element. It functions as memory storage during the No Change
State.
40. When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) When the Q output is complementary of the input

Answer: b
Explanation: Flip-flop have the property of responding immediately to the changes in its
inputs. This property is called transparency.
41. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW

Answer: c
Explanation: Edge triggered device will follow when there is transition. It is a positive edge
triggered when transition takes place from low to high, while, it is negative edge triggered
when the transition takes place from high to low.
42. What is the hold condition of a flip-flop?
a) Both S and R inputs activated
b) No active S or R input
c) Only S is active
d) Only R is active

Answer: b
Explanation: The hold condition in a flip-flop is obtained when both of the inputs are LOW.
It is the No Change State or Memory Storage state if a flip-flop.
43. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R
input goes to 0, the latch will be ________
a) SET
b) RESET
c) Clear
d) Invalid

Answer: b
Explanation: If S=0, R=1, the flip flop is at reset condition. Then at S=0, R=0, there is no
change. So, it remains in reset. If S=1, R=0, the flip flop is at the set condition.
44. The circuit that is primarily responsible for certain flip-flops to be designated as edge-
triggered is the _____________
a) Edge-detection circuit
b) NOR latch
c) NAND latch
d) Pulse-steering circuit

Answer: a
Explanation: The circuit that is primarily responsible for certain flip-flops to be designated as
edge-triggered is the edge-detection circuit.
45. Which circuit is generated from D flip-flop due to addition of an inverter by causing
reduction in the number of inputs?
a) Gated JK-latch
b) Gated SR-latch
c) Gated T-latch
d) Gated D-latch
Answer: d
Explanation: Since, both inputs of the D flip-flop are connected through an inverter. And this
causes reduction in the number of inputs.

46. The characteristic of J-K flip-flop is similar to _____________

a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) Gated T flip-flop

Answer: a
Explanation: In an S-R flip-flop, S refers to “SET” whereas R refers to “RESET”. The same
behaviour is shown by J-K flip-flop.
47. A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
___________
a) Two AND gates
b) Two NAND gates
c) Two NOT gates
d) Two OR gates

Answer: a
Explanation: A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting
two AND gates.
48. How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Answer: d
Explanation: When j=k=1 then the race condition is occurs that means both output wants to
be HIGH. Hence, there is toggle condition is occurs, where 0 becomes 1 and 1 becomes 0.
That is device is either set or reset.
49. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is
HIGH is called ___________
a) Parity error checking
b) Ones catching
c) Digital discrimination
d) Digital filtering

Answer: b
Explanation: Ones catching means that the input transitioned to a 1 and back very briefly
(unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it
caught the 1. Similarly for 0’s catching.
50. In J-K flip-flop, “no change” condition appears when ___________
a) J = 1, K = 1
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 0, K = 0

Answer: d
Explanation: If J = 0, K = 0, the output remains unchanged. This is the memory storing state.
51. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave

Answer: d
Explanation: The flip flop is sensitive only to the positive or negative edge of the clock pulse.
So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-
flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve
has a time period twice that of the clock. Frequency is inversely related to time period and
hence frequency gets halved.
52. What is the significance of the J and K terminals on the J-K flip-flop?
a) There is no known significance in their designations
b) The J represents “jump,” which is how the Q output reacts whenever the clock goes high
and the J input is also HIGH
c) The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit
d) All of the other letters of the alphabet are already in use

Answer: c
Explanation: The letters J & K were chosen in honour of Jack Kilby, the inventory of the
integrated circuit. In J&K flip-flops, the invalid state problem is resolved, thus leading to the
toggling of states.
53. On a J-K flip-flop, when is the flip-flop in a hold condition?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1

Answer: a
Explanation: At J=0 k=0 output continues to be in the same state. This is the memory storing
state.
54. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters.
After four input clock pulses, the binary count is ________
a) 00
b) 11
c) 01
d) 10

Answer: a
Explanation: Every O/P repeats after its mod. Here mod is 4 (because 2 flip-flops are used.
So mod = 22 = 4). So after 4 clock pulses the O/P repeats i.e. 00.
55. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency
(fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
a) 1 kHz
b) 2 kHz
c) 4 kHz
d) 16 kHz

Answer: b
Explanation: 32/2=16:-first flip-flop, 16/2=8:- second flip-flop, 8/2=4:- third flip-flop,
4/2=2:- fourth flip-flop. Since the output frequency is determined on basis of the 4th flip-flop.
56. Determine the output frequency for a frequency division circuit that contains 12 flip-flops
with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz

Answer: b
Explanation: 12 flip flops = 212 = 4096
Input Clock frequency = 20.48*106 = 20480000
Output Clock frequency = 20480000/4096 = 5000 i.e., 5 kHz.
57. How many flip-flops are in the 7475 IC?
a) 2
b) 1
c) 4
d) 8

Answer: c
Explanation: There are 4 flip-flops used in 7475 IC and those are D flip-flops only.

58. In D flip-flop, D stands for _____________

a) Distant
b) Data
c) Desired
d) Delay

Ans b

59. The D flip-flop has _______ input.

a) 1
b) 2
c) 3
d) 4

Answer: a
Explanation: The D flip-flop has one input. The D of D-flip-flop stands for “data”. It stores
the value on the data line.
60. The D flip-flop has ______ output/outputs.
a) 2
b) 3
c) 4
d) 1

Answer: a
Explanation: The D flip-flop has two outputs: Q and Q complement. The D flip-flop has one
input. The D of D-flip-flop stands for “data”. It stores the value on the data line.
61. A D flip-flop can be constructed from an ______ flip-flop.
a) S-R
b) J-K
c) T
d) S-K

Answer: a
Explanation: A D flip-flop can be constructed from an S-R flip-flop by inserting an inverter
between S and R and assigning the symbol D to the S input.
62. In D flip-flop, if clock input is LOW, the D input ___________
a) Has no effect
b) Goes high
c) Goes low
d) Has effect

Answer: a
Explanation: In D flip-flop, if clock input is LOW, the D input has no effect, since the set and
reset inputs of the NAND flip-flop are kept HIGH.

63. In D flip-flop, if clock input is HIGH & D=1, then output is ___________
a) 0
b) 1
c) Forbidden
d) Toggle

Answer: a
Explanation: If clock input is HIGH & D=1, then output is 0. It can be observed from this
diagram:

64. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

a) The logic level at the D input is transferred to Q on NGT of CLK
b) The Q output is ALWAYS identical to the CLK input if the D input is HIGH
c) The Q output is ALWAYS identical to the D input when CLK = PGT
d) The Q output is ALWAYS identical to the D input

Answer: a
Explanation: By the truth table of D flip flop, we can observe that Q always depends on D.
Hence, for every negative trigger pulse, the logic at input D is shifted to Output Q.

65. Which of the following is correct for a gated D flip-flop?

a) The output toggles if one of the inputs is held HIGH
b) Only one of the inputs can be HIGH at a time
c) The output complement follows the input when enabled
d) Q output follows the input D when the enable is HIGH

Answer: d
Explanation: If clock is high then the D flip-flop operate and we know that input is equals to
output in case of D flip-flop. It stores the value on the data line.
66. With regard to a D latch ________
a) The Q output follows the D input when EN is LOW
b) The Q output is opposite the D input when EN is LOW
c) The Q output follows the D input when EN is HIGH
d) The Q output is HIGH regardless of EN’s input state

Answer: c
Explanation: Latch is nothing but flip flop which holds the o/p or i/p state. And in D flip-flop
output follows the input. It stores the value on the data line.
67. Which of the following is correct for a D latch?
a) The output toggles if one of the inputs is held HIGH
b) Q output follows the input D when the enable is HIGH
c) Only one of the inputs can be HIGH at a time
d) The output complement follows the input when enabled

Answer: b
Explanation: If the clock is HIGH then the D flip-flop operates and we know that input equals
to output in case of D flip flop. It stores the value on the data line.
68. Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle
b) The output will follow the input on the leading edge of the clock
c) When both inputs are LOW, an invalid state exists
d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
output on the trailing edge of the clock

Answer: b
Explanation: Edge-triggered flip-flop means the device will change state during the rising or
falling edge of the clock pulse. The main phenomenon of the D flip-flop is that the o/p will
follow the i/p when the enable pin is HIGH.
69. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input
actions will cause it to change states?
a) CLK = NGT, D = 0
b) CLK = PGT, D = 0
c) CLOCK NGT, D = 1
d) CLOCK PGT, D = 1

Answer: d
Explanation: PGT refers to Positive Going Transition and NGT refers to negative Going
Transition. Earlier, the DFF is in a clear state (output is 0). So, if D = 1 then in the next stage
output will be 1 and hence the stage will be changed.
70. A positive edge-triggered D flip-flop will store a 1 when ________
a) The D input is HIGH and the clock transitions from HIGH to LOW
b) The D input is HIGH and the clock transitions from LOW to HIGH
c) The D input is HIGH and the clock is LOW
d) The D input is HIGH and the clock is HIGH
Answer: b
Explanation: A positive edge-triggered D flip-flop will store a 1 when the D input is HIGH
and the clock transitions from LOW to HIGH. While a negative edge-triggered D flip-flop
will store a 0 when the D input is HIGH and the clock transitions from HIGH to LOW.
71. Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’?
a) Due to its capability to receive data from flip-flop
b) Due to its capability to store data in flip-flop
c) Due to its capability to transfer the data into flip-flop
d) Due to erasing the data from the flip-flop

Answer: c
Explanation: Due to its capability to transfer the data into flip-flop. D-flip-flops stores the
value on the data line.
72. The characteristic equation of D-flip-flop implies that ___________
a) The next state is dependent on previous state
b) The next state is dependent on present state
c) The next state is independent of previous state
d) The next state is independent of present state

Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific
output in order to satisfy the truth table. The characteristic equation of D flip-flop is given by
Q(n+1) = D; which indicates that the next state is independent of the present state.
73. The characteristic equation of J-K flip-flop is ______________
a) Q(n+1)=JQ(n)+K’Q(n)
b) Q(n+1)=J’Q(n)+KQ'(n)
c) Q(n+1)=JQ'(n)+KQ(n)
d) Q(n+1)=JQ'(n)+K’Q(n)

Answer: d
Explanation: A characteristic equation is needed when a specific gate requires a specific
output in order to satisfy the truth table. The characteristic equation of J-K flip-flop is given
by: Q(n+1)=JQ'(n)+K’Q(n).
74. In a J-K flip-flop, if J=K the resulting flip-flop is referred to as _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

Answer: c
Explanation: In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.
75. In J-K flip-flop, the function K=J is used to realize _____________
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) S-K flip-flop

Answer: c
Explanation: T flip-flop allows the same inputs. So, in J-K flip-flop J=K then it will work as
T flip-flop.
76. The only difference between a combinational circuit and a flip-flop is that
_____________
a) The flip-flop requires previous state
b) The flip-flop requires next state
c) The flip-flop requires a clock pulse
d) The flip-flop depends on the past as well as present states

Answer: c
Explanation: Both flip-flop and latches are memory elements with clock/control inputs. They
depend on the past as well as present states. Whereas, in case of combinational circuits, they
only depend on the present state.
77. How many stable states combinational circuits have?
a) 3
b) 4
c) 2
d) 5

Answer: c
Explanation: The two stable states of combinational circuits are 1 and 0. Whereas, in flip-
flops there is an additional state known as Forbidden State.

78. The flip-flop is only activated by _____________

a) Positive edge trigger
b) Negative edge trigger
c) Either positive or Negative edge trigger
d) Sinusoidal trigger

Answer: c
Explanation: Flip flops can be activated with either a positive or negative edge trigger.
79. The S-R latch composed of NAND gates is called an active low circuit because
_____________
a) It is only activated by a positive level trigger
b) It is only activated by a negative level trigger
c) It is only activated by either a positive or negative level trigger
d) It is only activated by sinusoidal trigger

Answer: b
Explanation: Active low indicates that only an input value of 0 sets or resets the circuit.
80. Both the J-K & the T flip-flop are derived from the basic _____________
a) S-R flip-flop
b) S-R latch
c) D latch
d) D flip-flop

Answer: b
Explanation: The SR latch is the basic block for the D latch/flip flop from which the JK and T
flip flops are derived. A latch is similar to a flip-flop, only without a clock input.
81. The flip-flops which has not any invalid states are _____________
a) S-R, J-K, D
b) S-R, J-K, T
c) J-K, D, S-R
d) J-K, D, T

Answer: d
Explanation: Unlike the SR latch, these circuits have no invalid states. The SR latch or flip-
flop has an invalid or forbidden state where no output could be determined.
10. What does the triangle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Edge triggered
c) Both Level enabled & Edge triggered
d) Level triggered
View Answer
Answer: b
Explanation: The triangle on the clock input of a J-K flip-flop mean edge triggered. Whereas
the absence of triangle symbol implies that the flip-flop is level-triggered.
11. What does the circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
View Answer
Answer: c
Explanation: The circle on the clock input of a J-K flip-flop mean negative edge triggered.
Whereas the absence of triangle symbol implies that the flip-flop is level-triggered.
12. What does the direct line on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
View Answer
Answer: d
Explanation: The direct line on the clock input of a J-K flip-flop mean level triggered.
Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.
13. What does the half circle on the clock input of a J-K flip-flop mean?
a) Level enabled
b) Positive edge triggered
c) negative edge triggered
d) Level triggered
View Answer
Answer: d
Explanation: The half circle on the clock input of a J-K flip-flop mean level triggered.
Whereas the presence of triangle symbol implies that the flip-flop is edge-triggered.
14. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is
_____________
a) Constantly LOW
b) Constantly HIGH
c) A 20 kHz square wave
d) A 10 kHz square wave
View Answer
Answer: d
Explanation: As one flip flop is used so there are two states available. So, 20/2 = 10Hz
frequency is available at the output.
15. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when
________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
View Answer
Answer: c
Explanation: Edge triggered device will follow the input condition when there is a transition.
It is said to be positive edge triggered when transition occurs from LOW to HIGH. While it is
said to be a negative edge triggered when a transition occurs from HIGH to LOW.
1. The asynchronous input can be used to set the flip-flop to the ____________
a) 1 state
b) 0 state
c) either 1 or 0 state
d) forbidden State
View Answer
Answer: c
Explanation: The asynchronous input can be used to set the flip-flop to the 1 state or clear the
flip-flop to the 0 state at any time, regardless of the condition at the other inputs.
2. Input clock of RS flip-flop is given to ____________
a) Input
b) Pulser
c) Output
d) Master slave flip-flop
View Answer
Answer: b
Explanation: Pulser behaves like an arithmetic operator, to perform the operation or
determination of corresponding states.
3. D flip-flop is a circuit having ____________
a) 2 NAND gates
b) 3 NAND gates
c) 4 NAND gates
d) 5 NAND gates
View Answer
Answer: c
Explanation: D flip-flop is a circuit having 4 NAND gates. Two of them are connected with
each other.
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4. In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will
oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q
is uncertain. The situation is referred to as?
a) Conversion condition
b) Race around condition
c) Lock out state
d) Forbidden State
View Answer
Answer: b
Explanation: A race around condition is a flaw in an electronic system or process whereby
the output and result of the process is unexpectedly dependent on the sequence or timing of
other events.
5. Master slave flip flop is also referred to as?
a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
View Answer
Answer: b
Explanation: The term pulse triggered means the data is entered on the rising edge of the
clock pulse, but the output does not reflect the change until the falling edge of the clock
pulse.
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6. In a positive edge triggered JK flip flop, a low J and low K produces?
a) High state
b) Low state
c) Toggle state
d) No Change State
View Answer
Answer: d
Explanation: In JK Flip Flop if J = K = 0 then it holds its current state. There will be no
change.
7. If one wants to design a binary counter, the preferred type of flip-flop is ____________
a) D type
b) S-R type
c) Latch
d) J-K type
View Answer
Answer: d
Explanation: If one wants to design a binary counter, the preferred type of flip-flop is J-K
type because it has capability to recover from toggle condition. SR flip-flop is not suitable as
it produces the “Invalid State”.
8. S-R type flip-flop can be converted into D type flip-flop if S is connected to R through
____________
a) OR Gate
b) AND Gate
c) Inverter
d) Full Adder
View Answer
Answer: c
Explanation: S-R type flip-flop can be converted into D type flip-flop if S is connected to R
through an Inverter gate.
9. Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
View Answer
Answer: a
Explanation: T flip-flop is free from the race around condition because its output depends
only on the input; hence there is no any problem creates as like toggle.
10. Which of the following is the Universal Flip-flop?
a) S-R flip-flop
b) J-K flip-flop
c) Master slave flip-flop
d) D Flip-flop
View Answer
Answer: b
Explanation: There are lots of flip-flops can be prepared by using J-K flip-flop. So, the name
is a universal flip-flop. Also, the JK flip-flop resolves the Forbidden State.
11. How many types of triggering take place in a flip flops?
a) 3
b) 2
c) 4
d) 5
View Answer
Answer: a
Explanation: There are three types of triggering in a flip-flop, viz., level triggering, edge
triggering and pulse triggering.
12. Flip-flops are ____________
a) Stable devices
b) Astable devices
c) Bistable devices
d) Monostable devices
View Answer
Answer: c
Explanation: Flip-flops are synchronous bistable devices known as bistable multivibrators as
they have 2 stable states.
13. The term synchronous means ____________
a) The output changes state only when any of the input is triggered
b) The output changes state only when the clock input is triggered
c) The output changes state only when the input is reversed
d) The output changes state only when the input follows it
View Answer
Answer: b
Explanation: The term synchronous means the output changes state only when the clock input
is triggered. That is, changes in the output occur in synchronization with the clock.
14. The S-R, J-K and D inputs are called ____________
a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
View Answer
Answer: b
Explanation: The S-R, J-K and D inputs are called synchronous inputs because data on these
inputs are transferred to the flip-flop’s output only on the triggering edge or level triggering
of the clock pulse. Moreover, flip-flops have a clock input whereas latches don’t. Hence,
known as synchronous inputs.
15. The circuit that generates a spike in response to a momentary change of input signal is
called ____________
a) R-C differentiator circuit
b) L-R differentiator circuit
c) R-C integrator circuit
d) L-R integrator circuit
View Answer
Answer: a
Explanation: The circuit that generates a spike in response to a momentary change of input
signal is called R-C differentiator circuit.

1. To realise one flip-flop using another flip-flop along with a combinational circuit, known
as ____________
a) PREVIOUS state decoder
b) NEXT state decoder
c) MIDDLE state decoder
d) PRESENT state decoder
View Answer
Answer: b
Explanation: To realise one flip-flop using another flip-flop along with a combinational
circuit, known as NEXT state decoder which acts as like a flip-flop.
2. For realisation of JK flip-flop from SR flip-flop, the input J and K will be given as
___________
a) External inputs to S and R
b) Internal inputs to S and R
c) External inputs to combinational circuit
d) Internal inputs to combinational circuit
View Answer
Answer: a
Explanation: If a JK Flip Flop is required, the inputs are given to the combinational circuit
and the output of the combinational circuit is connected to the inputs of the actual flip flop.
So, J and K will be given as external inputs to S and R. As SR flip-flop have invalid state and
JK flip-flop don’t.
3. For realisation of JK flip-flop from SR flip-flop, if J=0 & K=0 then the input is
___________
a) S=0, R=0
b) S=0, R=X
c) S=X, R=0
d) S=X, R=X
View Answer
Answer: b
Explanation: If J=0 & K=0, the output will be as: Q(n)=0, Q(n+1)=0 and it is fed into both
the AND gates which results as S=0 & R=X(i.e. don’t care).

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4. For realisation of JK flip-flop from SR flip-flop, if J=1, K=0 & present state is 0(i.e.
Q(n)=0) then excitation input will be ___________
a) S=0, R=1
b) S=X, R=0
c) S=1, R=0
d) S=1, R=1
View Answer
Answer: c
Explanation: If J=1, K=0 & present state is 0(i.e. Q(n)=0) then next state will be 1 which
results excitation inputs as S=1 & R=0.

5. For realisation of SR flip-flop from JK flip-flop, the excitation input will be obtained from
___________
a) S and R
b) R input
c) J and K input
d) D input
View Answer
Answer: c
Explanation: It is the reverse process of SR flip-flop to JK flip-flop. So, for realisation of SR
flip-flop from JK flip-flop, the excitation input will be obtained from J and K.
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6. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then next
state will be ___________
a) 1
b) 0
c) Don’t care
d) Toggle
View Answer
Answer: a
Explanation: For JK flip-flop to SR flip-flop, if S=1, R=0 & present state is 0 then next state
will be 1 because next stage is complement of present stage.

7. For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0 then the
excitation input will be ___________
a) J=1, K=1
b) J=X, K=1
c) J=1, K=X
d) J=0, K=0
View Answer
Answer: c
Explanation: For realisation of SR flip-flop from JK flip-flop, if S=1, R=0 & present state is 0
then the excitation input will be J=1, K=X.

8. The K-map simplification for realisation of SR flip-flop from JK flip-flop is ___________

a) J=1, K=0
b) J=R, K=S
c) J=S, K=R
d) J=0, K=1
View Answer
Answer: c
Explanation: The K-map simplification for realisation of SR flip-flop from JK flip-flop is
given by: J=S, K=R.
9. For realisation of D flip-flop from SR flip-flop, the external input is given through
___________
a) S
b) R
c) D
d) Both S and R
View Answer
Answer: c
Explanation: For realisation of D flip-flop from SR flip-flop, S and R are the actual inputs of
the flip flop which is connected together via NOT gate and it is called external input as D.
10. For D flip-flop to JK flip-flop, the characteristics equation is given by ___________
a) D=JQ(p)’+Q(p)K’
b) D=JQ(p)’+KQ(p)’
c) D=JQ(p)+Q(p)K’
d) D=J’Q(p)+Q(p)K
View Answer
Answer: a
Explanation: A characteristic equation is needed when a specific gate requires a specific
output in order to satisfy the truth table. For D flip-flop to JK flip-flop, the characteristics
equation is given by D=JQ(p)’+Q(p)K’.

Counters
1. In digital logic, a counter is a device which ____________
a) Counts the number of outputs
b) Stores the number of times a particular event or process has occurred
c) Stores the number of times a clock pulse rises and falls
d) Counts the number of inputs
View Answer
Answer: b
Explanation: In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has occurred, often in
relationship to a clock signal.
2. A counter circuit is usually constructed of ____________
a) A number of latches connected in cascade form
b) A number of NAND gates connected in cascade form
c) A number of flip-flops connected in cascade
d) A number of NOR gates connected in cascade form
View Answer
Answer: c
Explanation: A counter circuit is usually constructed of a number of flip-flops connected in
cascade. Preferably, JK Flip-flops are used to construct counters and registers.

3. What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a) 0 to 2n
b) 0 to 2n + 1
c) 0 to 2n – 1
d) 0 to 2n+1/2
View Answer
Answer: c
Explanation: The maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops is 0 to 2n-1. For say, there is a 2-bit counter, then it will
count till 22-1 = 3. Thus, it will count from 0 to 3.
4. How many types of the counter are there?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: b
Explanation: Counters are of 3 types, namely, (i)asynchronous/synchronous, (ii)single and
multi-mode & (iii)modulus counter. These further can be subdivided into Ring Counter,
Johnson Counter, Cascade Counter, Up/Down Counter and such like.
5. A decimal counter has ______ states.
a) 5
b) 10
c) 15
d) 20
View Answer
Answer: b
Explanation: Decimal counter is also known as 10 stage counter. So, it has 10 states. It is also
known as Decade Counter counting from 0 to 9.
6. Ripple counters are also called ____________
a) SSI counters
b) Asynchronous counters
c) Synchronous counters
d) VLSI counters
View Answer
Answer: b
Explanation: Ripple counters are also called asynchronous counter. In Asynchronous
counters, only the first flip-flop is connected to an external clock while the rest of the flip-
flops have their preceding flip-flop output as clock to them.
7. Synchronous counter is a type of ____________
a) SSI counters
b) LSI counters
c) MSI counters
d) VLSI counters
View Answer
Answer: c
Explanation: Synchronous Counter is a Medium Scale Integrated (MSI). In Synchronous
Counters, the clock pulse is supplied to all the flip-flops simultaneously.

8. Three decade counter would have ____________

a) 2 BCD counters
b) 3 BCD counters
c) 4 BCD counters
d) 5 BCD counters
View Answer
Answer: b
Explanation: Three decade counter has 30 states and a BCD counter has 10 states. So, it
would require 3 BCD counters. Thus, a three decade counter will count from 0 to 29.
9. BCD counter is also known as ____________
a) Parallel counter
b) Decade counter
c) Synchronous counter
d) VLSI counter
View Answer
Answer: b
Explanation: BCD counter is also known as decade counter because both have the same
number of stages and both count from 0 to 9.
10. The parallel outputs of a counter circuit represent the _____________
a) Parallel data word
b) Clock frequency
c) Counter modulus
d) Clock count
View Answer
Answer: d
Explanation: The parallel outputs of a counter circuit represent the clock count. A counter
counts the number of times an event takes place in accordance to the clock pulse.
1. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
View Answer
Answer: c
Explanation: In an n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
2. A ripple counter’s speed is limited by the propagation delay of _____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series
of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is
composed of FF only and no gates are there other than FF, so only propagation delay of FF
will be taken into account. Propagation delay refers to the amount of time taken in producing
an output when the input is altered.
3. One of the major drawbacks to the use of asynchronous counters is that ____________
a) Low-frequency applications are limited because of internal propagation delays
b) High-frequency applications are limited because of internal propagation delays
c) Asynchronous counters do not have major drawbacks and are suitable for use in high- and
low-frequency counting applications
d) Asynchronous counters do not have propagation delays, which limits their use in high-
frequency applications
View Answer
Answer: b
Explanation: One of the major drawbacks to the use of asynchronous counters is that High-
frequency applications are limited because of internal propagation delays. Propagation delay
refers to the amount of time taken in producing an output when the input is altered.
4. Internal propagation delay of asynchronous counter is removed by ____________
a) Ripple counter
b) Ring counter
c) Modulus counter
d) Synchronous counter
View Answer
Answer: d
Explanation: Propagation delay refers to the amount of time taken in producing an output
when the input is altered. Internal propagation delay of asynchronous counter is removed by
synchronous counter because clock input is given to each flip-flop individually in
synchronous counter.
5. What happens to the parallel output word in an asynchronous binary down counter
whenever a clock pulse occurs?
a) The output increases by 1
b) The output decreases by 1
c) The output word increases by 2
d) The output word decreases by 2
View Answer
Answer: b
Explanation: In an asynchronous counter, there isn’t any clock input. The output of 1 st flip-
flop is given to second flip-flop as clock input. So, in case of binary down counter the output
word decreases by 1.

6. How many flip-flops are required to construct a decade counter?

a) 4
b) 8
c) 5
d) 10
View Answer
Answer: a
Explanation: Number of flip-flop required is calculated by this formula: 2(n-1) <= N< = 2n.
24=16and23=8, therefore, 4 flip flops needed.
7. The terminal count of a typical modulus-10 binary counter is ____________
a) 0000
b) 1010
c) 1001
d) 1111
View Answer
Answer: c
Explanation: A binary counter counts or produces the equivalent binary number depending on
the cycles of the clock input. Modulus-10 means count from 0 to 9. So, the terminal count is
9 (1001).
8. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
View Answer
Answer: c
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
9. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(total)) is ____________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
View Answer
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay
in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5
bits = 12ns * 5 = 60ns.
10. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many
transitional states are required?
a) 1
b) 2
c) 8
d) 15
View Answer
Answer: d
Explanation: Transitional state is given by (2n – 1). Since, it’s a 4-bit counter, therefore,
transition states = 24 – 1 = 15. So, total transitional states are 15.
11. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of
____________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
View Answer
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay
in the counter occurs only due to the flip-flops. One bit change is 15 ns, so 4-bit change = 15
* 4 = 60.
12. Three cascaded decade counters will divide the input frequency by ____________
a) 10
b) 20
c) 100
d) 1000
View Answer
Answer: d
Explanation: Decade counter has 10 states. So, three decade counters are cascaded i.e.
10*10*10=1000 states.
13. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series
of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is
composed of FF only and no gates are there other than FF, so only propagation delay of FF
will be taken into account. Propagation delay refers to the amount of time taken in producing
an output when the input is altered.
14. A 4-bit counter has a maximum modulus of ____________
a) 3
b) 6
c) 8
d) 16
View Answer
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 4-bit counter, the total number of states = 24 = 16 states.
15. A principle regarding most display decoders is that when the correct input is present, the
related output will switch ____________
a) HIGH
b) To high impedance
c) To an open
d) LOW
View Answer
Answer: d
Explanation: A principle regarding most display decoders is that when the correct input is
present, the related output will switch LOW. Since it’s an active-low device.
1. Which of the following statements are true?
a) Asynchronous events does not occur at the same time
b) Asynchronous events are controlled by a clock
c) Synchronous events does not need a clock to control them
d) Only asynchronous events need a control clock
View Answer
Answer: a
Explanation: Asynchronous events does not occur at the same time because of propagation
delay and they do need a clock pulse to trigger them. Whereas, synchronous events occur in
presence of clock pulse.
2. A down counter using n-flip-flops count ______________
a) Downward from a maximum count
b) Upward from a minimum count
c) Downward from a minimum to maximum count
d) Toggles between Up and Down count
View Answer
Answer: a
Explanation: As the name suggests down counter means counting occurs from a higher value
to lower value (i.e. (2^n – 1) to 0).
3. UP Counter is ____________
a) It counts in upward manner
b) It count in down ward manner
c) It counts in both the direction
d) Toggles between Up and Down count
View Answer
Answer: a
Explanation: UP counter counts in an upward manner from 0 to (2n – 1).

4. DOWN counter is ____________

a) It counts in upward manner
b) It count in downward manner
c) It counts in both the direction
d) Toggles between Up and Down count
View Answer
Answer: b
Explanation: DOWN counter counts in a downward manner from (2n – 1) to 0.
5. How many different states does a 3-bit asynchronous down counter have?
a) 2
b) 4
c) 6
d) 8
View Answer
Answer: d
Explanation: In a n-bit counter, the total number of states = 2n.
Therefore, in a 3-bit counter, the total number of states = 23 = 8 states.
6. In a down counter, which flip-flop doesn’t toggle when the inverted output of the
preceeding flip-flop goes from HIGH to LOW.
a) MSB flip-flop
b) LSB flip-flop
c) Master slave flip-flop
d) Latch
View Answer
Answer: b
Explanation: Since the LSB flip-flop changes its state at each negative transition of clock.
That is why LSB flip-flop doesn’t have toggle.
7. In a 3-bit asynchronous down counter, the initial content is ____________
a) 000
b) 111
c) 010
d) 101
View Answer
Answer: a
Explanation: Initially, all the flip-flops are RESET. So, the initial content is 000. At the first
negative transition of the clock, the counter content becomes 101.
8. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
View Answer
Answer: b
Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative
transition of the clock, the counter content becomes 111.
9. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the
counter content becomes ____________
a) 000
b) 111
c) 101
d) 010
View Answer
Answer: c
Explanation: Since, in the down counter, the counter content is decremented by 1 for every
negative transition. Hence, in a 3-bit asynchronous down counter, at the first negative
transition of the clock, the counter content becomes 101.
10. The hexadecimal equivalent of 15,536 is ________
a) 3CB0
b) 3C66
c) 63C0
d) 6300
View Answer
Answer: a
Explanation: You just divide the number by 16 at the end and store the remainder from
bottom to top.
11. In order to check the CLR function of a counter ____________
a) Apply the active level to the CLR input and check all of the Q outputs to see if they are all
in their reset state
b) Ground the CLR input and check to be sure that all of the Q outputs are LOW
c) Connect the CLR input to Vcc and check to see if all of the Q outputs are HIGH
d) Connect the CLR to its correct active level while clocking the counter; check to make sure
that all of the Q outputs are toggling
View Answer
Answer: a
Explanation: CLR stands for clearing or resetting all states of flip-flop. In order to check the
CLR function of a counter, apply the active level to the CLR input and check all of the Q
outputs to see if they are all in their reset state.
1. Modulus refers to ____________
a) A method used to fabricate decade counter units
b) The modulus of elasticity, or the ability of a circuit to be stretched from one mode to
another
c) An input on a counter that is used to set the counter state, such as UP/DOWN
d) The maximum number of states in a counter sequence
View Answer
Answer: d
Explanation: Modulus is defined as the maximum number of stages/states a counter has. It is
independent of the number of states the counter will actually traverse.
2. A sequential circuit design is used to ____________
a) Count up
b) Count down
c) Decode an end count
d) Count in a random order
View Answer
Answer: d
Explanation: A sequential circuit design is used to count in a random manner which is faster
than the combinational circuit. It is used for storing data.
3. In general, when using a scope to troubleshoot digital systems, the instrument should be
triggered by ____________
a) The A channel or channel 1
b) The vertical input mode, when using more than one channel
c) The system clock
d) Line sync, in order to observe troublesome power line glitches
View Answer
Answer: c
Explanation: All the information is sent from one end to another end through the clock pulse
which behaves like a carrier. So, for troubleshooting it should be triggered by the same. Since
the system clock is internally produced.

4. Which counters are often used whenever pulses are to be counted and the results displayed
in decimal?
a) Synchronous
b) Bean
c) Decade
d) BCD
View Answer
Answer: d
Explanation: BCD means Binary Coded Decimal, which means that decimal numbers coded
of binary numbers. It displays the decimal equivalent of corresponding binary numbers.
5. The ________ counter in the Altera library has controls that allow it to count up or down,
and perform synchronous parallel load and asynchronous cascading.
a) 74134
b) LPM
c) Synchronous
d) AHDL
View Answer
Answer: b
Explanation: The library of parameterized modules (LPM) counter in the Altera library has
controls that allow it to count up or down, and perform synchronous parallel load and
asynchronous cascading.
6. The minimum number of flip-flops that can be used to construct a modulus-5 counter is
____________
a) 3
b) 8
c) 5
d) 10
View Answer
Answer: a
Explanation: The minimum number of flip-flops used in a counter is given by: 2(n-1)<=N<=2n.
Thus, for modulus-5 counter: 22 <= N <= 23, where N = 5 and n = 3.
7. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is
____________
a) 20%
b) 50%
c) 10%
d) 80%
View Answer
Answer: a
Explanation: There are 10 states, out of which MSB is high only for (1000, 1001) 2 times.
Hence duty cycle is 2/10*100 = 20%. Since the duty cycle is the ratio of on-time to the total
time.

8. Normally, the synchronous counter is designed using ____________

a) S-R flip-flops
b) J-K flip-flops
c) D flip-flops
d) T flip-flops
View Answer
Answer: b
Explanation: Since J-K flip-flops have options of recovery from toggle condition and by
using less number of J-K flip-flops a synchronous counter can be designed. So, it is more
preferred. Also, because JK-flip-flops resolves the problem of Forbidden States.
9. MOD-16 counter requires ________ no. of states.
a) 8
b) 4
c) 16
d) 32
View Answer
Answer: c
Explanation: 2n >= N >= 2(n-1), by using this formula we get the value of N=16 for n=4.
10. What is a state diagram?
a) It provides the graphical representation of states
b) It provides exactly the same information as the state table
c) It is same as the truth table
d) It is similar to the characteristic equation
View Answer
Answer: b
Explanation: The state diagram provides exactly the same information as the state table and is
obtained directly from the state table.
11. High speed counter is ____________
a) Ring counter
b) Ripple counter
c) Synchronous counter
d) Asynchronous counter
View Answer
Answer: c
Explanation: Synchronous counter doesn’t have propagation delay. Propagation delay refers
to the amount of time taken in producing the output when the input is altered.
12. Program counter in a digital computer ____________
a) Counts the number of programs run in the machine
b) Counts the number of times a subroutine
c) Counts the number of time the loops are executed
d) Points the memory address of the current or the next instruction
View Answer
Answer: d
Explanation: Program counter in a digital computer points the memory address of the current
or the next instruction which is to be executed.
13. Fundamental mode is another name for ____________
a) Level operation
b) Pulse operation
c) Clock operation
d) Edge operation
View Answer
Answer: b
Explanation: Whatever the input given to the devices are in the form of pulses always. That is
why it is known as a fundamental mode.
1. A ripple counter’s speed is limited by the propagation delay of ____________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. It’s like a series
of Flip Flops. The output of one FF becomes the input of the next. Because ripple counter is
composed of FF only and no gates are there other than FF, so only propagation delay of FF
will be taken into account. Propagation delay refers to the amount of time taken in producing
an output when the input is altered.
2. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns
propagation delay. The total propagation delay (tp(tot)) is ________
a) 12 ms
b) 24 ns
c) 48 ns
d) 60 ns
View Answer
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay
in the counter occurs only due to the flip-flops. Each bit has propagation delay = 12ns. So, 5
bits = 12ns * 5 = 60ns.
3. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from
clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of
________
a) 15 ns
b) 30 ns
c) 45 ns
d) 60 ns
View Answer
Answer: d
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay
in the counter occurs only due to the flip-flops. Each bit has propagation delay = 15ns. So, 4
bits = 15ns * 4 = 60ns.
4. A ripple counter’s speed is limited by the propagation delay of __________
a) Each flip-flop
b) All flip-flops and gates
c) The flip-flops only with gates
d) Only circuit gates
View Answer
Answer: a
Explanation: A ripple counter is something that is derived by other flip-flops. Its like a series
of Flip Flops. Output of one FF becomes the input of the next. Because ripple counter is
composed of FF only and no gates are there other than FF, so only propagation delay of FF
will be taken into account. Propagation delay refers to the amount of time taken in producing
an output when the input is altered.
5. What is the maximum delay that can occur if four flip-flops are connected as a ripple
counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?
a) 15 ns
b) 22 ns
c) 60 ns
d) 88 ns
View Answer
Answer: d
Explanation: Maximum propagation delay is the longest delay between an input changing
value and the output changing value. Hence, 22 * n = 22*4 (Since there are 4 FFs) = 88ns.
6. The main drawback of a ripple counter is that __________
a) It has a cumulative settling time
b) It has a distributive settling time
c) It has a productive settling time
d) It has an associative settling time
View Answer
Answer: a
Explanation: The main drawback of a ripple counter is that it has a cumulative settling time
(i.e. another bit is transmitted just after one consequently).
7. A 4 bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each flip-
flop is 50 nsec, the maximum clock frequency that can be used is equal to __________
a) 20 MHz
b) 10 MHz
c) 5 MHz
d) 4 MHz
View Answer
Answer: c
Explanation: Since a counter is constructed using flip-flops, therefore, the propagation delay
in the counter occurs only due to the flip-flops. Each bit has propagation delay = 50ns. So, 4
bits or FFs = 50ns * 4 = 200ns. Clock frequency = 1/200ns = 5 MHz.
8. As the number of flip flops are increased, the total propagation delay of __________
a) Ripple counter increases but that of synchronous counter remains the same
b) Both ripple and synchronous counters increase
c) Both ripple and synchronous counters remain the same
d) Ripple counter remains the same but that of synchronous counter increases
View Answer
Answer: a
Explanation: In ripple counter, the clock pulses are applied to one flip-flop only. Hence, as
the number of flip-flops increases the delay increases. In the synchronous counter, clock
pulses to all flip-flops are applied simultaneously.
9. A reliable method for eliminating decoder spikes is the technique called ________
a) Strobing
b) Feeding
c) Wagging
d) Waving
View Answer
Answer: a
Explanation: A reliable method for eliminating decoder spikes is the technique called
strobing. A strobe signal validates the availability of data on consecutive parallel lines.

10. A glitch that appears on the decoded output of a ripple counter is often difficult to see on
an oscilloscope because of __________
a) It is a random event
b) It occurs less frequently than the normal decoded output
c) It is very fast
d) All of the Mentioned
View Answer
Answer: d
Explanation: A glitch is a transition that occurs before a signal settles to a specific value. A
glitch that appears on the decoded output of a ripple counter is often difficult to see on an
oscilloscope because it is a random event and very fast and it occurs less frequently than the
normal decoded output.
11. Assume a 4-bit ripple counter has a failure in the second flip-flop such that it “locks up”.
The third and fourth stages will __________
a) Continue to count with correct outputs
b) Continue to count but have incorrect outputs
c) Stop counting
d) Turn into molten silicon
View Answer
Answer: c
Explanation: The ripple counter would stop counting because next flip-flop’s input depends
on the output of the previous flip-flop.
1. UP-DOWN counter is a combination of ____________
a) Latches
b) Flip-flops
c) UP counter
d) Up counter & down counter
View Answer
Answer: d
Explanation: As the name suggests UP-DOWN, it means that it has up-counter and down-
counter as well. It alternatively counts up and down.
2. UP-DOWN counter is also known as ___________
a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
View Answer
Answer: c
Explanation: UP-DOWN counter is also known as multimode counter because it has
capability of counting upward as well as downwards.
3. In an UP-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
View Answer
Answer: b
Explanation: In an UP-counter, each flip-flop is triggered by the normal output of the
preceding flip-flop. UP-counter counts from 0 to a maximum value.
4. In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
b) The normal output of the preceding flip-flop
c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
View Answer
Answer: d
Explanation: In DOWN-counter, each flip-flop is triggered by the inverted output of the
preceding flip-flop. DOWN-counter counts from a maximum value to 0.
5. Binary counter that count incrementally and decrement is called ___________
a) Up-down counter
b) LSI counters
c) Down counter
d) Up counter
View Answer
Answer: a
Explanation: Binary counter that counts incrementally and decrement is called UP-DOWN
counter/multimode counter. It alternately counts up and down.

6. Once an up-/down-counter begins its count sequence, it ___________

a) Starts counting
b) Can be reversed
c) Can’t be reversed
d) Can be altered
View Answer
Answer: d
Explanation: In up/down ripple counter once the counting begins, we can simply change the
pulse M (mode control) M = 0 or 1 respectively for UP counter or Down counter.
7. In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: An n-bit bit counter requires n number of FFs. In a 4-bit up-down counter, there
are 4 J-K flip-flops required.
8. A modulus-10 counter must have ________
a) 10 flip-flops
b) 4 Flip-flops
c) 2 flip-flops
d) Synchronous clocking
View Answer
Answer: b
Explanation: 2n-1 < = N < = 2n
For modulus-10 counter, N = 10. Therefore, 23 < = 10 < = 24. Thus, n = 4, and therefore, we
require 4 FFs.
9. Which is not an example of a truncated modulus?
a) 8
b) 9
c) 11
d) 15
View Answer
Answer: a
Explanation: An n-bit counter whose modulus is less than the maximum possible is called a
truncated counter. Here, 9, 11 and 15 modulus counters are truncated counters. Whereas,
modulus-8 is not a truncated counter.
10. The designation means that the ________
a) Up count is active-HIGH, the down count is active-LOW
b) Up count is active-LOW, the down count is active-HIGH
c) Up and down counts are both active-LOW
d) Up and down counts are both active-HIGH
View Answer
Answer: a
Explanation: The designation means that the up count is active-HIGH, the down count is
active-LOW. Active-High means that up-count would be triggered when clock is 1 else when
clock is 0, down-count would be triggered, which is referred to as Active-low.
11. An asynchronous binary up counter, made from a series of leading edge-triggered flip-
flops, can be changed to a down counter by ________
a) Taking the output on the other side of the flip-flops (instead of Q)
b) Clocking of each succeeding flip-flop from the other side (instead of Q)
c) Changing the flip-flops to trailing edge triggering
d) All of the Mentioned
View Answer
Answer: d
Explanation: By all of the mentioned ideas, an asynchronous binary up counter, made from a
series of leading edge-triggered flip-flops, can be changed to a down counter. Edge-triggered
FFs refer to FFs being triggered during a clock transition from LOW to HIGH or HIGH to
LOW.
12. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of the
most significant bit is ________
a) 1.25 kHz
b) 2.50 kHz
c) 160 kHz
d) 320 kHz
View Answer
Answer: a
Explanation: Input clock is given by 20/2 kHz. So, count on the basis of 10 kHz clock. And
MSB changes on 8th stage; Hence, f = 10/8 = 1.25 kHz.

Registers

1. A register is defined as ___________

a) The group of latches for storing one bit of information
b) The group of latches for storing n-bit of information
c) The group of flip-flops suitable for storing one bit of information
d) The group of flip-flops suitable for storing binary information
View Answer
Answer: d
Explanation: A register is defined as the group of flip-flops suitable for storing binary
information. Each flip-flop is a binary cell capable of storing one bit of information. The data
in a register can be transferred from one flip-flop to another.
2. The register is a type of ___________
a) Sequential circuit
b) Combinational circuit
c) CPU
d) Latches
View Answer
Answer: a
Explanation: Register’s output depends on the past and present states of the inputs. The
device which follows these properties is termed as a sequential circuit. Whereas,
combinational circuits only depend on the present values of inputs.
3. How many types of registers are?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: There are 4 types of shift registers, viz., Serial-In/Serial-Out, Serial-In/Parallel-
Out, Parallel-In/Serial-Out and Parallel-In/Parallel-Out.
4. The main difference between a register and a counter is ___________
a) A register has no specific sequence of states
b) A counter has no specific sequence of states
c) A register has capability to store one bit of information but counter has n-bit
d) A register counts data
View Answer
Answer: a
Explanation: The main difference between a register and a counter is that a register has no
specific sequence of states except in certain specialised applications.

5. In D register, ‘D’ stands for ___________

a) Delay
b) Decrement
c) Data
d) Decay
View Answer
Answer: c
Explanation: D stands for “data” in case of flip-flops and not delay. Registers are made of a
group of flip-flops.
6. Registers capable of shifting in one direction is ___________
a) Universal shift register
b) Unidirectional shift register
c) Unipolar shift register
d) Unique shift register
View Answer
Answer: b
Explanation: The register capable of shifting in one direction is unidirectional shift register.
The register capable of shifting in both directions is known as a bidirectional shift register.
7. A register that is used to store binary information is called ___________
a) Data register
b) Binary register
c) Shift register
d) D – Register
View Answer
Answer: b
Explanation: A register that is used to store binary information is called a binary register. A
register in which data can be shifted is called shift register.

8. A shift register is defined as ___________

a) The register capable of shifting information to another register
b) The register capable of shifting information either to the right or to the left
c) The register capable of shifting information to the right only
d) The register capable of shifting information to the left only
View Answer
Answer: b
Explanation: The register capable of shifting information either to the right or to the left is
termed as shift register. A register in which data can be shifted only in one direction is called
unidirectional shift register, while if data can shifted in both directions, it is known as a
bidirectional shift register.
9. How many methods of shifting of data are available?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: a
Explanation: There are two types of shifting of data are available and these are serial shifting
& parallel shifting.

10. In serial shifting method, data shifting occurs ____________

a) One bit at a time
b) simultaneously
c) Two bit at a time
d) Four bit at a time
View Answer
Answer: a
Explanation: As the name suggests serial shifting, it means that data shifting will take place
one bit at a time for each clock pulse in a serial fashion. While in parallel shifting, shifting
will take place with all bits simultaneously for each clock pulse in a parallel fashion.

1. Based on how binary information is entered or shifted out, shift registers are classified into
_______ categories.
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: c
Explanation: The registers in which data can be shifted serially or parallelly are known as
shift registers. Based on how binary information is entered or shifted out, shift registers are
classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO),
Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).
2. The full form of SIPO is ___________
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
View Answer
Answer: a
Explanation: SIPO is always known as Serial-in Parallel-out.
3. A shift register that will accept a parallel input or a bidirectional serial load and internal
shift features is called as?
a) Tristate
b) End around
c) Universal
d) Conversion
View Answer
Answer: c
Explanation: A shift register can shift it’s data either left or right. The universal shift register
is capable of shifting data left, right and parallel load capabilities.
4. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
View Answer
Answer: d
Explanation: Because no other flip-flops are connected with the output Q, therefore one can
use the Q out of each FF to take out parallel data.
5. What is meant by the parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
View Answer
Answer: a
Explanation: At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus
input is definitely 1.
6. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output
shift register with an initial state 01110. After three clock pulses, the register contains
________
a) 01110
b) 00001
c) 00101
d) 00110
View Answer
Answer: c
Explanation: LSB bit is inverted and feed back to MSB:
01110->initial
10111->first clock pulse
01011->second
00101->third.
7. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
a) 1100
b) 0011
c) 0000
d) 1111
View Answer
Answer: c
Explanation: In Serial-In/Serial-Out shift register, data will be shifted one at a time with
every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1st clock
11 | 0000 2nd clock.
8. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is
waiting to enter. After four clock pulses, the register contains ________
a) 0000
b) 1111
c) 0111
d) 1000
View Answer
Answer: c
Explanation: In Serial-In/Parallel-Out shift register, data will be shifted all at a time with
every clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1st clk
01 | 1100 2nd clk
0 | 1110 3rd clk
X | 1111 4th clk.
9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in
________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
View Answer
Answer: b
Explanation: f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be
loaded = 8 * 5 = 40 micro-sec.
10. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to
achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us
View Answer
Answer: c
Explanation: One clock period is = (1⁄2) micro-s = 0.5 microseconds. In serial transmission,
data enters one bit at a time. So, the total delay = 0.5*8 = 4 micro seconds time is required to
transmit information of 8 bits.
1. A sequence of equally spaced timing pulses may be easily generated by which type of
counter circuit?
a) Ring shift
b) Clock
c) Johnson
d) Binary
View Answer
Answer: a
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s
input. Thus, it generates equally spaced timing pulses.
2. A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble
1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift
register is storing ________
a) 1101
b) 0111
c) 0001
d) 1110
View Answer
Answer: b
Explanation: Mode is high means it’s a right shift register. Then after 3 clock pulses enter bits
are 011 and remained bit in register is 1. Therefore, 0111 is the required solution.
1011 | 1101
101 | 1110 -> 1st clock pulse
10 | 1111 -> 2nd clock pulse
1 | 0111 -> 3rd clock pulse.
3. To operate correctly, starting a ring shift counter requires __________
a) Clearing all the flip-flops
b) Presetting one flip-flop and clearing all others
c) Clearing one flip-flop and presetting all others
d) Presetting all the flip-flops
View Answer
Answer: b
Explanation: In Ring counter, the feedback of the output of the FF is fed to the same FF’s
input. To operate correctly, starting a ring shift counter requires presetting one flip-flop and
clearing all others so that it can shift to the next bit.
4. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by
________ position for each clock pulse.
a) Right, one
b) Right, two
c) Left, one
d) Left, three
View Answer
Answer: a
Explanation: If register shifts towards left then it shift by a bit to the left and if register shifts
right then it shift to the right by one bit. Since, it receives parallel data, then by default, it will
shift to right by one position.
5. How many clock pulses will be required to completely load serially a 5-bit shift register?
a) 2
b) 3
c) 4
d) 5
View Answer
Answer: d
Explanation: A register is a collection of FFS. To load a bit, we require 1 clock pulse for 1
shift register. So, for 5-bit shift register we would require of 5 clock pulses.
6. How is a strobe signal used when serially loading a shift register?
a) To turn the register on and off
b) To control the number of clocks
c) To determine which output Qs are used
d) To determine the FFs that will be used
View Answer
Answer: b
Explanation: A strobe is used to validate the availability of data on the data line. It (an
auxiliary signal used to help synchronize the real data in an electrical bus when the bus
components have no common clock) signal is used to control the number of clocks during
serially loading a shift register.
7. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What
is the time delay between the serial input and the Q3 output?
a) 1.67 s
b) 26.67 s
c) 26.7 ms
d) 267 ms
View Answer
Answer: b
Explanation: In serial-sifting, one bit of data is shifted one at a time. From Q0 to Q3 total of 4
bit shifting takes place. Therefore, 4/150kHz = 26.67 microseconds.
8. What are the three output conditions of a three-state buffer?
a) HIGH, LOW, float
b) High-Z, 0, float
c) Negative, positive, 0
d) 1, Low-Z, float
View Answer
Answer: a
Explanation: Three conditions of a three-state buffer are HIGH, LOW & float.
9. The primary purpose of a three-state buffer is usually ____________
a) To provide isolation between the input device and the data bus
b) To provide the sink or source current required by any device connected to its output
without loading down the output device
c) Temporary data storage
d) To control data flow
View Answer
Answer: a
Explanation: The primary purpose of a three-state buffer is usually to provide isolation
between the input device or peripheral devices and the data bus. Three conditions of a three-
state buffer are HIGH, LOW & float.

10. What is the difference between a ring shift counter and a Johnson shift counter?
a) There is no difference
b) A ring is faster
c) The feedback is reversed
d) The Johnson is faster
View Answer
Answer: c
Explanation: A ring counter is a shift register (a cascade connection of flip-flops) with the
output of the last one connected to the input of the first, that is, in a ring. Whereas, a Johnson
counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius
counter) is a modified ring counter, where the output from the last stage is inverted and fed
back as input to the first stage.
1. What is a recirculating register?
a) Serial out connected to serial in
b) All Q outputs connected together
c) A register that can be used over again
d) Parallel out connected to Parallel in
View Answer
Answer: a
Explanation: A recirculating register is a register whose serial output is connected to the
serial input in a circulated manner.

2. When is it important to use a three-state buffer?

a) When two or more outputs are connected to the same input
b) When all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs
View Answer
Answer: a
Explanation: When two or more outputs are connected to the same input, in such situation we
use of tristate buffer always because it has the capability to take upto three inputs. A buffer is
a circuit where the output follows the input.
3. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble
0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift
register is storing ________
a) 1110
b) 0111
c) 1000
d) 1001
View Answer
Answer: d
Explanation: Given,
Stored nibble | waiting nibble

0111 | 1110, Initially

111 | 1100, 1st pulse

11 | 1001, 2nd pulse.

4. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three
clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
View Answer
Answer: b
Explanation: Parallel in parallel out gives the same output as input. Thus, after three clock
pulses, the data outputs are 0001.
5. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel
output shift register with an initial state 11110000. After two clock pulses, the register
contains ______________
a) 10111000
b) 10110111
c) 11110000
d) 11111100
View Answer
Answer: d
Explanation: After first clock pulse, the register contains 11111000. After second clock pulse,
the register would contain 11111100. Since the bits are shifted to the right at every clock
pulse.
6. By adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a
________ ________ and ________ out register.
a) Parallel-in, serial, parallel
b) Serial-in, parallel, serial
c) Series-parallel-in, series, parallel
d) Bidirectional in, parallel, series
View Answer
Answer: a
Explanation: One bit shifting takes place just after the output obtained on every register.
Hence, by adding recirculating lines to a 4-bit parallel-in serial-out shift register, it becomes a
Parallel-in, Serial, and Parallel-out register. Since, the bots can be inputted all at the same
time, while the data can be outputted either one at a time or simultaneously.
7. What type of register would have a complete binary number shifted in one bit at a time and
have all the stored bits shifted out one at a time?
a) Parallel-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-in Parallel-out
View Answer
Answer: c
Explanation: Serial-in Serial-out register would have a complete binary number shifted in one
bit at a time and have all the stored bits shifted out one at a time. Since in serial transmission,
bits are transmitted or received one at a time and not simultaneously.

8. In a 4-bit Johnson counter sequence, there are a total of how many states or bit patterns?
a) 1
b) 3
c) 4
d) 8
View Answer
Answer: d
Explanation: In johnson counter, total number of states are determined by 2 N = 2*4 = 16
Total Number of Used states = 2N = 2*4 = 8
Total Number of Unused states = 16 – 8 = 8.

9. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second
clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
View Answer
Answer: b
Explanation: After shifting 2-bit we get the output as 0011010000 (Since two zeros are at
1st position and 2nd position which came from the last two bits). As in a ring counter, the bits
rotate in clockwise direction.
10. How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits
View Answer
Answer: a
Explanation: A register is made of flip-flops. And each flip-flop stores 1 bit of data. Thus, a
shift register has the capability to store one bit and if another bit is to store, in such a situation
it deletes the previous data and stores them.
1. Ring shift and Johnson counters are ____________
a) Synchronous counters
b) Asynchronous counters
c) True binary counters
d) Synchronous and true binary counters
View Answer
Answer: a
Explanation: Synchronous counters are the counters being triggered in the presence of a clock
pulse. Since all of the clock inputs are connected through a single clock pulse in ring shift and
johnson counters. So, both are synchronous counters.

2. What is the difference between a shift-right register and a shift-left register?

a) There is no difference
b) The direction of the shift
c) Propagation delay
d) The clock input
View Answer
Answer: b
Explanation: In shift-right register, shifting of bit takes place towards the right and towards
left for shift-left register. Thus, both the registers vary in the shifting of their direction.
3. What is a transceiver circuit?
a) A buffer that transfers data from input to output
b) A buffer that transfers data from output to input
c) A buffer that can operate in both directions
d) A buffer that can operate in one direction
View Answer
Answer: c
Explanation: A transceiver circuit is a buffer that can operate in both directions right as well
as left.
4. A 74HC195 4-bit parallel access shift register can be used for ____________
a) Serial in/serial out operation
b) Serial in/parallel out operation
c) Parallel in/serial out operation
d) All of the Mentioned
View Answer
Answer: d
Explanation: 74HC195 is an IC, which can be used for all of the given operations, as well as
for, parallel-in/parallel-out.
5. Which type of device may be used to interface a parallel data format with external
equipment’s serial format?
a) UART
b) Key matrix
c) Memory chip
d) Series in Parallel out
View Answer
Answer: a
Explanation: UART means Universal Asynchronous Receiver/Transmitter which converts the
bytes it receives from the computer along parallel circuits into a single serial bit stream for
outbound transmission. And also receives data in serial form and converts it into parallel
form and sent to the processor.
6. What is the function of a buffer circuit?
a) To provide an output that is inverted from that on the input
b) To provide an output that is equal to its input
c) To clean up the input
d) To clean up the output
View Answer
Answer: b
Explanation: The function of a buffer circuit is to provide an output that is equal to its input.
A transceiver circuit is a buffer that can operate in both directions right as well as left.
7. What is the preset condition for a ring shift counter?
a) All FFs set to 1
b) All FFs cleared to 0
c) A single 0, the rest 1
d) A single 1, the rest 0
View Answer
Answer: d
Explanation: A ring shift counter is a counter in which the output of one FF connected to the
input of the adjacent FF. In preset condition, all of the bits are 0 except first one.
8. Which is not characteristic of a shift register?
a) Serial in/parallel in
b) Serial in/parallel out
c) Parallel in/serial out
d) Parallel in/parallel out
View Answer
Answer: a
Explanation: There is no such type of register present who doesn’t have output end. Thus,
Serial in/Parallel in is not a characteristic of a shift register. There has to be an output, be it
serial or parallel.
9. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a
____________
a) Divide-by-4 clock pulse
b) Sequence generator
c) Strobe line
d) Multiplexer
View Answer
Answer: c
Explanation: In computer or memory technology, a strobe is a signal that is sent that validates
data or other signals on adjacent parallel lines. Thus, in registers the strobe line is there to
check the availability of data.
10. Another way to connect devices to a shared data bus is to use a ____________
a) Circulating gate
b) Transceiver
c) Bidirectional encoder
d) Strobed latch
View Answer
Answer: b
Explanation: A transceiver is a device comprising both a transmitter and a receiver which are
combined and share common circuitry or a single housing. When no circuitry is common
between transmit and receive functions, the device is a transmitter-receiver.