SN54LVTH245A, SN74LVTH245A

3.3-V ABT OCTAL BUS TRANSCEIVERS

WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

D Support Mixed-Mode Signal Operation (5-V D Bus Hold on Data Inputs Eliminates the
Input and Output Voltages With 3.3-V VCC) Need for External Pullup/Pulldown
D Typical VOLP (Output Ground Bounce) Resistors
<0.8 V at VCC = 3.3 V, TA = 25°C D Latch-Up Performance Exceeds 500 mA Per
D Support Unregulated Battery Operation JESD 17
Down to 2.7 V D ESD Protection Exceeds JESD 22
D Ioff and Power-Up 3-State Support Hot − 2000-V Human-Body Model (A114-A)
Insertion − 200-V Machine Model (A115-A)

SN54LVTH245A . . . J OR W PACKAGE SN74LVTH245A . . . RGY PACKAGE SN54LVTH245A . . . FK PACKAGE

SN74LVTH245A . . . DB, DW, NS, (TOP VIEW) (TOP VIEW)
OR PW PACKAGE

VCC
VCC
DIR

DIR

OE
(TOP VIEW)

A2
A1
DIR 1 20 VCC 1 20
3 2 1 20 19
A1 2 19 OE A1 2 19 OE A3 4 18 B1
A2 3 18 B1 A2 3 18 B1 A4 5 17 B2
A3 4 17 B2 A3 4 17 B2 A5 6 16 B3
A4 5 16 B3 A4 5 16 B3 A6 7 15 B4
A5 6 15 B4 A5 6 15 B4 A7 8 14 B5
9 10 11 12 13
A6 7 14 B5 A6 7 14 B5
A7 8 13 B6

A8

B8
B7
B6
GND
A7 8 13 B6
A8 9 12 B7 A8 9 12 B7
GND 10 11 B8 10 11
GND

B8

description/ordering information
These octal bus transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.

ORDERING INFORMATION
ORDERABLE
TA PACKAGE† TOP-SIDE MARKING
PART NUMBER
QFN − RGY Tape and reel SN74LVTH245ARGYR LXH245A
Tube SN74LVTH245ADW
SOIC − DW LVTH245A
Tape and reel SN74LVTH245ADWR
SOP − NS Tape and reel SN74LVTH245ANSR LVTH245A
−40°C
40 C to 85°C
85 C SSOP − DB Tape and reel SN74LVTH245ADBR LXH245A
Tube SN74LVTH245APW
TSSOP − PW LXH245A
Tape and reel SN74LVTH245APWR
VFBGA − GQN SN74LVTH245AGQNR
Tape and reel LXH245A
VFBGA − ZQN (Pb-free) SN74LVTH245AZQNR
CDIP − J Tube SNJ54LVTH245AJ SNJ54LVTH245AJ
−55°C to 125°C CFP − W Tube SNJ54LVTH245AW SNJ54LVTH245AW
LCCC − FK Tube SNJ54LVTH245AFK SNJ54LVTH245AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

description/ordering information (continued)

These devices are designed for asynchronous communication between data buses. They transmit data from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
SN74LVTH245A . . . GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1 2 3 4
1 2 3 4
A A A1 DIR VCC OE
B B A3 B2 A2 B1
C C A5 A4 B4 B3

D D A7 B6 A6 B5

E E GND A8 B8 B7

FUNCTION TABLE
INPUTS
OPERATION
OE DIR
L L B data to A bus
L H A data to B bus
H X Isolation

logic diagram (positive logic)

1
DIR

19
OE

2
A1

18
B1

To Seven Other Channels

Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO: SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2): SN54LVTH245A . . . . . . . . . . . . . . . . . . . . . . 48 mA
SN74LVTH245A . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 5)

SN54LVTH245A SN74LVTH245A
UNIT
MIN MAX MIN MAX
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
Δt/Δv Input transition rise or fall rate Outputs enabled 10 10 ns/V
Δt/ΔVCC Power-up ramp rate 200 200 μs/V
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LVTH245A SN74LVTH245A
PARAMETER TEST CONDITIONS UNIT
MIN TYP† MAX MIN TYP† MAX
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = 2.7 V to 3.6 V, IOH = −100 μA VCC−0.2 VCC−0.2
VCC = 2.7 V, IOH = −8 mA 2.4 2.4
VOH V
IOH = −24 mA 2
VCC = 3 V
IOH = −32 mA 2
IOL = 100 μA 0.2 0.2
VCC = 2
2.7
7V
IOL = 24 mA 0.5 0.5
IOL = 16 mA 0.4 0.4
VOL V
IOL = 32 mA 0.5 0.5
VCC = 3 V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 3.6 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
II VI = 5.5 V 20 20 μA
A or B ports‡ VCC = 3.6 V VI = VCC 1 1
VI = 0 −5 −5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 μA
VI = 0.8 V 75 75
VCC = 3 V
VI = 2 V −75 −75
II(hold)
I(h ld) A or B ports μA
500
VCC = 3.6 V§, VI = 0 to 3.6 V
−750
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
IOZPU ±100∗ ±100 μA
OE = don’t care
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
IOZPD ±100∗ ±100 μA
OE = don’t care

VCC = 3.6 V, Outputs high 0.19 0.19

ICC IO = 0, Outputs low 5 5 mA
VI = VCC or GND Outputs disabled 0.19 0.19
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
ΔICC¶ 0.2 0.2 mA
Other inputs at VCC or GND
Ci VI = 3 V or 0 4 4 pF
Cio VO = 3 V or 0 9 9 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ Unused terminals are at V
CC or GND.
§ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
CC or GND.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
SN54LVTH245A SN74LVTH245A
FROM TO VCC = 3.3 V VCC = 3.3 V
PARAMETER VCC = 2.7 V VCC = 2.7 V UNIT
(INPUT) (OUTPUT) ± 0.3 V ± 0.3 V
MIN MAX MIN MAX MIN TYP† MAX MIN MAX
tPLH 0.7 3.7 4.2 1.2 2.3 3.5 4
A or B B or A ns
tPHL 0.7 3.7 4.2 1.2 2.1 3.5 4
tPZH 1.2 5.7 7.4 1.3 3.2 5.5 7.1
OE A or B ns
tPZL 1.6 5.7 6.8 1.7 3.4 5.5 6.5
tPHZ 1.8 6.2 6.8 2.2 3.5 5.9 6.5
OE A or B ns
tPLZ 1.8 5.3 5.5 2.2 3.4 5 5.1
† All typical values are at VCC = 3.3 V, TA = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54LVTH245A, SN74LVTH245A
3.3-V ABT OCTAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS130T − MAY 1992 − REVISED SEPTEMBER 2003

PARAMETER MEASUREMENT INFORMATION

6V
TEST S1
From Output 500 Ω S1 Open
tPLH/tPHL Open
Under Test GND tPLZ/tPZL 6V
CL = 50 pF tPHZ/tPZH GND
(see Note A) 500 Ω

2.7 V
LOAD CIRCUIT Timing Input 1.5 V
0V
tw
tsu th
2.7 V
2.7 V
Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V
0V 0V

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

PULSE DURATION SETUP AND HOLD TIMES

2.7 V 2.7 V
Output 1.5 V 1.5 V
Input 1.5 V 1.5 V
Control
0V 0V

tPLH tPHL tPZL tPLZ

VOH Output 3V
1.5 V 1.5 V Waveform 1 1.5 V
Output VOL + 0.3 V
S1 at 6 V VOL
VOL
(see Note B)
tPHL tPLH tPZH tPHZ
Output VOH
VOH
Waveform 2 VOH − 0.3 V
1.5 V 1.5 V 1.5 V
Output S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9564201Q2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9564201Q2A
SNJ54LVTH
245AFK
5962-9564201QRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201QR Samples
& Green A
SNJ54LVTH245AJ
5962-9564201QSA ACTIVE CFP W 20 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201QS Samples
& Green A
SNJ54LVTH245AW
5962-9564201V2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9564201V2A
SNV54LVTH
245AFK
5962-9564201VRA ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201VR Samples
& Green A
SNV54LVTH245AJ
5962-9564201VSA ACTIVE CFP W 20 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201VS Samples
& Green A
SNV54LVTH245AW
SN74LVTH245ADBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245ADW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH245A Samples

SN74LVTH245ADWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH245A Samples

SN74LVTH245ADWRG4 ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH245A Samples

SN74LVTH245ANSR ACTIVE SOP NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVTH245A Samples

SN74LVTH245APW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245APWE4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245APWG4 ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 LXH245A Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVTH245APWRE4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245APWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LXH245A Samples

SN74LVTH245ARGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 LXH245A Samples

SNJ54LVTH245AFK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9564201Q2A
SNJ54LVTH
245AFK
SNJ54LVTH245AJ ACTIVE CDIP J 20 20 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201QR Samples
& Green A
SNJ54LVTH245AJ
SNJ54LVTH245AW ACTIVE CFP W 20 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9564201QS Samples
& Green A
SNJ54LVTH245AW

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVTH245A, SN54LVTH245A-SP, SN74LVTH245A :

• Catalog : SN74LVTH245A, SN54LVTH245A

• Enhanced Product : SN74LVTH245A-EP, SN74LVTH245A-EP
• Military : SN54LVTH245A
• Space : SN54LVTH245A-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVTH245ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVTH245ADWR SOIC DW 20 2000 330.0 24.4 10.9 13.3 2.7 12.0 24.0 Q1
SN74LVTH245ANSR SOP NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1
SN74LVTH245APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVTH245APWRG4 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74LVTH245ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVTH245ADBR SSOP DB 20 2000 356.0 356.0 35.0
SN74LVTH245ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVTH245ANSR SOP NS 20 2000 367.0 367.0 45.0
SN74LVTH245APWR TSSOP PW 20 2000 356.0 356.0 35.0
SN74LVTH245APWRG4 TSSOP PW 20 2000 367.0 367.0 38.0
SN74LVTH245ARGYR VQFN RGY 20 3000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9564201Q2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9564201V2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9564201VSA W CFP 20 25 506.98 26.16 6220 NA
SN74LVTH245ADW DW SOIC 20 25 507 12.83 5080 6.6
SN74LVTH245APW PW TSSOP 20 70 530 10.2 3600 3.5
SN74LVTH245APWE4 PW TSSOP 20 70 530 10.2 3600 3.5
SN74LVTH245APWG4 PW TSSOP 20 70 530 10.2 3600 3.5
SNJ54LVTH245AFK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0020A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/B 08/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0020A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/B 08/2019
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4225264/A

www.ti.com
 PACKAGE OUTLINE
RGY0020A SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.65 B
A
3.35

PIN 1 INDEX AREA

4.65
4.35

1.0
0.8

SEATING PLANE
0.05
0.00 0.08 C
2.05 0.1

2X 1.5
(0.2) TYP
10 11 EXPOSED
THERMAL PAD
9
12
14X 0.5

2X SYMM 21
3.05 0.1
3.5

2
19
0.30
1 20 20X
PIN 1 ID 0.18
SYMM
0.1 C A B
0.5 0.05
20X
0.3
4225320/A 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(2.05)
SYMM
1 20
20X (0.6)

2
19

20X (0.24)

(1.275)

(4.3)
SYMM 21
(3.05)

14X (0.5)

(0.775) 12
9

(R0.05) TYP

( 0.2) TYP
VIA 10 11
(0.75) TYP

(3.3)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225320/A 09/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGY0020A VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

SYMM

4X (0.92)

1 20 (R0.05) TYP

20X (0.6)

2
19

20X (0.24)

4X
(1.33)

21
SYMM

(4.3)
(0.77)

14X (0.5)

(0.56)
9 12

METAL
TYP
10 11
(0.75)
TYP
(3.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225320/A 09/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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