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Igital Erification Low: Ahmoud Aeed Lbosily, Taff Erification Ngineer

The document provides an overview of SystemVerilog for verification, covering key topics such as processes, classes, constrained randomization, and functional coverage. It details procedural blocks like 'initial' and 'always', parallel execution with 'fork-join', and object-oriented programming concepts including class definition, object instantiation, and memory management. The content is intended for ITI students and includes examples to illustrate the concepts discussed.
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0% found this document useful (0 votes)
2 views21 pages

Igital Erification Low: Ahmoud Aeed Lbosily, Taff Erification Ngineer

The document provides an overview of SystemVerilog for verification, covering key topics such as processes, classes, constrained randomization, and functional coverage. It details procedural blocks like 'initial' and 'always', parallel execution with 'fork-join', and object-oriented programming concepts including class definition, object instantiation, and memory management. The content is intended for ITI students and includes examples to illustrate the concepts discussed.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 21

Digital Verification Flow

Mahmoud Saeed Elbosily, Staff Verification Engineer

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 1


SystemVerilog for Verification
+ Verification Planning
Mahmoud Saeed Elbosily, Staff Verification Engineer

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 2


Agenda

§ SystemVerilog Processes
§ SystemVerilog Class
§ System Verilog Constrained Randomization
§ SystemVerilog Funtional Coverage

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 3


SystemVerilog Processes -01-

In this part we will discuss the keyword:


▪ initial
▪ always, always_ff, always_latch, always_comb, and always @*
▪ fork-join, fork-join_any, and fork-join_non
▪ Level-sensitive time control, and named event time control

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 4


SystemVerilog Processes -02-

initial and always Procedural Blocks:


▪ The “initial” block:
• Starts execution at time ZERO and finishes when all its executable statements complete “between
begin and end”.
• It is executed only once.
• Do not have a trigger point.
▪ The “always” block:
• Executes continually through simulation and finishes only when the simulation finishes.
• May have a trigger point. Or without a trigger point, for example “always” for clock generation.
• The block keep executing whenever the trigger point fires.
▪ All the “initial” and “always” blocks fire at time ZERO in parallel. There is no order of
execution.
Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 5
SystemVerilog Processes -03-
initial and always Procedural Blocks:
▪ Consider the examples in SystemVerilog Processes file.
▪ Notes on always flavors:
• always_ff must contain an event control.
• always_comb automatically executes once at time ZERO.
• always@(*) waits until a change occurs on a signal in its sensitivity list.
• always_comb is sensitive to changes within the entire contents of a function.
• always@(*) is only sensitive to changes to the arguments of a function.
• Variables on the LHS of assignments within an always_comb block, including variables from
the contents of a called function, will not be written to by any other process. The same for
always_latch, always_ff.
• Always@(*) permits multiple processes to write to the same variable.
• Blocking timing control is not allowed in always_comb, always_latch, and always_ff.
• Blocking timing control is allowed in always@(*).
Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 6
SystemVerilog Processes -04-

Parallel Blocks fork-join: “Dynamic Processes”


▪ fork-join
▪ fork-join_any
▪ fork-join_none
▪ wait_fork
▪ disable_fork

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 7


SystemVerilog Processes -05-

Parallel Blocks fork-join:


§ Classic Verilog has two ways of grouping statements:
• Inside a begin ... end, statements run sequentialy.
• With a fork…join, statements execute in parallel.
§ SystemVerilog introduces two new ways to create threads, with the fork…join_none and
fork…join_any statements.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 8


SystemVerilog Processes -06-

§ fork-join:
Parallel Blocks fork-join:

Wait for all processes


to be executed
§ fork-join_any:
Wait for at least one
process to be
executed
§ fork-join_none:
No waiting at all

Check the examples for


more details.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 9


SystemVerilog Processes -07-

Using fork-join/join_eny/join_none and fork


begin-end will trigger: #5 $display ($time,"\t Parallel process 1");
▪ Parallel statements #40 $display ($time,"\t Parallel process 2");
▪ Parellel blocks with an enclosed begin-end #10 $display ($time,"\t Parallel process 3");
sequential statements
begin // Child/Parallel Process 4
▪ Both parallel statements and blocks #20 $display ($time,"\t Sequential line 1");
#15 $display ($time,"\t Sequential line 2");
end
join
Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 10
SystemVerilog Processes -08-

Using wait fork:


▪ With Dynamic processes SystemVerilog needed to provide more global detection that
spawned processes have completed.
▪ The wait fork statement is used to ensure that all child processes have completed
execution.
Using disable fork:
▪ The disable fork statement terminates all active child processes of the process where it is
called.
▪ Termination is recursive, in other words it terminates child processes, grandchild
processes, etc.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 11


SystemVerilog Class -01-

▪ Object Oriented design is a common programming model “OOP”. Data and the means to manipulate are
described together in a formal structure called a class.
▪ A class is a datatype:
• Like a struct: Has data elements called properties
• Contains functions and tasks called methods, through which class properties may be manipulated
▪ An instance of a class is referred to as an object.
▪ SystemVerilog objects are dynamically created and destroyed.
▪ Memory allocation and deallocation are handled automatically by SystemVerilog.
▪ Pointers are a key in the flexibility of using classes, SystemVerilog implements them too and called handles.
▪ Code minimization and reuse is facilitated through inheritance, parameterization and polymorphism.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 12


SystemVerilog Class -02-

Class: class Transaction;


int A = 10;
• Formal Description/Name int B = 15; class data members
• Members ( data members, methods) int C = 20;

• Constructor function new();


… • class methods: new() and
Object: endfunction : new initialize()
• new function is the class
Instance of the class for example: txn function void initialize (); constructor
A = 0;
Data members and Methods: B = 0;
endfunction : initialize
• Accessing using “ . ” operator endclass
• txn.A = 50; Transaction txn; • txn is a handle
txn =new();
• $display (“ B Value = %d ”, txn.B); txn.initialize;
• txn is now an object
• txn.initialize(); • calling class method

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 13


SystemVerilog Class -03-

Where to define a class?


▪ You can define and use classes in SystemVerilog in a program, module, package , or
outside of any of these.
▪ Typically, we store a single class per a file.
▪ When the number of files gets too large, you can group a set of related classes and type
definitions into a SystemVerilog package as shown in classes example file.
▪ For instance, while working on a big design like an SOC, you may need to group every bus
protocol classes files in a single folder named with the protocol name, the protocol classes
should be grouped together in a single SystemVerilog package, then wherever you need
to use the protocol files, you will just need to import the protocol package.
Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 14
SystemVerilog Class -04-
Creating New Objects:
• A SystemVerilog class is instantiated during simulation, when needed by the testbench.
• SystemVerilog stimulus objects are constantly being created and used to drive the DUT and check the
results. Later, the objects may be obsolete so their memory space can be used by new ones.
• SystemVerilog class must be instantiated before it can be used.
• This leads us to talk about object creation or construction. Transaction txn; // declare the handle txn
txn = new (); // txn is now an object
SystemVerilog Handles and Constructing Objects:
• First line in the code shown, we declare the handle for the type Transaction.
• The handle name is txn. It’s initialized to a special value null. It points at nowhere at the memory “no
memory allocation yet”
• 2nd line, by calling the special new() function, it constructs/create the Transaction’s object txn.
• The special new() function allocates a memory space for the Transaction’s object txn. The memory
space size depends on the size of the class’s data members and methods.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 15


SystemVerilog Class -05-

Custom Constructor: class Transaction;


int A ;
§ You can define your own new() function to set your own values. int B ;

§ You must not give a return value type, as the constructor is a special function new( int a = 3 , b = 5);
function and automatically returns a handle to an object of the same A = a;
type as the class. B = b;
endfunction : new
§ Check the declaration of the handles of txn1 to txn4 and check the endclass
objects construction.
initial begin
§ Please keep in your mind we have two different statements: Transaction txn1, txn2, txn3, txn4;
txn1 = new();
• Declare the handle txn2 = new (4,7);
• Create the object txn3 = new (.a(10), .b(12));
txn4 = new[5];
§ You declare a handle and construct/create an object. end

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 16


SystemVerilog Class -06-

Handles: initial begin


Transaction txn1, txn2;
§ You declare a handle and construct/create an object. txn1 = new(); // line 1
txn2 = txn1; // line 2
§ Handle can point to nothing, has the vale null. txn1 = new(); // line 3
end
§ Along the simulation time, a single handle can point to many objects.
1st
§ Multiple handles can point to the same object. txn2 txn1
Object

txn1 1st
txn2 Object

2nd 1st
txn1 txn2
Object Object

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 17


SystemVerilog Class -07-

Objects Deallocation: initial begin


Transaction txn1; // line 1
▪ Once the transaction usage is completed successfully. You should txn1 = new(); // line 2
deallocate the transaction’s memory space; otherwise, a long txn1 = new(); // line 3
simulation may run out of memory. txn1 = null; // line 4
end
▪ Remember: physical memory space and its utilization may become
a nightmare. txn1
▪ You can deallocate the memory space implicitly, by calling the
new() multiple times, every time the new() is called, a new object is 1st
txn1
created, and its address will be stored in txn1. Object

▪ You can deallocate explicitly, by assign null value to txn1. Now the
1st and 2nd objects memory spaces are garbage. 2nd 1st
txn1
Object Object

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 18


SystemVerilog Class -08-
§ As mentioned before SystemVerilog class must be instantiated before it
can be used. “an object”.

§ Class methods can be normal SystemVerilog functions/task or both. extern function void add();

§ Defining class methods can be inside/outside the scope of the class. function void Calculator::add();
input_a = 20;
§ Please refer to the examples provided for more understanding. result = input_a + input_b;
$display("Result from add function: %d", result);
§ Methods can be defined inside the class scope or outside the class. endfunction : add

§ Please check the static variables and static function examples. static int unsigned input_a;
• Static variables and methods can be accessed directly by the data type Calculator::input_a ++;
“class name Calculator” using the scope operator “::” as shown.
• Static variables and methods can be accessed also by the class object extern static function void incr();
itself, and static variables can be modified inside a class method Calculator::incr();
regardless it’s defined as static or automatic as shown. Or at the c1.incr();
new() function.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 19


SystemVerilog Class -09-
Copying Objects:
▪ Sometimes it require to copy a specific class object because you need to do some data manipulation on the
object without affecting the original one.
▪ Note that the ultimate objective to have a copy which can be access at any time without accessing the
original one.
▪ There are different flavors of copying, you should be careful which flavor should you choose:
• Copying an object with the new operator
• Writing a simple copy Function
• Writing a deep copy Function

§ Check the examples provided for more explanation.

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 20


Thank You!

Mahmoud Elbosily, Confidential to ITI Students Year 2023 10/17/2023 21

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