MS Thesis

Design and Implementation of High-Speed CMOS Clock and Data Recovery Circuit for Optical Interconnection Applications Seong-Jun Song
Dec. 20, 2002
Semiconductor System Laboratory, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST)

SS L

Semiconductor System Lab

Seong-Jun Song 1

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 2

Introduction
Optical Input Data Noise Corrupted Data Boosted Data Recovered Clock Retimed Data Recovered Clock

Pre Amp

Post Amp

Decision Circuit

1:4 DEMUX

Network Interface Framer

AGC*
* AGC : Automatic Gain Control

Clock Recovery Circuit

Freq. Divider

SS L

Semiconductor System Lab

Seong-Jun Song 3

Motivation
Long-Haul Applications (SONET, Gigabit Ethernet) Short-Haul Applications (Backplane, Chip-to-Chip)

III-V, Si Bipolar, SiGe HBT Very high-speed Inherently low noise # High cost # High power consumption # Not compatible with
other technologies

CMOS Low cost High level of integration Low power consumption # Less speed # High noise

SS L

The Solution is Novel CDR Architecture and Circuit Techniques In CMOS !!!
Seong-Jun Song 4

Semiconductor System Lab

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 5

Generic CDR Configuration

Clock and Data Recovery (CDR)
Pre Amp Post Amp Decision Circuit
1:4 DEMUX

Network Interface Framer

AGC

Clock Recovery Circuit

Freq. Divider

Edge Edge Detector Detector

Phase Phase Detector Detector

Loop Loop Filter Filter

VCO VCO

SS L

PLL-Based Clock Recovery Circuit

Seong-Jun Song 6

Semiconductor System Lab

Performance Limitation of 0.25-m CMOS *

Max. Oscillation Frequency (GHz)

Max. Performance 2GHz (2-Gb/s)

2.4 2.0 1.6 1.2 0.8 3 4 5 6 7
Delay Delay Delay

Simple VCO
* M. Fukaishi, et al., JSSC, Dec. 1998

A Number of Delay Stages

! Simulation result for 0.25-m CMOS differential ring oscillators with resistive loads and isolation buffers

SS L

Semiconductor System Lab

Seong-Jun Song 7

Substrate Noise Effect of VCO

Pre Amp

Post Amp

CDR VCO

1:4 DEMUX

Noise-Sensitive Analog Blocks Si Substrate

VCO Switching Noise

Substrate noise voltage

* M. van Heijningen, et al., JSSC, Aug. 2002

SS L

Semiconductor System Lab

Seong-Jun Song 8

Conventional CDR Techniques (1/2)

! Full-Rate Clock Technique * # Full-rate clock frequency (4GHz) # Impossible to design VCO
* M. Soyuer, et al., JSSC, Dec. 1993
Data 0 1 2 3 4

CK

! Half-Rate Clock Technique ** # Half-rate clock frequency (2GHz) # Close to performance limitation # Difficult to design VCO
** M. Rau, et al., JSSC, July 1997

Data

CK

SS L

Semiconductor System Lab

Seong-Jun Song 9

Conventional CDR Techniques (2/2)

! Oversampling Technique * Quarter-rate clock frequency (1GHz) Easier to design VCO # Highly clock phase resolution # Quantization jitter # Extra decision logic
* C.-K. Yang, et al., JSSC, May 1998

Data CK0 CK1 CK2

SS L

Semiconductor System Lab

Seong-Jun Song 10

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 11

Proposed CDR Technique

! 1/8-Rate Clock Technique * 1/8-rate clock frequency (0.5GHz) Very easy to design VCO Data No quantization jitter No extra decision logic Can do 1:4 DEMUX CK0 # Complex design
* S.-J. Song, et al., ESSCIRC, Sept. 2002 * S.-J. Song, et al., to be published for JSSC, July 2003

CK1 CK2 CK3

SS L

Semiconductor System Lab

Seong-Jun Song 12

Proposed 1/8-Rate CDR Architecture

Conventional Full-Rate CDR
Decision Circuit
1:4 DEMUX

Proposed 1/8-Rate CDR

1/8-Rate CDR Circuit Freq. Divider

Clock Recovery Circuit

Merging

Multiple Funtional Blocks

A Single Functional Block

! Proposed 1/8-rate CDR circuit can achieve higher speed operation, lower power consumption, and smaller area.

SS L

Semiconductor System Lab

Seong-Jun Song 13

Proposed 1/8-Rate CDR Circuit

Data Output Buffers

NRZ Data D (4-Gb/s) in

1/8-Rate Phase Detector Performing 1:4 DEMUX

DT CT

D0

CK0

CK1

CK2

CK3

Charge Pump

1:4 D1 Demultiplexed Data D2 (1-Gb/s) D3

6-Bit Coarse CC Control [5:0] Word

VCO (0.5GHz)

LPF

Clock Output Buffers

CK0 CK1 CK2 CK3 Four Half-Quadrature 1/8-Rate Clocks (0.5GHz)

SS L

Semiconductor System Lab

Seong-Jun Song 14

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 15

Choice of VCO Configuration

Ring Oscillator LC Oscillator

Delay

Delay

Delay

Wide tuning range Different phase clock generation # Low center frequency # Low Q factor # High phase noise & jitter

High center frequency High Q factor Low phase noise & jitter # Narrow tuning range # Large area
Seong-Jun Song 16

SS L

Semiconductor System Lab

Choice of Inductor Load

Spiral Inductor Load
VC

Active Inductor Load

1 L gm
osc
1 LC gm ID

C VC
osc
1 LC 1 VC

# Low Q factor (3~5) # Large area # Dependent on process # Difficult to design

Moderately high Q factor (>>10) Small area Easy to design # Noise caused by resistor and MOS
Seong-Jun Song 17

SS L

Semiconductor System Lab

Voltage-Controlled Oscillator
* DCC : Duty Cycle Correction

CK0 CK0

CK1 CK1

CK2 CK2

CK3 CK3

Feedback Isolation Buffers with DCC *

Delay

Delay

Delay

Delay

Fine Control Coarse Control 6

! Four half-quadrature phase clocks ! Delay stage with active inductor load ! DCC for using both rising and falling edges of clock

SS L

Semiconductor System Lab

Seong-Jun Song 18

Feedback Isolation Buffer

Bandwidth Extension
Resistive Feedback

Vin

Vout
Vin Vout

High CMRR Feedback

Duty-Cycle Correction

(a) Block Diagram

(b) Transistor-Level Implementation

Seong-Jun Song 19

SS L

Semiconductor System Lab

Single Delay Stage of the VCO

R1 M9

Active Inductor Load

R2 M10 M11 M12 Vout

Vin
6-Bit Coarse Control Word

M1 M2
6

M3 M4

M5 M6

M7 M8

Vfine_ctrl

R3
32I 16I 8I 4I 2I I

R4

6-bit Digital Coarse Tuning

Folded Differential Fine Tuning

osc = FR + K VCO_FineVfine_ctrl + K VCO_Coarse N for N = 0,...,63

SS L

Semiconductor System Lab

Seong-Jun Song 20

1/8-Rate Linear Phase Detector

Four Demultiplexed Data (D0~D3)
D Q

Data & Clock Transition (DCT) Detector

Data & Clock Transition (DCT) Generator

CK0
D Q D Q

DCT0

! Three tasks
! Data Transition Detection ! Linear phase error detection ! Data regeneration
DT
To Charge Pump

CK1
D Q

DCT1

Din
D Q

! Data demultiplexing ! No systematic offset ! Employing proposed folded current-mode logic family
(D-latch, MUX, and XOR)

CK2
D Q D Q

DCT2

CT

CK3
D Q

DCT3

SS L

Semiconductor System Lab

Seong-Jun Song 21

1/8-Rate Linear PD Characteristic

250ps Data CK Data-CK delay
100 80

VCT - VDT (mV)

60 40 20 0 -20 -40 -60 -80 0 50 100 150 200 250 300 350 400 450 500

Locking Point

SS L

Data to CK delay

(ps)
Seong-Jun Song 22

Semiconductor System Lab

Current-Mode Logic (CML)

Conventional CML D-Latch Proposed Folded CML D-Latch

Q
D

D
CK

CK

High speed operation Low power consumption # High supply voltage # Need for level shifter

Higher speed operation Low supply voltage No need for level shifter Wide input/output range # High power consumption # Large area
Seong-Jun Song 23

SS L

Semiconductor System Lab

Proposed Folded CML Family *

Folded MUX * Folded XOR *

Q = CK D1 + CK D0

Q = A B + A B = A B

D1 CK

D0

B A

* S.-J. Song, et al., to be published for JSSC, July 2003

SS L

Semiconductor System Lab

Seong-Jun Song 24

Fully Differential Charge Pump

* CMFB
* CMFB : Common-Mode Feedback

LPF

Vctrl

DT

CT

DT CT Vctrl t

SS L

Semiconductor System Lab

Seong-Jun Song 25

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 26

Chip Microphotograph
1/8-Rate Phase Detector Performing 1:4 DEMUX CP

VCO

! 0.25-m Standard CMOS ! 0.9 x 1.0 mm2

LPF

SS L

Semiconductor System Lab

Seong-Jun Song 27

Test Fixture
Four 0.5GHz Recovered Clock Out

Gold Wire Bonding

4-Gb/s Data In

Four 1-Gb/s Recovered Data Out FR-4 PCB

SS L

Semiconductor System Lab

Seong-Jun Song 28

Measured Recovered Clock

! For 231-1 PRBS input data at 4-Gb/s,

10 dB/div

-112dBc/Hz @ 1MHz offset

47ps pk-pk 5.2ps RMS

1 MHz/div

100 ps/div

SS L

Semiconductor System Lab

Seong-Jun Song 29

Measured Eye Diagrams

Four Recovered Data Output (1-Gb/s) 231-1 PRBS Data Input (4-Gb/s)
Din
V: 200 mV/div, H: 200 ps/div
CK0 CK1 CK2 CK3

1/8-Rate CDR Circuit

D0 D1 D2 D3

Four Recovered Clock Output (0.5GHz)

V: 200 mV/div, H: 200 ps/div

V: 200 mV/div, H: 500 ps/div

SS L

Semiconductor System Lab

Seong-Jun Song 30

Recovered Clock and Data

! For 231-1 PRBS input data at 4-Gb/s,
1-Gb/s Demultiplexed Recovered Data (D0)

200 mV/div

0.5GHz Recovered Clock (CK0) 500 ps/div

SS L

Semiconductor System Lab

Seong-Jun Song 31

Measured VCO Characteristic

Differential Fine Tuning
Measured VCO Frequency (MHz)
530 520 510 500 490 480 470 460 450 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

6-Bit Digital Coarse Tuning

Measured VCO Frequency (MHz)
540 520 500 480 460 440 420 400 380 0 10 20 30 40 50 60 70

osc

ID

osc

ID

Differential Fine Control Voltage (V)

6-Bit Coarse Control Word (N)

! KVCO_Fine = 75 MHz/V ! Fine Tuning Range = 70 MHz (14%)

! KVCO_Coarse = 2.5 MHz/Word Step ! Coarse Tuning Range = 150 MHz (30%)

osc = FR + K VCO_FineVfine_ctrl + K VCO_Coarse N for N = 0,...,63

SS L

Semiconductor System Lab

Seong-Jun Song 32

Performance Summary
NRZ Data Rate Recovered Clock Recovered Data Capture Range VCO Fine Tuning Gain Phase Noise at 1-MHz offset Clock Jitter for 231-1 PRBS BER for 231-1 PRBS Power Dissipation (excluding output buffers) Supply Voltage Active Area Technology 4-Gb/s 0.5 GHz Four 1-Gb/s 16 MHz 75 MHz/V -112 dBc/Hz 5.2 ps RMS < 10-6 70 mW 2.5 V 0.9 x 1.0 mm2 0.25-m standard CMOS
Seong-Jun Song 33

SS L

Semiconductor System Lab

Proposed Performance Index

! From O. T.-C. Chen, et al., JSSC, Jan. 2002, ! Frequency index in PLL is derived by
1.8 V Technology F = F (MHz) 0.35 m Supply Voltage

! By taking account into power consumption in CDR circuit, ! Proposed performance index in CDR circuit can be expressed as
Normalized Data Rate =
70 mW Technology Supply Voltage Data Rate (Gb/s) 2.5 V 0.25 m Power Consumption

SS L

Semiconductor System Lab

Seong-Jun Song 34

Performance Comparison
Reference [1] [2] [3] [4] [5] [6] [7] [8] This Work CDR Technique Full-Rate Clock Half-Rate Clock Half-Rate Clock Half-Rate Clock Half-Rate Clock 3x-Oversampling 3x-Oversampling 2x-Oversampling 1/81/8-Rate Clock Normalized Data Rate 1.12-Gb/s 1.08-Gb/s 1.27-Gb/s 2.17-Gb/s 2.62-Gb/s 0.76-Gb/s 2.29-Gb/s 2.47-Gb/s 4-Gb/s Data Rate 1-Gb/s 1.25-Gb/s 10-Gb/s 1-Gb/s 6-Gb/s 4-Gb/s 5-Gb/s 4-Gb/s 4-Gb/s Power Consumption 300 mW 150 mW 285 mW 85 mW 83 mW 973.5 mW 153 mW 84 mW 70 mW Supply Voltage 5V 3.3 V 1.8 V 3.3 V 1.8 V 3.3 V 2.5 V 1.93 V 2.5 V Technology 0.6-m CMOS 0.35-m CMOS 0.18-m CMOS 0.5-m CMOS 0.18-m CMOS 0.5-m CMOS 0.25-m CMOS 0.24-m CMOS 0.250.25-m CMOS

Normalized Data Rate =

70 mW Technology Supply Voltage Data Rate (Gb/s) 0.25 m Power Consumption 2.5 V

SS L

Semiconductor System Lab

Seong-Jun Song 35

Normalized Performance Comparison

4.5 Normalized Data Rate (Gb/s) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
0
Full-Rate Clock Half-Rate Clock Oversampling 1/8-Rate Clock

50% Increase
[1] H. Wang, et al., ISSCC, 1999 [2] K. Iravani, et al., CICC, 1998 [3] J. E. Rogers, et al., ISSCC, 2002 [4] M. Rau, et al., JSSC, July 1997 [5] K. Nakamura, et al., SOVC, 1998 [6] C.-K. Yang, et al., JSSC, May 1998 [7] S.-H. Lee, et al., JSSC, Dec. 2002 [8] M.-K.E. Lee, et al., SOVC, 2002

[1] 1

[2] 2

[3] 3

[4] 4

[5] 5

[6] 6

[7] 7

CMOS CDR Circuits

[8] This 10 8 9 Work

SS L

Semiconductor System Lab

Seong-Jun Song 36

Outline
! ! ! ! ! ! ! Introduction Motivation Problem Definition Proposed 1/8-Rate CDR Building Blocks Measurement Results Conclusion & Further Works

SS L

Semiconductor System Lab

Seong-Jun Song 37

Conclusion
! A high-speed and low-power CDR circuit has been introduced :
! Exploiting 1/8-rate clock technique ! Using a 0.25-m standard CMOS technology ! Single functional block merging clock recovery circuit, decision circuit, divider, and 1:4 DEMUX

! The proposed CDR demonstrates 4-Gb/s and 70mW operation

suitable for low cost optical interconnection applications.

SS L

Semiconductor System Lab

Seong-Jun Song 38

Further Works
! Fully Integrated Frequency-Locked Loop
! Broadband frequency detection

! Improvement of BER
! To improve SNR ! To improve Clock Jitter Characteristic

! Need for Detailed Mathematical Analysis

SS L

Semiconductor System Lab

Seong-Jun Song 39

Supplemental Materials

SS L

Semiconductor System Lab

Seong-Jun Song 40

Operation of 1/8-Rate PD (1/4)

Din CK0 CK1
D Q

9 10 11 12

CK0
D Q D Q

CK2 CK3 DCT0 DCT1

D Q

0+1 1+2 2+3

4+5 5+6 6+7

8+9 9 + 10 10 + 11 11+12

CK1 Din
D Q

DCT2 DCT3 DT
D Q

3+4

7+8

CK2
D Q

CT

CK3
D Q

D0 D1 D2 D3

0 1 2 3

4 5 6 7

8 9 10

12

11

SS L

Semiconductor System Lab

Seong-Jun Song 41

Operation of 1/8-Rate PD (2/4)

Din CK0 CK1
D Q

9 10 11 12

Data & Clock Transition (DCT) Detector

CK0
D Q D Q

DCT0

CK2 CK3 DCT0 0+1 1+2 2+3 3+4 4+5 5+6 6+7 7+8 8+9 9 + 10 10 + 11 11+12

CK1
D Q

DCT1

DCT1 DCT2

Din
D Q

CK2
D Q D Q

DCT2

DCT3 DT CT

CK3
D Q

DCT3

D0 D1 D2 D3

0 1 2 3

4 5 6 7

8 9 10

12

11

SS L

Semiconductor System Lab

Seong-Jun Song 42

Operation of 1/8-Rate PD (3/4)

Din 0 1 2 3 4 5 6 7 8 9 10 11 12

Four Demultiplexed Data (D0~D3)

D Q

CK0 CK1

Data & Clock Transition (DCT) Detector

CK0
D Q D Q

DCT0

CK2 CK3 DCT0 0+1 1+2 2+3 3+4 4+5 5+6 6+7 7+8 8+9 9 + 10 10 + 11 11+12

CK1
D Q

DCT1

DCT1 DCT2

Din
D Q

CK2
D Q D Q

DCT2

DCT3 DT CT

CK3
D Q

DCT3

D0 D1 D2 D3

0 1 2 3

4 5 6 7

8 9 10

12

11

SS L

Semiconductor System Lab

Seong-Jun Song 43

Operation of 1/8-Rate PD (4/4)

Din 0 1 2 3 4 5 6 7 8 9 10 11 12

Four Demultiplexed Data (D0~D3)

D Q

CK0 CK1

Data & Clock Transition (DCT) Detector

Data & Clock Transition (DCT) Generator

CK0
D Q D Q

DCT0

CK2 CK3 DCT0 0+1 1+2 2+3 3+4 4+5 5+6 6+7 7+8 8+9 9 + 10 10 + 11 11+12

CK1
D Q

DCT1

DT

DCT1 DCT2 DCT3

Din
D Q

CK2
D Q D Q

DCT2

CT

DT CT D0 D1 D2 D3 0 1 2 3 4 5 6 7 8 9 10 11 12

CK3
D Q

DCT3

SS L

Semiconductor System Lab

Seong-Jun Song 44

Example
0 1 1 0 0 1 0 0 1 1 1
Din CK0 CK1 CK2 CK3 DCT0 DCT1 DCT2 DCT3 DT CT

SS L

Semiconductor System Lab

Seong-Jun Song 45