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Numerical Simulation of N+ Source Pocket

PIN-GAA-Tunnel FET: Impact of Interface
Trap Charges and Temperature
Jaya Madan, Student Member, IEEE , and Rishu Chaujar, Senior Member, IEEE

Abstract — This paper investigates the reliability of PIN- leakage current, high subthreshold swing (SS), and other short
gate-all-around (GAA)-tunnel field-effect transistor (TFET) channel effects [1]. These challenges enforce for exploring
with N+ source pocket. The reliability of the PNIN-GAA-TFET the novel devices that work on new operation mechanisms
is examined by analyzing: 1) the impact of interface trap
charge (ITC) density and polarity and 2) the temperature other than thermionic emission over the thermal barrier as
affectability on analog/RF performance of the device. It in the case of MOSFET. In this regard, tunnel field-effect
is realized that the interface traps existing at the Si/SiO2 transistors (TFETs) that use interband tunneling in the source
interface modifies the flatband voltage and, thereby, alters and channel junction with a control of gate bias has attracted
the analog and RF characteristics of the device. The analy- much attention [2]–[6]. The major challenges faced by
sis is done at various trap charge densities and polari-
ties. The results, thus, obtained reveal that, at higher trap MOSFET, such as the limitations on the SS that has a
charge density, the device performance alters significantly. fundamental limit of 60 mV/decade and high OFF-state leakage
It is obtained that, for a donor trap charge density of current, have been overcome by TFET up to a great extent.
3 × 1012 cm−2 , the off-state current of the device In TFET, the large tunneling barrier width present at the
degrades tremendously (increases from an order of source–channel junction at lower gate bias blocks the tunneling
10−17 –10−9 A). The temperature affectability over the device
of electrons and, thereby, benefits a very low leakage current.
reveals that, at lower gate bias, the Shockley–Read–Hall
phenomenon dominates and degrades the subthreshold However, the band-to-band tunneling (BTBT) of carriers from
current of the device at elevated temperatures. How- the source potentially allows a steep SS values [7]. Apart
ever, for the superthreshold regime, the band-to-band from these merits, TFET suffers from low ON-current, high
tunneling (BTBT) mechanism dominates. Furthermore, threshold voltage (Vth ), high gate–drain parasitic capacitance,
the results show enormous degradation in the off-state
and ambipolar current [8], [9]. For superior analog/RF per-
current at elevated temperatures, such that, with an
increase in the ambient temperature from 200 K to 400 K, formance, many device engineering architectures and III–V
the IOFF degrades by an order of 105 , i.e., increases materials have also been proposed by various researchers [2],
from 10−18 A to 10−13 A. The results specify that the [8], [10]–[15]. Among all device engineering architectures, the
PNIN-GAA-TFET is insusceptible to the acceptor traps exist- N+ source pocket p-i-n TFET or PNIN-TFET proposed by
ing at the Si/SiO2 interface in comparison with the donor [14] is a strong candidate as it offers higher ON-current with
traps.
lower SS and lower Vth . III–V TFET, however, mitigates the
Index Terms — Interface trap charges (ITCs), N+ source problem of lower ION offered by their lower bandgap, lower
pocket, temperature sensitivity, tunnel FET (TFET). effective mass, and wide range of band alignments; thus, III-V
material-based TFETs have the potential of high switching
I. I NTRODUCTION speed, but at the same time suffering from large SS [16].
However, the basic device characteristics, such as improved

P ERPETUAL miniaturization of complementary metal–

oxide–semiconductor (CMOS) devices has incredibly rev-
olutionized many areas, such as security, military, mobile
analog, RF, and linearity of TFET, have been the major
encompassing area of the investigation up to now. Recently,
Moselund et al. [9] fabricated lateral p-type InAs/Si TFET
communications, and medicine. However, downscaling the with ION of a few μA/μm for |Vds| = |Vgs | = 0.5 V. A SiGe/Si
CMOS technology results in severe problems, such as high heterostructure TFET has been fabricated by Blaeser et al. [17]
that shows ION of 6.7 μA/μm at Vdd = 0.5 V and SS
Manuscript received January 16, 2017; revised February 1, 2017;
accepted February 14, 2017. The work of J. Madan was supported by the of ∼80 mV/decade. Nonetheless, for sub-100-nm devices,
University Grants Commission. The review of this paper was arranged the reliability of TFET is also a critical concern, owing to the
by Editor Frank Schwierz. strong electric field at the source–channel junction. This strong
The authors are with the Microelectronics Research Labora-
tory, Engineering Physics Department, Delhi Technological Univer- electric field roots to the generation of defects at the Si–SiO2
sity, New Delhi 110042, India (e-mail: jayamadan.2012@gmail.com; interface [18]. Along with the high electric field, the fabri-
rishu.phy@dce.edu). cation processes for sub-100-nm devices, such as the plasma
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. etching, may damage the gate oxide and the Si-oxide interface.
Digital Object Identifier 10.1109/TED.2017.2670603 These defects are the origin of fixed interface and oxide

0018-9383 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE TRANSACTIONS ON ELECTRON DEVICES

charges. These fixed charges can adversely affect the yield and
reliability, and also alters the ideal predicted device character-
istics [19], [20]. The impact of interface trap charges (ITCs)
has also been investigated on lateral p-type InAs/Si (a III–V
TFET) by Sant et al. [21], which reported that the high con-
centration of trap centers formed at the heterojunction of III–V
material (source side) and the silicon (channel region)
attributes to the carrier generation by the trap-assisted tun-
neling (TAT) at the heterojunction, which degrades the SS
of TFET. The large trap centers at the interface of III–V Fig. 1. (a) Simulation structure of PNIN-GAA-TFET. (b) Comparison of
experimental [28] and simulated Ids –Vgs of GAA-TFET.
TFET evaluate the charge density at the interface and, thereby,
alter the device electrostatics. In addition to the traps present
at the heterojunction, for a III–V TFET, the traps at the The device parameters such as the channel length (L g ),
interface of channel and oxide add to further degradation gate oxide thickness (tOX ), and radius (R) of the device under
of the subthreshold characteristics of TFET. However, till consideration are 50, 3, and 10 nm, respectively. The source,
date, not much has been reported regarding the study of the channel, and drain are of silicon. The source (P+ ), channel,
impact of ITCs on the reliability of TFET [18]–[20], [22]–[24]. and drain (N+ ) regions are uniformly doped. The source is
Moreover, to meet the everlasting demand of transistors with p+ -type doped (1 × 1020 cm−3 ), and the drain is n+ -doped
high- and low-temperature tolerance (other than the room tem- (5 × 1018 cm−3 ). The drain doping is 5 × 1018 cm−3 (i.e.,
perature) needed in aircraft, space, and automotive technology, less than source doping), to minimize the drain–channel tun-
the temperature affectability over the device performance must neling and, thus, the ambipolar conduction [29]. Furthermore,
be analyzed [25], [26]. In addition, with an increase in number an optimum value of gate metal work function, i.e., 4.3 eV has
of on-chip transistors, the heat dissipation increases drasti- been chosen for optimum better subthreshold characteristics.
cally. Therefore, the operating temperature of transistor also
increases. Thus, for better reliability, it is obligatory to analyze A. Simulation Methodology
the performance of the device at various ambient temperatures. The PNIN-GAA-TFET is simulated using the ATLAS
Dey et al. [16] and Mookerjea et al. [27] reported that the device simulator [30]. For TFETs, the BTBT model is signif-
temperature dependence of III–V TFET is a strong function icantly important. Local BTBT model estimates a triangular
of gate bias, due to the onset of various conduction mecha- barrier approximation in the energy bands and, thus, considers
nisms at different gate-bias regions. At lower gate-bias region, a constant electric field at the entire tunneling region. However,
the consequence of exponential temperature dependence of the non-local BTBT incorporates the dynamic changes in the
Shockley–Read–Hall (SRH) generation recombination results electric field at the entire tunneling path. Thus, the non-local
in the exponential rise of IOFF . Further increase in the gate BTBT that calculates the generation rate at each mesh point
bias thermally excites the carriers from the trap centers into in the tunneling region is incorporated in this work [31].
the conduction band. However, at higher gate-bias region, In addition to the non-local BTBT model, concentration-
the BTBT contributes to the drain current with negligible and field-dependent mobility model, SRH model for carrier
contribution from the trap centers. Moreover, it is reported recombination, bandgap narrowing, and Fermi–Dirac statistics
in [27] that the peak interface state density is in the middle are also invoked during simulation. Besides, Gummel (decou-
of the energy bandgap. Therefore, the major contribution of pled) and Newton’s (fully coupled) methods have been used
the midgap traps at the oxide–semiconductor interface in the to numerically solve the carrier transport equation. Owing
tunneling process causes a degradation in SS at elevated to the strong electric field at the source–channel (tunneling)
temperatures. The surface passivation is recommended for junction, the ITCs are considered only at 10-nm length from
reducing the TAT and the degradation caused at the elevated the interface of the source and the N+ pocket and along the
temperatures and the ITCs to the SS and IOFF . In this work, Si–SiO2 interface [19]. In addition, the reliability of device
the gate-all-around (GAA) architecture with N+ source pocket in terms of ITCs is analyzed by transmuting the equivalent
PIN-TFET is considered, and an elaborate study of its analog positive (negative) localized charges at the Si–SiO2 interface.
characteristics and RF figure of merits is reported, including The uniform distribution of ITC density is considered in the
the impact of ITC density and polarity at various ambient TCAD simulations. The parameters such as the trap charge
temperatures. density, polarity, and their position along the channel are
defined in INTERFACE statement. In this work, the density of
II. D EVICE A NALYSIS AND S IMULATION the interface charge density (N f ) is chosen in support with var-
Fig. 1(a) shows the 3-D view of simulated device structure, ious formerly published experimental and simulation data that
i.e., N+ source pocket PIN-GAA-TFET (PNIN-GAA-TFET). includes the process damage, radiation damage, and hot carrier
For PNIN-GAA-TFET, the source pocket length (L p ) and the damage, and results in ITC density of 1011–1013 cm−2 eV−1
source pocket (N+ ) doping (N p ) are assessed for the optimized [18], [20], [21]. The reliability of PNIN-GAA-TFET
analog characteristics, and the optimum values of L p and N p is analyzed in terms of various electrical, analog, and RF
are obtained as 4 nm and 4×1019 cm−3 , respectively, as shown figures of merit. Moreover, while analyzing the influence
in our previous work [4]. of ITCs on device characteristics, the temperature is kept
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MADAN AND CHAUJAR: NUMERICAL SIMULATION OF N+ SOURCE POCKET PIN-GAA-TFET 3

Fig. 2. (a) Electric field profile along the channel of PNIN-GAA-TFET

at Nf = ±1, 2, 3 (×12) cm−2 . (b) Peak intensity of parallel and normal
components of electric field near tunneling junction of PNIN-GAA-TFET Fig. 3. Nonlocal BTBT of electrons of PNIN-GAA-TFET as a function of
as a function of ITC density. channel length at Nf = ±1, 2, 3 (×12) cm−2 .

constant at 300 K, and during investigation of tempera- is a merit for enhancing the tunneling rate of electrons, but
ture affectability, the trap charge density is kept constant at it also attributes to the generation of trap centers near the
N f = ±1 × 1012 cm−2 . source–channel junction. As reported in [32], the parallel
component of the electric field, i.e., E y contributes to the
tunneling rate of electrons and, thereby, affects the drain
B. Model Validation
current of TFET. Higher value E y is required for enhanced
Simulation setup has been validated by the experimental BTBT rate of electrons and, thus, for the higher value of
data, before simulating the device structure [28]. The Ids . However, the normal component of the electric field,
non-local BTBT model has been calibrated by tuning i.e., E x is responsible for the reliability concerns, such as
the tunneling masses from their default values to fit it the interface trap generation along with the gate leakage
with [28]. The adjusted value of me.tunnel = 0.22 m o and current. The lower value of E x is required for improved device
mh.tunnel = 0.52 m o [4], [19], where m o is the rest mass reliability. Thus, the peak of parallel (E y ) and normal (E x )
of electron. The validation of simulation setup with the components of electric field at the tunneling junction as a
experimental data for the transfer characteristics is shown function of ITC density is analyzed and is shown in Fig. 2(b).
in Fig. 1(b). The close proximity of simulation model At higher donor (acceptor) trap charge density, the peaks
with the experimental data, thereby, authorizes the model of both E x and E y are large (small). The higher value
considerations of simulation setup. of E y enhances the tunneling rate of electrons; however,
the larger value of E x degrades the device reliability. Fig. 3
III. R ESULTS AND D ISCUSSION shows the impact of ITC density on nonlocal BTBT rate
A. Impact of Interface Trap Charges—Density of electrons along the channel length. It is examined that,
and Polarity with an increase in the density of donor (acceptor) ITCs,
In this section, the influence of ITC density and polarity of the BTBT rate of electrons increases (decreases) extensively.
PNIN-GAA-TFET is examined at a constant temperature of This increase (decrease) in the BTBT rate of electrons is
300 K. Fig. 2(a) shows the impact of ITC density on the total attributed to the enhanced (reduced) electric field at the
electric field of PNIN-GAA-TFET. It is clearly evident from tunneling junction, as shown in Fig. 2(a). Fig. 4(a) shows
the inset (that shows the magnified view of the peak of the the impact of ITC density on the transfer characteristics of
electric field at the tunneling junction) that, with an increase of PNIN-GAA-TFET at T = 300 K. The result reveals that
donor (acceptor) trap charge density, the peak of electric field the positive (negative) traps enhances (reduces) the drain
increases (decreases) with respect to the case of undamaged current. This increase (decrease) in the drain current is the
device. This increase (decrease) in an electric field is attributed consequence of the enhanced (reduced) effective gate bias
to the decrease (increase) in the flatband voltage caused by the caused by the reduced (increased) Vfb by the presence of
presence of positive (negative) trap charges, defined as positive (negative) trap charges. The degradation posed by
the donor traps is more hazardous for the device operated in
qNf
V f b = subthreshold regime in comparison with the superthreshold
Cox regime. Furthermore, it is analyzed that, with an increase in
where q is the electronic charge, N f is the ITC density, positive trap charge density, IOFF degrades significantly from
and Cox is the gate oxide capacitance. The presence of posi- an order of 10−17 A to 10−9 A. Therefore, as the fixed charges
tive (negative) ITCs decreases (increases) the flatband voltage generated by the various process-, radiation-, and stress-
and, thereby, increases (decreases) the effective gate bias induced damages are always present in a practically fabricated
(Veff = Vgs − Vfb ) at the tunneling junction. The device, it may severely degrade the device characteristics.
enhanced (reduced) Veff caused by the occurrence of Fig. 4(b) shows the impact of trap charge density on IOFF and
donor (acceptor) trap charges, thereby, enhances (reduces) the current switching ratio (ION /IOFF ratio). As clearly shown
the electric field at the tunneling junction as evident from in Fig. 4(b), the damaged region with donor trap charges of
Fig. 2(a). Moreover, the considerably high electric field peak 3 × 1012 cm−2 degrades IOFF tremendously from an order
at the tunneling junction (caused by the steeper band bending) of 10−17 A to 10−9 A. However, as shown in Fig. 4(a),
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4 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 6. Influence of ITC density on (a) Cgs , Cgd , and (b) Cgg as a function
Fig. 4. Impact of ITC density on (a) transfer characteristics (b) Ioff and of gate voltage of PNIN-GAA-TFET.
switching ratio of PNIN-GAA-TFET at Nf = ±1, 2, 3 (×12) cm−2 .

Fig. 7. Effect of ITC density on fT as a function of Vgs of

PNIN-GAA-TFET.
Fig. 5. Impact of ITC density on Vth and SS of PNIN-GAA-TFET at
Nf =± 1, 2, 3 (×12) cm−2 . layer distribution is distinct from MOSFET. This results in
fundamentally different partitions of total gate capacitance Cgg
the presence of ITC alters the superthreshold current mar- in TFET from that of a MOSFET. As shown in [34], for TFET,
ginally and, thus, the switching ratio is mainly affected by IOFF . the drain is connected to the inversion layer and, therefore, Cgd
It is obtained that the switching ratio degrades from an order contributes majorly to Cgg , in contrary to MOSFET, where
of 1012 (for the undamaged device) to 105 (for a damaged Cgg /2∼Cgd ∼Cgs . Fig. 6(a) and (b) shows the impact of ITC
device with donor trap charge density of 3 × 1012 cm−2 ). density on Cgs , Cgd , and Cgg as a function of Vgs at the
However, the consequence of immunity against the presence constant Vds = 1 V. At lower value of Vgs , the inversion
of acceptor trap charges is also observed in unaltered ION /IOFF layer is first formed at the drain side, and with an increase
for the negative ITC density. in Vgs , it extends toward the source side as evident from
The impact of ITC density on Vth and the SS of Fig. 6(a). The reduced coupling between gate and source with
PNIN-GAA-TFET are presented in Fig. 5. It is an increase in Vgs monotonically decreases Cgs with increasing
obtained that the presence of donor (acceptor) trap Vgs . Before the inversion layer formation, Cgs comprises the
charges decreases (increases) Vth . The reduced Vth parasitic capacitance; after the inversion layer formation, Cgd
for donor trap charges is attributed to the additional dominates. In addition, the similar values of Cgg and Cgd are
band bending caused by the presence of positive trap attributed to the small value of Cgs that results in almost the
charges. Vth reduces (enhances) by 29.26% (15.90%) at same values of Cgg and Cgd . It is evaluated that the presence
N f = ±3 × 1012 cm−2 . The degradation in the SS due to of positive (negative) ITCs increases (decreases) the Cgd by
the presence of ITC is elucidated clearly in Fig. 5. This 0.1% (0.1%) at Vgs = 0 V and 8.5% (4.9%) at Vgs = 1.2 V.
degradation in the SS is due to the tremendously enhanced The influence of ITC density on Cgg as a function of Vgs of
IOFF for positive ITC. However, the consequence of little PNIN-GAA-TFET is shown in Fig. 6(b). The consequence of
variation in IOFF and ION for acceptor ITCs is shown by the immunity of Cgd against ITC density due to low electric field
slight change in the SS at negative ITCs. at the drain channel junction is evident from the unaltered Cgg
Moreover, the reliance of operating speed of TFET on with ITC density. An important RF figure of merit is the cutoff
parasitic capacitance and the different switching operation of frequency ( f T ) defined as the frequency at which the current
TFET necessitates the investigation of bias-dependent para- gain falls to 0 dB. The impact of ITC density on f T as a
sitic capacitances. In this work, the intrinsic capacitances are function of gate voltage is shown in Fig. 7. It is analyzed that
evaluated through the small-signal ac analysis, at a constant the existence of positive (negative) ITCs increases (decreases)
dc solution. In this regard, the intrinsic capacitances among f T . This increase (decrease) is due to the enhanced (reduced)
each pair of electrodes (i.e., source, gate, and drain) are drain current and, thus, the transconductance that has a direct
calculated at a single constant frequency at 1 GHz with a dependence on f T . Moreover, it is obtained that the peak
dc voltage ramp of 0–1.6 V. Moreover, for better conver- of f T , increases (decreases) more prominently at higher ITC
gence, DIRECT parameter is incorporated while simulating density. It is evaluated that, at Vgs = 1 V, the presence of
the device. As reported in [33], in TFETs, the inversion donor (acceptor) ITCs of N f = ±3 × 12 cm−2 increases
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MADAN AND CHAUJAR: NUMERICAL SIMULATION OF N+ SOURCE POCKET PIN-GAA-TFET 5

Fig. 8. Variation of nonlocal BTBT rate of electrons at the tunneling Fig. 9. (a) Drain current (b) Ioff and current switching ratio
junction as a function of temperature of PNIN-GAA-TFET at as a function of temperature (200–400 K) of PNIN-GAA-TFET at
Nf = ±1 × 12 cm−2 . Nf = ±1 × 12 cm−2 .

(decreases) f T by 2.06 (2.65) times, respectively. As f T of

TFET has a direct variation with gm and inverse variation with
the total gate capacitance Cgg (=Cgs + Cgd ), thus, the demerit
of higher Cgd in TFET attributes to the lower f T in compar-
ison with the experimental conventional Si MOSFETs with
comparable gate length, as also reported in various published
articles [33].

B. Temperature Affectability
In this section, PNIN-GAA-TFET is analyzed at various
ambient temperatures at constant ITC density. Fig. 8 presents
the variations in the nonlocal BTBT rate at various temper- Fig. 10. (a) Vth and SS as a function of temperature (b) output
characteristics at Vgs = 1.2 V, for the temperature range of 200–400 K
atures, including the effect of ITCs. In the case of TFET, of PNIN-GAA-TFET.
the BTBT rate is reliant on temperature. In addition, the prop-
erty of semiconductor, such as the energy bandgap, is also
dependent on temperature. The reliance of energy bandgap on dependence of BTBT (that is caused by the bandgap narrowing
temperature has been experimentally measured [35], and is with temperature) is dictated by the slight enhancement in
defined as the drain current at elevated temperature in the superthresh-
old region, as clearly shown in Fig. 9(a). The impact of
αE T 2
E g (T ) = E g (0) − temperature on transfer characteristics remains unaltered for
T + βE donor/acceptor ITCs. The influence of temperature on IOFF and
where E g (0) is the energy bandgap at T = 0 K for Si, the ION /IOFF ratio at N f = ±1 × 12 cm−2 and for the undam-
E g (0) = 1.170 eV, α E and β E are the material spe- aged device, i.e., with N f = 0, is shown in Fig. 9(b). The
cific fitting constants for Si, α E = 4.37 × 10−4 eV/K, results reveal that, with an increase in the temperature from
β E = 636 K, and T is the absolute temperature. With an 200 K to 400 K, IOFF increases from 10−19 A to 10−15 A (for
increase in the temperature, the bandgap of a semiconductor N f = −1×12 cm−2 ) and from 10−14 A to 10−10 A (for N f =
decreases. Thus, the narrower bandgap at elevated temperature +1 ×12 cm−2 ). However, the current switching ratio degrades
lowers the tunneling barrier width and, thereby, enhances from an order of 1014 –109 A (for N f = −1 × 12 cm−2 )
the BTBT rate of electrons. It is evaluated that, with an and from 109 A to 105 A (for N f = +1 × 12 cm−2 ). This
increase in the temperature from 200 K to 400 K, the nonlocal degradation in the ION /IOFF ratio is attributed to the enhanced
BTBT rate of electrons increases by 97.17% and 81.46% for IOFF at elevated temperatures. The influence of temperature
N f = 1 × 12 cm−2 and −1 × 12 cm−2 , respectively. The and ITC polarity on Vth and the SS of PNIN-GAA-TFET
influence of temperature (200–400 K) on the drain current as is depicted in Fig. 10(a). The significantly high degradation
a function of temperature at N f = ±1 × 12 cm−2 and for the in IOFF at elevated temperatures (instigated by SRH) and an
undamaged device, i.e., with N f = 0, is shown in Fig. 9(a). inconsiderable increase in ION (instigated by BTBT) degrade
It is clearly evident from the results that the temperature the SS at elevated temperatures. It has been analyzed that, for
affectability on the transfer characteristics is bias-dependent, an increase in the temperature from 200 K to 400 K, the SS
due to the distinct transport mechanism in OFF and ON increases by 83.23% and 25.43% for N f = −1×12 cm−2 and
states. In the subthreshold region, the drain current increases N f = 1 × 12 cm−2 , respectively. The temperature dependence
exponentially with the rise in the temperature. This increase in of Vth is also shown in Fig.10(a). As discussed before,
the drain current is attributed to the dominance of SRH recom- the drain current increases with an increase in the temperature,
bination at lower gate bias that has an exponential temperature i.e., PNIN-GAA-TFET has positive temperature coefficient
dependence. However, with an increase in Vgs , the BTBT in both subthreshold and superthreshold regions. This higher
current dominates. The consequence of small temperature drain current at elevated temperature results in reduced Vth .
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6 IEEE TRANSACTIONS ON ELECTRON DEVICES

Fig. 11. Influence of ITCs on the temperature sensitivity of the Ioff Fig. 12. (a) Variations of Cgg as a function of Vgs at the temperature
variability of PNIN-GAA-TFET at Nf =± 1 × 12 cm−2 and Nf = 0. range of 200–400 K and (b) fT as a function of Vgs at the temperature
range of 200–400 K of PNIN-GAA-TFET at Nf =± 1 × 12 cm−2 .

In addition, the consequence of bandgap reduction of Si at

elevated temperature is the lowered tunneling barrier width at and is shown in Fig. 12(a). It is examined that Cgg increases
the source–channel junction that, thereby, allows more number with an increase in the gate bias. This increase in Cgg with
of carriers to tunnel through the valence band of the source to the gate bias is owing to the fact that, at fixed drain bias and
the conduction band of the channel. Thus, the band bending at low gate bias, the inversion layer is formed near the drain
at lower gate bias at the tunneling junction for high ambient side. After the inversion layer formation, further increase in
temperature enhances the tunneling rate at lower gate bias and the gate bias extends the inversion layer toward the source
subsequently decreases Vth of the device with an increase in side. Moreover, it is obtained that, with an increase in the
the temperature. The results show that, for an increase in the temperature, Cgg increases. It is examined that, at Vgs = 1.1 V,
temperature from 200 K to 400 K, Vth decreases by 23.92% an increase in the temperature from 200 K to 400 K increases
and 36.05% for N f = −1 × 12 cm−2 and N f = 1 × 12 cm−2 , Cgg by 51.87%. Fig. 12(b) shows the influence of temperature
respectively. Fig. 10(b) illustrates the output characteristics of variation on f T as a function of gate bias. Owing to the conse-
PNIN-GAA-TFET for a temperature range of 200–400 K at quence of positive temperature coefficient of the drain current,
N f = ±1 × 12 cm−2 and for the case when localized charges gm also increases with the temperature and, thus, enhances f T
are absent. In consistent with the above results, the drain with the temperature. It is evaluated that, at Vgs = 1 V for
current increases with an increase in the temperature. It is N f = −1 × 12 cm−2 and 1 × 12 cm−2 , an increase in the
analyzed that, at Vgs = 1.2 V, with a rise in the temperature temperature from 200 K to 400 K increases f T by 23.97% and
from 200 K to 400 K, the drain current increases by 2.11 times, 11.76%, respectively.
2.03 times, and 1.97 times for N f = −1 × 12 cm−2 , N f = 0,
and N f = +1 × 12 cm−2 , respectively. IV. C ONCLUSION
As the temperature affectability is maximum in the sub-
This work encompasses the reliability of N+ source pocket
threshold region, therefore, a quantitative analysis of the
PIN-GAA-TFET in terms of: 1) impact of ITC density and
influence of ITCs on the temperature sensitivity (ST ) of the
polarity and 2) temperature affectability over the device char-
IOFF variability has been done. ST of PNIN-GAA-TFET as a
acteristics by numerical simulations. It is analyzed that the
function of ITCs is shown in Fig. 11, and is evaluated as
presence of donor (acceptor) trap charges enhances (reduces)
 
∂ log (IOFF ) −1 the parallel E y and normal E x component of the electric
ST = K/decade. field. The enhanced E y increases the BTBT rate of electrons.
∂T
However, the increased E x contributes to the generation of
As shown in Fig. 11, the presence of ITCs modifies interface defects and also to the gate leakage current and,
ST of the device. It is assessed that the donor (acceptor) thereby, degrades the reliability of the device. Moreover, it is
ITCs increase (decrease) ST of PNIN-GAA-TFET by 31.7% obtained that the presence of donor trap charges tremendously
(7.89%) with respect to the ideal device. Moreover, it is degrades IOFF . In addition, IOFF is immune to the presence of
analyzed that, for the ideal device, a change in the ambient acceptor traps. Furthermore, it is explored that the presence
temperature by 41 K alters IOFF by an order of a decade. of ITCs alters superthreshold characteristics marginally. The
However, for the presence of donor (acceptor) ITCs, a change temperature affectability over the device characteristics reveals
in the temperature by 54 K (38 K) alters IOFF by an order a more prominent degradation in subthreshold characteristics
of a decade. Consequently, the presence of donor (acceptor) in comparison with the superthreshold region. In addition,
trap charges enhances (reduces) the temperature sensitivity that PNIN-GAA-TFET shows a positive temperature coefficient
must be detrimental for the devices used for sensors applica- for the complete gate-bias range. Importantly, the temperature
tions, in temperature sensitive environment. For the analog and sensitivity of the device is also altered by the ITCs that is
digital applications, the examination of parasitic capacitances harmful to the device operating in the temperature sensitive
is essential. In order to analyze the reliance of temperature on ambience. The results obtained in this analysis could be
bias-dependent parasitic capacitance, the total gate capacitance beneficial while designing TFETs for a temperature sensitive
as a function of gate bias is examined at various temperatures, environment.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MADAN AND CHAUJAR: NUMERICAL SIMULATION OF N+ SOURCE POCKET PIN-GAA-TFET 7

ACKNOWLEDGMENT [22] G. F. Jiao et al., “New degradation mechanisms and reliability per-
formance in tunneling field effect transistors,” in IEDM Tech. Dig.,
The authors would like to thank the Microelectronics Dec. 2009, pp. 1–4.
Research Laboratory, Department of Engineering Physics, [23] J. Madan and R. Chaujar, “Temperature associated reliability issues of
Delhi Technological University, Delhi, India, to carry out this heterogeneous gate dielectric-gate all around-tunnel FET,” IEEE Trans.
Nanotechnol., 2017, doi: 10.1109/TNANO.2017.2650209.
work. [24] R. Wang et al., “Investigations on line-edge roughness (LER) and line-
R EFERENCES width roughness (LWR) in nanoscale CMOS technology: Part II—
Experimental results and impacts on device variability,” IEEE Trans.
[1] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy- Electron Devices, vol. 60, no. 11, pp. 3676–3682, Nov. 2013.
efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, [25] P. G. D. Agopian et al., “Temperature impact on the tunnel FET off-
2011. state current components,” Solid-State Electron., vol. 78, pp. 141–146,
[2] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-K Dec. 2012.
gate dielectric,” IEEE Trans. Electron Devices, vol. 54, pp. 1725–1733, [26] P.-F. Guo et al., “Tunneling field-effect transistor: Effect of strain and
2007. temperature on tunneling current,” IEEE Electron Device Lett., vol. 30,
[3] Y. Khatami and K. Banerjee, “Steep subthreshold slope n- and no. 9, pp. 981–983, Sep. 2009.
p-type tunnel-FET devices for low-power and energy-efficient digital [27] S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, and S. Datta,
circuits,” IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2752–2761, “Temperature-dependent I-V characteristics of a vertical In0.53 Ga0.47 As
Nov. 2009. tunnel FET,” IEEE Electron Device Lett., vol. 31, no. 6, pp. 564–566,
[4] J. Madan and R. Chaujar, “Gate drain underlapped-PNIN-GAA-TFET Jun. 2010.
for comprehensively upgraded analog/RF performance,” Superlattices [28] Z. X. Chen et al., “Demonstration of tunneling FETs based on highly
Microstruct., vol. 102, pp. 17–26, Feb. 2017. scalable vertical silicon nanowires,” IEEE Electron Device Lett., vol. 30,
[5] J. Madan, R. S. Gupta, and R. Chaujar, “Analytical drain current no. 7, pp. 754–756, Jul. 2009.
formulation for gate dielectric engineered dual material gate-gate all [29] P.-F. Wang et al., “Complementary tunneling transistor for low power
around-tunneling field effect transistor,” Jpn. J. Appl. Phys., vol. 54, application,” Solid-State Electron., vol. 48, no. 12, pp. 2281–2286,
no. 9, p. 094202, 2015. Dec. 2004.
[6] Y. Taur, J. Wu, and J. Min, “Dimensionality dependence of TFET [30] Atlas User’s Manual, Silvaco, Santa Clara, CA, USA, 2010.
performance down to 0.1 V supply voltage,” IEEE Trans. Electron [31] A. Biswas, S. S. Dan, C. Le Royer, W. Grabinski, and A. M. Ionescu,
Devices, vol. 63, no. 2, pp. 877–880, Feb. 2016. “TCAD simulation of SOI TFETs and calibration of non-local band-
[7] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling to-band tunneling model,” Microelectron. Eng., vol. 98, pp. 334–337,
field-effect transistors (TFETs) with subthreshold swing (SS) less than Oct. 2012.
60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–745, [32] W. Cao, C. J. Yao, G. F. Jiao, D. Huang, H. Yu, and M.-F. Li,
Aug. 2007. “Improvement in reliability of tunneling field-effect transistor with
[8] J. Madan and R. Chaujar, “Gate drain-overlapped-asymmetric gate p-n-i-n structure,” IEEE Trans. Electron Devices, vol. 58, no. 7,
dielectric-GAA-TFET: A solution for suppressed ambipolarity and pp. 2122–2126, Jul. 2011.
enhanced ON state behavior,” Appl. Phys. A, Solids Surf., vol. 122, [33] Y. Yang, X. Tong, L.-T. Yang, P.-F. Guo, L. Fan, and Y.-C. Yeo, “Tun-
p. 973, Nov. 2016. neling field-effect transistor: Capacitance components and modeling,”
[9] K. E. Moselund et al., “Lateral InAs/Si p-type tunnel FETs integrated IEEE Electron Device Lett., vol. 31, no. 7, pp. 752–754, Jul. 2010.
on Si—Part 1: Experimental devices,” IEEE Trans. Electron Devices, [34] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “On enhanced
vol. 63, no. 11, pp. 4233–4239, Nov. 2016. Miller capacitance effect in interband tunnel transistors,” IEEE Electron
[10] G. B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, Device Lett., vol. 30, no. 10, pp. 1102–1104, Oct. 2009.
“Optimization of a pocketed dual-metal-gate TFET by means of TCAD [35] Y. P. Varshni, “Temperature dependence of the energy gap in semicon-
simulations accounting for quantization-induced bandgap widening,” ductors,” Physica, vol. 34, no. 1, pp. 149–154, 1967.
IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 44–51, Jan. 2015.
[11] W. Y. Choi and W. Lee, “Hetero-gate-dielectric tunneling field-
effect transistors,” IEEE Trans. Electron Devices, vol. 57, no. 9,
pp. 2317–2319, Sep. 2010.
[12] N. Cui, R. Liang, and J. Xu, “Heteromaterial gate tunnel field effect
transistor with lateral energy band profile modulation,” Appl. Phys. Lett.,
vol. 98, no. 14, p. 142105, 2011.
Jaya Madan (S’14) was born in New Delhi, India,
[13] M. J. Lee and W. Y. Choi, “Effects of device geometry on hetero-gate-
in 1989. She received the B.Sc. degree (Hons.)
dielectric tunneling field-effect transistors,” IEEE Electron Device Lett.,
and M.Sc. degree in electronics from the Uni-
vol. 33, no. 10, pp. 1459–1461, Oct. 2012.
versity of Delhi, New Delhi, India, in 2011 and
[14] V. Nagavarapu, R. Jhaveri, and J. C. S. Woo, “The tunnel source (PNPN)
2013 respectively. She is currently pursuing
n-MOSFET: A novel high performance transistor,” IEEE Trans. Electron
the Ph.D. degree in electronics with the Micro-
Devices, vol. 55, no. 4, pp. 1013–1019, Apr. 2008.
electronics Research Laboratory, Department of
[15] H. Wang et al., “A novel barrier controlled tunnel FET,” IEEE Electron
Engineering Physics, Delhi Technological Uni-
Device Lett., vol. 35, no. 7, pp. 798–800, Jul. 2014.
versity, New Delhi.
[16] A. W. Dey et al., “High-current GaSb/InAs(Sb) nanowire tunnel
field-effect transistors,” IEEE Electron Device Lett., vol. 34, no. 2,
pp. 211–213, Feb. 2013.
[17] S. Blaeser et al., “Line tunneling dominating charge transport in SiGe/Si
heterostructure TFETs,” IEEE Trans. Electron Devices, vol. 63, no. 1,
pp. 4173–4178, Nov. 2016.
[18] Y. Qiu, R. Wang, Q. Huang, and R. Huang, “A comparative study on
the impacts of interface traps on tunneling FET and MOSFET,” IEEE
Trans. Electron Devices, vol. 61, no. 5, pp. 1284–1291, May 2014. Rishu Chaujar (SM’16) received the M.Sc. and
[19] J. Madan and R. Chaujar, “Interfacial charge analysis of heterogeneous Ph.D in Electronics from Delhi University in 2005
gate dielectric-gate all around-tunnel FET for improved device relia- and 2009 respectively. Since 2010, she has been
bility,” IEEE Trans. Device Mater. Rel., vol. 16, no. 2, pp. 227–234, an Assistant Professor with the Department of
Jun. 2016. Engineering Physics, Delhi Technological Uni-
[20] M. G. Pala, D. Esseni, and F. Conzatti, “Impact of interface traps on the versity, New Delhi. She has authored or co-
IV curves of InAs tunnel-FETs and MOSFETs: A full quantum study,” authored more than 175 papers in various inter-
in IEDM Tech. Dig., Dec. 2012, pp. 6.6.1–6.6.4. national and national journals and conferences.
[21] S. Sant et al., “Lateral InAs/Si p-type tunnel FETs integrated on Si— She has supervised around 10-11 M.Tech stu-
Part 2: Simulation study of the impact of interface traps,” IEEE Trans. dents and 6 Ph.D students are presently working
Electron Devices, vol. 63, no. 11, pp. 4240–4247, Nov. 2016. under her guidance.