Reconfigurable Computing CS G553 Dr. A. Amalin Prince BITS - Pilani K K Birla Goa Campus Department of Electrical and Electronics Engineering Lecture — 22 rele eR ltr Heo PMU lg InstantiationObjectives UO After completing this module, you will be able to: © Understand the key benefits provided by the Vivado logic debug feature © List various debugging cores and their functionality © Describe the process of including debug tool sampling cores in the Vivado Design Suite Oo Verification is Critical O Debug and verification can account for over 40% of an — FPGA design time O Serial nature of debug and Design Verification 737) verification can make it difficult and Debug Fim to optimize ie O Inefficient strategy may result in product launch delay Pore nocd o Loss in market share o Loss of first-to-market advantages Design ‘SpecificationBRCM eL-vele te] Challenges accessing internal signals O Limited Internal Visibility 0 How do | access the ‘embedded system bus... O Hard IP Cores © Can't get internal access to... O Full Scan Insertion o Increases overhead... Olt's Too Late Anyway! o Re-spins are ENORMOUSLY expensive O Co-Verification 0 Tools are cumbersome and slow 0 Model DURE ATAATTTAAaS ORequires Extensive Dedicated I/O for Debug, © Driving signals to external I/O introduces additional problems Qlnflexible solution o Difficult or impossible to add additional debug pins if neede QLimited visibility to on-chip activityRecommended Debug Methodology Cl Engineers are trained to solve problems logically © Break @ problem into smaller parts © Simpify by reducing variables & variation © Make a prediction, verify the results © Plan how and where to debug early in the design cycles C FPGA design is an iterative process C1 Debugging a FPGA design is an iterative process: 0 1) Probe: Adding/modify debug probes Fix Bug © 2) Implement: Compile design w/probes Find © 3) Analyze: Look for bugs using probes Bug © 4) Fix: Fix any bugs, repeat as necessary The reconfigurable nature of FPGAs yee facilitates the iterative debug process Xilinx Hardware Solutions for Debugging Designs O Hardware debugging tool © Vivado logic analyzer for hardware © Functionally replaces need for external logic analyzer CO Now included in the Xilinx tool suite ODA single JTAG connection to the PC can be used for ‘© Programming the programmable logic © Hardware debugging oOO Shared across Vivado features © Simulator, Logic Analyzer, ete. © Reduces learning curve © Eases transition between features Co New functionality © Cursors and markers wimeasure 0 Zoom mouse gestures Custom colors ° Find next/previous transition Find signal name Multiple radix selections S Integrated analog plot wirow resize eo 0° 2Vivado Logic Analyzer Feature tcl scripting C Enables automation of logic debug ‘0 Uses common Vivado Tel engine and concepts ‘o Run tests in interactive or Caetano (get targets 9/dstlent plain 1235) = batch mode ad renee reeenes © Save results for future seat viewing esicw -spe_h 0 Allows you to create custom gee ut functions and tests ‘Bout property camec aciee AUTON S12 curren St Set foperty CPE VLE:D aN WE yet probes PEA, © Create repeatable tests © Link custom Tcl to toolbar buttons in Vivado IDE ‘0 More easily integrate into custom test environments enefits of Vivado Logic Debug Simplified Debugging (Single trigger comparator type (a.k.a. “match unit") per PROBE ipariso}) types, bit values 1_N6ICON core instantiation required (1. Most debug parameters are set during runtime © Minimize unnecessary re-implementation Focus on debugging the design, not on the debug core!Benefits of Vivado Logic Debug High-level Debugging O Flexible, targeted probing Debug Probe of HDL design using MARK_DEBUG property Soa) Spot fn C Synthesized design a Schematic _ probing in multiple views 7 . C1 System-level probing ‘ inside of IP integrator sos. view in Vivado IP Come Integrator —— Debug the design at the appropriate = |e level Vivado Integrated Logic Analyzer System C0 Vivado Design Suite debug cores provide internal visibility to all soft IP © Access to hard IP ports © Accesses all the internal signals, interfaces ports and nodes within the programmable logic (ILA v2.x) © Stimulus can be applied using the Virtual /O core (VIO v2.x) Cl Debugging occurs at, or near, system speeds © Debug on-chip using the system clock C1 Minimize pins needed for debugging o Access via the JTAG interface (debug_core_hub)Vivado Logic Debug IP OILA 4.0 © Vivado native Integrated Logic Analyzer debug IP core © Netlist insertion = support o HDL instantiation support OVIO 3.0 © Vivado native Virtual Input / Output debug IP core ‘© HDL instantiation @ . ILA Core 1 Used for monitoring internal programmable logic signals and ports for post-analysis C Multiple configurable ILA trigger units ‘© Configurable trigger input widths and match types for use with different input signals types . [ene CO Separate data and trigger inputs Lo CO Sequential triggering 3 tin CO Storage qualification Tees C0 Trigger out signal for cross-probing cceer001 eats C0 Pre- and post-trigger buffering (capture data te before, during, and after trigger condition is met) sjxissno) sscrobes]0.0) Saeco) be]ae ex.)¢-) C Support for monitoring and driving internal programmable logic signals in "real time" C Probe input unit C Probe output unit Fe poche outta) “KR te, (70) ano | pees cava te Hes nls 0 Besides the IP cores insertion, Vivado logic debugging can be done by making nets in the HDL code using Mark Debug property CO VHDL syntax example attribute mark_debug : string; attribute mark_debug of char_fifo_dout: signal is "true"; C Verilog Syntax example (* mark_debug = “true” *) wire [7:0] char_fifo_dout; @ .ANE CoCoMBI-oL d cellule ma Cole) O Netlist insertion flow (Highly recommended) —— © Most flexible with high predictability © Probing at different design levels (HDL, synthesized design, system design) © Compatible with various tool modes (Project, Non-project) OHDL instantiation OW as © Traditional flow for higtteS{ predictability, moderate flexibility + No longer requires ICON core instance © Probing at HDL design level only o Compatible with various tool modes (Project, Non-project) O Netlist insertion and HDL instantiation flows can be mixed Vivado Debug Tool Access Points O Select Tools > Set up Debug to launch the Vivado Debug Wizard O Debug tab appears in the Synthesized Design view © Click on the Set Up Debug icon to relaunch the wizard + Add signals + Add new ILAs + Create debug core orgort ql + Implement the cores i # aunSelecting Signals to Debug Ci Multiple ways to select nets in Vivado © Netlist view (nets folders) + Each level of logic hierarchy 0 Schematic © Find results Ci Right-click the net and select Mark Debug Ci Nets added to Unassigned Nets folder in the Debug tab view 0 Placeholder for probable nets prior to configuring cores CNet name search also in the Set Up Debug Wizard Debug Tool Configuration O The Vivado tool view displays core content and configuration o CLK, PROBE ‘0 Signal count O Set options for cores and signals in the PropertiesSoftware Deveopment_| Hardware Design Sotmare Devopneet Ki (SDK) yan nad pec 1P HWISW CoNeriction & iP) Mad c-Ualee Cod)ic Uric) eS Ife atv sedO Questions ? “ J O Thank you for your attention