TEA1024/ TEA1124

Zero Voltage Switch with Fixed Ramp

Description
The monolithic integrated bipolar circuit, TEA1024/ synchronized ramp generator with 640 ms (1280 ms)
TEA1124 is a zero voltage switch for triac control in duration (50 Hz). It is suitable for a typical load of 750 W
domestic equipments. It offers not only the control of a (1000 W) meeting the Flicker Standard. (values in
triac in zero crossing mode but also the possibility of brackets relate to TEA1124.)
power control. This is why the IC contains a mains

Features
D Direct supply from the mains D Simple power control
D Definite IC switching characteristics D Integrated ramp generator
D Very few external components D Reference voltage variable by external resistance
D Full wave drive – no dc component in the load circuit D Pulse position optimization
D Current consumption ≤ 1.5 mA
D Output short circuit protected Package: DIP8

Block Diagram
95 10871

D1 1N4007 L

R2 22 kW/ Load
390 kW (Rsync)
R1
2W 1000 W

7 4 C1 100 mF V M=
16 V 230 V ~
1 Ramp generator 6
TEA 1024 – 640 ms Sync. logic Supply TIC
56 kW
TEA 1124 – 1280 ms 236N MT2

Comparator MT1
5 RG
+
Protection
–
Pulse 68 W
min.
amplifier
2 3 8
100 kW
max. 43 kW NC NC N

Figure 1. Typical block diagram – open loop power control

TELEFUNKEN Semiconductors 1 (8)

Rev. A1, 24-May-96
TEA1024/ TEA1124
Power Supply and its Limitations Full-Wave Logic
The voltage limitation contained in the IC allows it to be The full-wave logic ensures that only pairs of pulses can
be released, and that these always begin with the positive
ă
powered from mains via series resistance R1 and recti–
fying diode D1 between Pin 6 (+ Pol/ ) and Pin 4 (–VS). dv/dt. The load is thus switched on for a minimum of one
The capacitor C1 smooths the supply voltage complete mains cycle. This means that the triac receives
(see figure 1). a minimum of two driving pulses, so that the unwanted
d.c. component in the load circuit is definitely eliminated.
An internal temperature-compensated limiting circuit
protects the module from random peaks of voltage on the
Pulse Amplifier
mains, and delivers a defined reference voltage during the The pulse amplifier connected to the output of the full-
negative half-cycle. wave logic circuit, is proof against continuos
short-circuits, and delivers negative output pulses of typ.
Synchronization 75 mA, via an integrated limiting resistance, to Pin 5.

Ramp Generator (Figures 3, 4)

Ramp voltage which is generated in the IC is available not
only at reference Pin 1, but also at the non-inverted input
of the comparator.
The current sink which is controlled by D/A converter
influences the internal reference voltage at Pin 1 specified
by voltage divider. The current sink is turned-off in the
reset state of the D/A converter so that the voltage at Pin 1
is primarily specified via the internal voltage divider
(ramp starting voltage).
In the maximum state of the 4 stage (5 stage – TEA1124)
D/A converter, the current sink overtakes the maximum
current, whereby the ramp’s final (end) voltage has
reached. External resistance Rx, Ry shown in figure 4 are
in position to influence the initial ramp voltage as well as
the ramp amplitude. If the external resistances ratio Rx,
Ry is the same as that of the internal ratio, the ramp
Figure 2. Pulse position optimization
voltage at the beginning remains maintained (constant),
only the amplitude is compressed.
The logic function is synchronized by means of a separate
resistance R2 connected between Pin 7 and phase
(voltage-synchronization). The width of the pulse can be
t
varied between wide limits by choice of Rsync. The larger
the value chosen, the wider the output pulse is on Pin 5. V
1
Automatic optimization of the phase of the pulse is
necessary, since the latching current of the triac exceeds –1.3 V
the steady current by a factor of 3. 2.2 V
The phase of the pulse is chosen so that ca. 1/3 of the pulse –3.8 V
width appears before the transition through null and 2/3 T= 640 ms
after it (see electrical characteristics and figure 2). (T= 1280 ms) 16 stage ramp
95 11410
In order to avoid phase-clipping after the switch-on the
first third of the first pulse is automatically suppressed. Figure 3. Ramp diagram without external circuit

2 (8) TELEFUNKEN Semiconductors

Rev. A1, 24-May-96
 TEA1024/ TEA1124
2
–
Protection
+
GND 6

Rx 50 kW 4 stage
1 ripple counter
D/A converter
23
150 kW
A Divider 7
Ry 22 Period
1:2
D 21 20 ms Sync (50 Hz)
4 (1:4)
20 (40 ms)
–VS Current sink

95 11411

Figure 4. Principle diagram – Generation and evaluation of ramp

Period Firing Pulse Width (Figures 6, 7)

1. The time required for one complete cycle of a regular. It depends on the latching current as well as on the load
repeating signal, function, or series of emends. current of the used triacs.
2. The tune between two consecutive transients of the
pointer or indicating means of an electrical indicating t p [s] + 4 3p f arcsin
IL
P Ǹ2
VM
instrument in the same disdain the rest position.
Something called periodic fine. whereas IL[A] = Latching current of the triac
VM[V]= Mains voltage, effective
Comparator P[W] = Power load
f[1/s] = Mains frequency
The comparison of set value and measured value is
carried out via the two comparator inputs Pin 1 and Pin 2. Firing pulse width is specified through the zero cross over
Here Pin 2 is the inverting input and has a circuit pro- identification which can be influenced by the sync.
tecting it against interference spikes. Figure 5 shows the resistance.
protective circuit of the comparator. Pin 1 is the non-
Ǹ2 sin ǒ w Ǔ
+V
2
R sync [W]
inverting input. M 3 t p – 0.6
–5
–1.4 10 3
1 2.5 10
Ramp
generator where
tp [s] = required ignition pulse width
6

GND
R
Z

T
2 +
–
95 11412

Figure 5. Protective circuit of the comparator

TELEFUNKEN Semiconductors 3 (8)

Rev. A1, 24-May-96
TEA1024/ TEA1124
10.00
Supply Voltage
Vmains = 230 V∼ Due to higher trigger sensitivity of the triac it is supplied
with negative signal. It can be supplied via diode and
series resistance from the negative half wave of the mains.
1.00 An internal parallel controller limits the voltage between
t p ( ms )

Pin 5 and 7 to a typical value of 6.55 V.

IL ( mA) Dimensioning of the Series Resistance

0.10
R1 (Figures 8, 9)
200
100
50
R 1max + 0.85 V 2 –I V Mmin

tot
Smax
–65 W
0.01

96 11939
10 100
P(W)
1000 10000
I tot +I )I )IS P X P(R 1) + (V 2–RV )
M

1
S
2

VM = Mains supply
VS = Limiting voltage of the IC
Figure 6.
Itot = Total current requirement
Ix = Current requirement for external circuit
2.5
VMains=230V X 50

2
40
X
R 2 ( MW )

1.5 VMains=230V
R 1 ( kW )

30

1
20
0.5
10
0
0 200 400 600 800 1000 0
95 11 tp ( ms ) 0 3 6 9 12 15
95 10114 Itot ( mA )
Figure 7.
Figure 8.

6
Ignition (Firing) Current
5
VMains=230V X
The necessary ignition current depends on the specified
triac. With the help of a resistance, it is possible to limit 4
PR1 ( W )

its value:
3

R Gmax [W] [ 5.7 V – V Gmax

I Gmax
–25 W 2

I p [A] + I Gmax
T
tp 1

whereas VG[V]= Gate voltage of the triac 0

IG[A]= Max. gate current 0 3 6 9 12 15
IP[A] = Average gate current requirement
Itot ( mA )
tP[s] = Ignition pulse width
95 10116

T[s] = Duration (of mains frequency) Figure 9.

4 (8) TELEFUNKEN Semiconductors

Rev. A1, 24-May-96
 TEA1024/ TEA1124
Absolute Maximum Ratings
Reference point Pin 6
Parameters Symbol Value Unit
Current consumption Pin 4 –IS 30 mA
t ≤ 10 ms is 150
Sync. current Pin 7 ISync 5 mA
t ≤ 10 ms iSync 40
Comparator input current Pin 2 " II 1 mA
Input voltages Pin 1,4,5 –VI ≤ VS V
Pin 5 +VI ≤ 0.5
Power dissipation
Tamb = 45°C Ptot 400 mW
Tamb = 100°C 125
Junction temperature Tj 125 °C
Ambient temperature range Tamb 0 to 100 °C
Storage temperature range Tstg –40 to + 125 °C

Thermal Resistance
Parameters Symbol Maximum Unit
Junction ambient RthJA 200 K/W

Electrical Characteristics
Supply voltage –VS = 5.6 V, Tamb = 25°C, f = 50 Hz, reference point Pin 6, unless otherwise specified

Parameters Test Conditions / Pins Symbol Min Typ Max Unit

Supply voltage limitation –I4 = 1 mA Pin 4 –VS 5.7 7.4 V
Current consumption Pos. half, cycle Pin 4 –IS 1 mA
Zero cross over
(Pin 5 open) Pin 4 –IS 1
neg. half cycle Pin 4 –IS 1.8
Synchronization Pin 7
Voltage limitation ±I7 = 1 mA "V 1.0 1.8 V
"I
I
Synchronization current 0.15 mA
"I
Sync
Zero cross detection Sync 25 mA
Comparator, figure 5
Input zero voltage Pin 1, 2 V10 10 mV
Input quiescent current Pin 2 IB 1 mA
Common mode input Pin 1, 2 –VIC 1 (VS–1.6) V
range

TELEFUNKEN Semiconductors 5 (8)

Rev. A1, 24-May-96
TEA1024/ TEA1124
Parameters Test Conditions / Pins Symbol Min Typ Max Unit
Ramp generator, figures 3, 4 Pin 1
Period TEA1024 T 640 ms
TEA1124 1280
Step number n 16
Initial voltage –V1 1.2 1.4 1.6 V

ǒ) Ǔ
Final voltage –V1 3.3 3.6 3.9 V
Internal reference V S 2.5% V
4–7.5%
Temperature coefficient of "TC Ref 1.2 mV/K
internal reference
Pulse amplifier Pin 5
Output pulse current VG ≤ 1.5 V –IO 50 100 mA
Output pulse width X
VSync = 230 V , t0 33 ms
R2 = 220 kW t1 65
t2 110

Applications
95 11416
D1 1N4007 L

390 kW/ R2
R1 22 kW/ Load
0.5 W (Rsync) 2W 0.7...1.5 kW

100 mF
VM =
7 4 C1
16 V 230 V ~
Ramp generator 6
1
TEA 1024 – 640 ms Sync. logic Supply TIC
TEA 1124 –1280 ms 236N MT2

Comparator MT1
5 RG
NTC / M87 +
B value = 3474
Protection
– Pulse 68 W
amplifier
R(25) = 10 kW 2 3 8
R(30) = 8 kW
NC NC
R(10) = 20 kW
N

Figure 10. Simple temperature regulation with maximum proportional range

6 (8) TELEFUNKEN Semiconductors

Rev. A1, 24-May-96
 TEA1024/ TEA1124
95 11417
D1 1N4007 L

390 kW/ R2 22 kW/ Load

R1
0.5 W (Rsync) 2W 0.7...1.5 kW

R4 R6 C1 100 mF V M=
7 4
16 V 230 V ~
33 kW 10 kW
1 Ramp generator 6
TEA1024 – 640 ms Sync. logic Supply TIC
Rp TEA1124 –1280 ms 236N MT2
50 kW
Comparator MT1
5 RG
+
NTC / M87
Protection Pulse 68 W
B value = 3474 – amplifier
R(25) = 10 kW 2
R12 3 8
R(30) = 8 kW
2.2 kW NC NC N
R(10) = 20 kW

Figure 11. Temperature regulation with proportional range, 10 to 30 °C/ 640 ms ramp cycle

Dimensions in mm
Package: DIP8

TELEFUNKEN Semiconductors 7 (8)

Rev. A1, 24-May-96
TEA1024/ TEA1124
Ozone Depleting Substances Policy Statement

It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances ( ODSs).

The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and
forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban
on these substances.

TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of
continuous improvements to eliminate the use of ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively

2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency ( EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively.

TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain
such substances.

We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized
application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of,
directly or indirectly, any claim of personal damage, injury or death associated with such unintended or
unauthorized use.

TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423

8 (8) TELEFUNKEN Semiconductors

Rev. A1, 24-May-96