NCP1581

High Frequency Synchronous

Step Down PWM Controller
for Tracking Applications
The NCP1581 controller IC is designed to provide a simple
synchronous buck regulator for on−board DC to DC applications in a http://onsemi.com
14−pin SOIC. The NCP1581 is designed specifically for tracking
applications by providing the track input. MARKING
The NCP1581 operates at a fixed internal 400 kHz switching SOIC−14 DIAGRAM
frequency allowing the use of small external components. The device 14 D SUFFIX
1 CASE 751A
features a programmable soft start set by an external capacitor, NCP1581G
under−voltage lockout and output under−voltage detection that latches A = Assembly Location AWLYWW
off the device when an output short is detected. WL = Wafer Lot
Y = Year 1
Features WW = Work Week
G = Pb−Free Package
• Power up Sequencing / Tracking
• Enable Input PIN CONNECTIONS
• Internal 400 kHz Oscillator 1
FB NC
• Programmable Soft−Start
• Fixed Frequency Voltage Mode VP SS

• Voltage Mode Adaptive Deadtime NC COMP

• This is a Pb−Free Device VCC NC

NC VC
Applications
LDRV HDRV
• Tracking Applications
• Game Consoles GND PGND

• Computing Peripheral Voltage Regulators (Top View)

• Graphics Cards
• General DC to DC Converters ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

NCP1581

Figure 1. Typical Application Circuit

 Semiconductor Components Industries, LLC, 2010 1 Publication Order Number:

January, 2010 − Rev. 0 NCP1581/D
 Block Diagram
Circuit Description:
VCC VC

POR
V CC UVLO

GND VP/EN Delay

0.65V FAULT HDRV
Figure 2. Simplified Block Diagram

V BIAS
2V
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Oscillator S PWM
POR
2 2 uA Q

NCP1581
CT R
Reset Dom
2

SS 64uA Max VCC

2V 2V
Error
POR SS
Comparator
Error Amp
POR Delay LDRV
VP/EN R POR
25k FAULT
FB Q
25k
COMP S PGND
0.4V
 NCP1581

Table 1. PIN FUNCTION DESCRIPTION

Pin Name Description
1 FB Inverting input to the error amplifier. This pin is connected to the output of the regulator via resistor divider
to set the output voltage and provide feedback to the error amplifier.

2 VP/EN Dual function pin. Non inverting input to the error amplifier. Enable input.
3 NC No Connect
4 VCC This pin provides power for the internal blocks of the IC as well as powers the low side driver. A minimum
of 0.1 mF, high frequency capacitor must be connected from this pin to power ground.

5 NC No Connect
6 LDRV Output driver for low side MOSFET.
7 GND IC ground for internal control circuitry.
8 PGND Power Ground. This pin serves as a separate ground for the MOSFET drivers and should be connected to
the system’s power ground plane.

9 HDRV Output driver for high side MOSFET. The negative voltage at this pin may cause instability for the gate
drive circuit. To prevent this, a low forward voltage drop diode (e.g. BAT54 or 1N4148) is required
between this pin and Power Ground.
10 VC This pin powers the high side driver.
11 NC No Connect
12 COMP Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to
ground to provide loop compensation.

13 SS Soft start. This pin provides user programmable soft−start function. Connect an external capacitor from
this pin to ground to set the start up time of the output voltage.

14 NC No Connect

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Symbol min max Unit
Main Supply Voltage Input VCC −0.3 20 V
Main Supply Voltage Input 200 ns wide spikes, 400 kHz VCC_SPK −0.3 22 V
Supply Voltage for the High side driver VC −0.3 20 V
Supply Voltage for the High side driver 200 ns wide spikes, 400 kHz VC_SPK −0.3 22 V
VP/EN pin Voltage VP/EN −0.3 10 or VCC (Note 1) V
FB pin Voltage VFB −0.3 10 or VCC (Note 1) V
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient (Note 2) Rthja 90 K/W
Storage Temperature Range Tstg −65 to 150 °C
Junction Operating Temperature TJ 0 to 150 °C
ESD Withstand Voltage (Note 3) VESD
Human Body Model 2.0 kV
Machine Model 200 V
Moisture Sensitivity Level MSL JEDEC Level 1 @ 260°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: All voltages are referenced to GND pin unless otherwise stated.
1. Maximum = 10 V or VCC, whichever is lower.
2. JEDEC High−K model
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) ±200 V per JEDEC standard: JESD22−A115

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 NCP1581

Table 3. RECOMMENDED OPERATING CONDITIONS

Symbol Definition Min Max Units
VCC Supply Voltage 7 20 V
VC Supply Voltage Converter Voltage + 5 V, (Note 4) 20 V
TJ Junction Temperature 0 125 °C
NOTE: All voltages are referenced to GND pin.
4. Depend on high side MOSFET VGS

Table 4. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0°C < TJ < 125°C
Parameter Symbol Test Condition Min Typ Max Units
SUPPLY CURRENT
VCC Supply Current (Static) ICC(Static) VP/EN = 0 V, No Switching 1.5 3 mA
VCC Supply Current (Dynamic) ICC(Dynamic) fSW = 400 kHz, CL = 1.5 nF 10 15 mA
VC Supply Current (Static) IC(Static) VP/EN = 0 V, No Switching 0.05 0.1 mA
VC Supply Current (Dynamic) IC(Dynamic) fSW = 400 kHz, CL = 1.5 nF 9 15 mA
UNDER VOLTAGE LOCKOUT
VCC−Start−Threshold VCC UVLO (R) Supply voltage Rising 6.3 6.6 7.0 V
VCC−Stop−Threshold VCC UVLO (F) Supply voltage Falling 6.0 6.3 6.6 V
VCC−Hysteresis VCC (Hyst) Supply ramping up and down 0.2 0.3 0.4 V
Enable−Start−Threshold VP/EN UVLO (R) Supply voltage Rising 0.6 0.65 0.7 V
Enable−Stop−Threshold VP/EN UVLO (F) Supply voltage Falling 0.56 0.6 0.66 V
Enable−Hysteresis VP/EN (Hyst) Supply ramping up and down 40 mV
FB UVLO VFB UVLO FB ramping down 0.3 0.4 0.5 V
OSCILLATOR
Frequency fSW 370 400 430 kHz
Ramp Amplitude VRAMP (Note 5) 1.25 V
Min Duty Cycle DMIN VFB =1V, VP/EN = 0.8 V 0 %
Max Duty Cycle DMAX fSW = 400 kHz, VFB = 0.6 V, VP/EN = 0.8 V 83 85 95 %
ERROR AMPLIFIER
FB Input Bias Current IFB1 VSS = 3 V −0.1 −0.5 mA
FB Input Bias current IFB2 VSS = 0 V 64 mA
VP/EN Input Bias Current IVP/EN VSS = 3 V −0.1 −0.5 mA
Transconductance gm 440 1300 mmho
Input Offset Voltage VOS VP/EN = 0.8 V, VCOMP = 2.0 V −6 0 +6 mV
VP/EN Common Mode Range VCOMN (Note 5) 0.6 1.5 V
ERROR AMPLIFIER DESIGN SPECIFICATIONS
OTA output current IOTA (SINK) VFB = 1.2 V, VP/EN = 1.0 V, 100 mA
VCOMP = 2.0 V, (Note 5)

OTA output current IOTA (SOURCE) VFB = 0.8 V, VP/EN = 1.0 V, 100 mA
VCOMP = 2.0 V, (Note 5)
5. Guaranteed by Design but not tested in production.

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Table 5. ELECTRICAL SPECIFICATIONS Unless otherwise specified, VCC = VC = 12 V, 0°C < TJ < 125°C
Parameter Symbol Test Condition Min Typ Max Units
SOFT START
Soft Start Current ISS VSS = 0 V 12 22 32 mA
Soft Start Turn On SS (on) 1.8 2 2.2 V
OUTPUT DRIVERS
LO Drive Rise Time tr(Lo) CL = 1.5 nF (See Figure 3) 20 50 ns
HI Drive Rise Time tr(Hi) CL = 1.5 nF (See Figure 3) 30 60 ns
LO Drive Fall Time tf(Lo) CL = 1.5 nF (See Figure 3) 20 50 ns
HI Drive Fall Time tf(Hi) CL = 1.5 nF (See Figure 3) 30 60 ns
Dead Band Time tDEAD (See Figure 3) 35 45 90 ns
Adaptive DBT Level VADT 2.0 V

tr(Hi) tf(Hi)

9V

High Side Driver

(HDRV)
tDEAD tDEAD

2V

tr(Lo) tf(Lo)

9V

Low Side Driver

(LDRV)

2V

Figure 3. Definition of Rise/Fall Time and Deadband Time

TYPICAL CHARACTERISTICS
7.00
6.90
6.80
6.70
6.60 Rising
VCC (V)

6.50
6.40
6.30 Falling
6.20
6.10
6.00
0 20 40 60 80 100 120
TEMPERATURE (°C)
Figure 4. VCC UVLO

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 NCP1581

TYPICAL CHARACTERISTICS
0.70 0.50
0.48
0.68
0.46
0.66 Rising 0.44
0.42
VP/EN (V)

VFB (V)
0.64
0.40
0.62 Falling
0.38

0.60 0.36
0.34
0.58
0.32
0.56 0.30
0 20 40 60 80 100 120 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 5. VP/EN UVLO Figure 6. FB UVLO

95 440

93 430

420
91
410
DMAX (%)

fSW (kHz)

89
400
87
390
85
380
83 370
81 360
0 20 40 60 80 100 120 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 7. Maximum Duty Cycle Figure 8. Switching Frequency

1300 90
1200
80
1100
1000 70
gm (mmho)

Low to High
900
t (ns)

60
800
High to Low
700 50

600
40
500
400 30
0 20 40 60 80 100 120 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 9. Error Amplifier Transconductance Figure 10. Deadtime

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 NCP1581

Detailed Description

Introduction The value of the output capacitor should be calculated

The NCP1581 is voltage mode PWM synchronous using the following equation:
controller designated to drive two external N-channel DI L
MOSFETs. Switching frequency is fixed at 400 kHz. Output C OUT w (eq. 3)
8 @ f SW @ (DV OUT * DI L @ ESR)
voltage is determined by feedback resistor divider and
external reference voltage. Reference voltage input can be For a higher switching frequency, it is suitable to use a
used to enabling and disabling operation and for tracking multilayer ceramic capacitor (MLCC) with very low ESR.
function. The advantages are small size, low output voltage ripple and
fast transient response. The disadvantage of the MLCC type
Under-Voltage Lockout is the requirement to use a Type III compensation network.
The undervoltage lockout circuit ensures that the IC does
not start and work until VCC and VP/EN are over set Input Capacitor Selection
thresholds. If these conditions are not fulfilled output drivers The input capacitor is used to supply current pulses while
are in the off state. the high side MOSFET is on. When the MOSFET is off, the
input capacitor is being charged. The value of this capacitor
Disable Function can be selected with the Equation (4):
The output voltage can be disabled by pulling the VP/EN
pin below 0.6 V. At this time are output drivers in the off
state.
I OUT @
VOUT
VIN
ǒ
@ 1*
VOUT
VIN
Ǔ (eq. 4)
C IN w
f SW @ DV IN
Output Voltage
Output voltage can be set by an external resistor divider where DVIN is the input voltage ripple and the
and external reference voltage at VP/EN pin according to recommended value is about 2–5% of VIN. The input
Equation (1): capacitor must be able to handle the input ripple current. Its
value should be calculated using Equation (5):
V OUT + V PńEN @ 1 ) R1ǒ Ǔ
Ǹ
(eq. 1)
R2
where VP/EN is the external reference voltage at VP/EN pin ǒ
V OUT @ 1 *
VOUT
V IN
Ǔ (eq. 5)
that is connected to noninverting input of error amplifier. R1 I RMS + I OUT @
V IN
and R2 resistors create voltage divider from output to FB pin
that is connected to inverting input of error amplifier.
Absolute values of resistors R1 and R2 depend on the Power MOSFET Selection
compensation network type. See discussion of The NCP1581 uses two N-channel MOSFETs. They can
compensation description for details. be primarily selected according to RDS(ON), maximum drain
to source voltage, and gate charge. RDS(ON) impacts
Inductor Selection conductive losses and gate charge impacts switching losses.
The inductor selection is based on the output power, The low side MOSFET is selected primarily for conduction
frequency, input and output voltages, and efficiency losses, and the high side MOSFET is selected to reduce
requirements. High inductor values cause low current switching losses especially when the output voltage is less
ripple, slower transient response, higher efficiency and than 30% of the input voltage. The drain to source
increased size. Inductor design can be reduced to desired breakdown voltage must be higher than the maximum input
maximum current ripple in the inductor. It is good to have voltage. Conductive power losses can be calculated using
current ripple (DILmax) between 20% and 50% of the output the following Equations (6) and (7):
current. V OUT
For a buck converter, the inductor should be chosen P COND−HIGHFET + I OUT 2 @ R DS(ON) @ (eq. 6)
V IN
according to Equation (2).

L+ ǒ V OUT
f SW @ DI Lmax
Ǔǒ 1*
V OUT
V INmax
Ǔ (eq. 2) P COND−LOWFET + I OUT 2 @ R DS(ON) @ 1 * ǒ V OUT
V IN
Ǔ (eq. 7)

Switching losses are dependent on the drain to source

Output Capacitor Selection voltage at turn-off state, output current, and switch-on and
The output voltage ripple and transient requirements switch-off times, as is shown by Equation (8).
determine the output capacitor type and value. The V DS(OFF)
important parameter for the selection of the output capacitor P SW + @ (t ON ) t OFF) @ f SW @ I OUT (eq. 8)
2
is equivalent serial resistance (ESR). If the capacitor has low
tON and tOFF times are dependent on the transistor gate
ESR, it often has sufficient capacity for filtering as well as
charge.
an adequate RMS current rating.

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 NCP1581

The MOSFET output capacitance loss is caused by the that of the body diode, and reverse recovery time (trr) should
charging and discharging during the switching process and be lower then that of the body diode. The Schottky diode’s
can be computed using Equation (9). capacitance loss can be calculated as shown in
C OSS @ V IN 2 @ f SW Equation (11).
P COSS + (eq. 9)
2 C schottky @ V IN 2 @ f SW
P C(schottky) + (eq. 11)
where COSS = CDS + CGS. 2
Some power dissipation is caused by the reverse recovery
Adaptive Deadtime
charge in the low side MOSFET body diode, which conducts
The NCP1581 includes voltage mode adaptive dead time
at dead time. This charge is needed to close the diode. The
feature. This block waits for full turn off of the one of
current from the input power supply flows through the high
MOSFETs before the second one can be turned on.
side MOSFET to the low side MOSFET body diode. This
Detection is based on driver voltage, when this voltage drops
power dissipation can be calculated using the following
below VADT second driver can be turned on. There is fixed
Equation (10):
time tDEAD between turn off detection and internal logical
P QRR + Q RR @ V IN @ f SW (eq. 10) turn on signal that increase safety. There can’t be used
QRR is the diode recovery charge as given in the additional gate resistors due to voltage base detection,
manufacturer’s datasheet. For some types of MOSFETs, this because these resistors would create voltage divider with
dissipation may be dominant at high input voltages. It is driver’s pull down transistor and correct turn off detection
necessary to take care when selecting a MOSFET. An is impossible. Gate resistors may be used only if MOSFETs
external Schottky diode across the low side MOSFET can be turn off time is at all operation conditions shorter than
used to eliminate the reverse recovery charge power loss. tDEAD. MOSFETs’ timing diagram can be seen at Figure 11.
The Schottky diode’s forward voltage should be lower than

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 NCP1581

tDEAD tDEAD

High Side
Logic

Signal

Low Side

Logic

Signal

HDRV

VADT

LDRV

VADT

t d (on ) tf
R DSmax

High Side

MOSFET

R DS
R DS (ON )min
tr t d (off )

tr tf

R DSmax

Low Side

MOSFET

R DS
R DS (ON )min

t d (on ) t d (off)

Figure 11. MOSFETs Timing Diagram

Soft Start means that the NCP1581 is in a shutdown state. The SS pin
The soft start time is set by a capacitor connected between voltage (0 V to 2 V) controls the internal current source
the SS pin and ground. This function is used for controlling (64 mA to 0 mA) with a negative linear characteristic. This
the output voltage slope and limiting start-up currents. The current source injects current into the resistor (25 kW)
start-up sequence initiates when the Power On Ready (POR) connected between the FB pin and the negative input of the
internal signal rises to logic level high. That means the error amplifier and into the external feedback resistor
supply voltage and VP/EN voltage are over the set thresholds. network. Voltage drop on these resistors is over 1.6 V, which
The soft start capacitor is charged by a 22 mA current source. is enough to force the error amplifier into a negative
If POR is low, the SS pin is internally pulled to GND, which saturation state and to block switching.

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 NCP1581

When the soft start pin reaches around 1.2 V (exact value The soft start time must be at least 10 times longer than the
depends on feedback and compensation network and on the time needed to charge the compensation network from the
soft start capacitor; a larger soft start capacitor and a lower output of the error amplifier. If the soft start time is not long
compensation capacity decrease this level), the IC starts enough, the soft start sequence would be faster than the
switching. The impact of the controlled current source charging compensation network and the IC would start
decreases and the output voltage starts to rise. When the soft without slowly increasing the output voltage. The soft start
start capacitor voltage reaches 2 V, the output voltage is at capacitance can be calculated using Equation 12:
nominal value. C SS + 22 @ 10 −6 @ T SS (eq. 12)

VCC = VC

VIN

VP_EN

POR

3V

VSS 2V
1V
0V

VOUT

64 mA
Internal IFB

Vneg_error_amp >1.6 V
VP/EN

VP/EN
VFB

0V

Figure 12. Start-up Sequence

Start to Pre-biased Output

The NCP1581 is able to start up into a pre-biased output not discharged by the low side MOSFET (current flows
capacitor. The low side MOSFET does not turn on before the through low side MOSFET body diode) until the soft start
output voltage is at set value. During this time, the energy is sequence ends.

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 NCP1581

Vout

3V
VSS
2V
1V

VLDRV

VHDRV

Figure 13. Start-up to Pre-biased Output

Short Circuit Protection pin is comparator that compares FB voltage to 0.4 V. If FB

The output of convertor with NCP1581 is protected voltage is below 0.4 V then IC goes to latch state and switch
against short circuit conditions. This protection is sensing output drivers to off state. Latch state can be released by
output voltage through feedback divider on FB pin. On this decrease VCC or VP/EN voltage below threshold.

VCC or
VP/EN

Threshold

Vout
Output
shorted

VSS

VLDRV

VHDRV

Figure 14. Short Circuit Protection (Start Up,

Short, Latch, Latch Release and New Start-up)

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 NCP1581

Compensation Circuit One zero of this LC filter is given by the output

The NCP1581 is a voltage mode buck converter with a capacitance and output capacitor ESR. Its value can be
transconductance error amplifier compensated by an calculated using the following equation:
external compensation network. Compensation is needed to 1
achieve accurate output voltage regulation and fast transient f Z0 + (eq. 14)
2 @ p @ C OUT @ ESR
response. The goal of the compensation circuit is to provide
The next parameter that must be chosen is the zero
a loop gain function with the highest crossing frequency and
crossover frequency f0. It can be chosen to be 1/10–1/5 of the
adequate phase margin (minimally 45°).
switching frequency. These three parameters show the
The transfer function of the power stage (the output LC
necessary type of compensation that can be selected from
filter) is a double pole system. The resonance frequency of
Table 6.
this filter is expressed as follows:
f PO + 1
(eq. 13)
2 @ p @ ǸL @ C OUT

Table 6. COMPENSATION TYPES

Zero Crossover Frequency Condition Compensation Type Typical Output Capacitor Type
fP0 < fZ0< f0 < fSW/2 Type II (PI) Electrolytic, Tantalum
fP0 < f0< fZ0 < fSW/2 Type III (PID) Method I Tantalum, Ceramic
fP0 < f0 < fSW/2 < fZ0 Type III (PID) Method II Ceramic

Compensation Type II (PI) Compensation Type III (PID)

This compensation is suitable for low-cost electrolytic Tantalum and ceramic capacitors have lower ESR than
capacitors. The zero created by the capacitor’s ESR is a few electrolytic capacitors, so the zero of the output LC filter
kHz, and the zero crossover frequency is chosen to be 1/10 goes to a higher frequency above the zero crossover
of the switching frequency. Components of the PI frequency. This situation needs to be compensated by the
compensation (Figure 15) network can be specified by the PID compensation network that is shown in Figure 16.
following equations: VOUT
VOUT CC2

RFB1
R1
R1
*Optional CFB1
− RC1 CC1
OTA
+
VP/EN
RC1 −
R2 OTA
CC2* +
CC1 R2 VP/EN

Figure 15. PI compensation (Type II) Figure 16. PID Compensation (Type III)

There are two methods to select the zeros and poles of the
2 @ p @ f 0 @ L @ V RAMP @ V OUT
R C1 + compensation network. The first one (method I) is usable for
ESR @ V IN @ V PńEN @ gm tantalum output capacitors, which have a higher ESR than
C C1 + 1 ceramics, and its zeros and poles can be calculated as shown
0.75 @ 2 @ p @ f P0 @ R C1 below:
(eq. 15)
C C2 + 1 f Z1 + 0.75 @ f P0
p @ R C1 @ f SW
f Z2 + f P0
V OUT * V PńEN (eq. 16)
R1 + @ R2 f P2 + f Z0
V PńEN
f SW
VRAMP is the peak-to-peak voltage of the oscillator ramp, f P3 +
2
and gm is the transconductance error amplifier gain.
Capacitor CC2 is optional.

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 NCP1581

The second one (method II) is for ceramic capacitors: The remaining calculations are the same for both
methods.
f Z2 + f 0 @ Ǹ 1 * sin q max
1 ) sin q max 2
R C1 uu gm

f P2 + f 0 @ Ǹ 1 ) sin q max
1 * sin q max
(eq. 17)
C C1 + 1
2 @ p @ f Z1 @ R C1

C C2 + 1
f Z1 + 0.5 @ f Z2 (eq. 18)
2 @ p @ f P3 @ R C1
f P3 + 0.5 @ f SW 2 @ p @ f 0 @ L @ V RAMP @ C OUT
C FB1 +
V IN @ R C1

R FB1 + 1
2 @ p @ C FB1 @ f P2

R1 + 1 * R FB1
2 @ p @ C FB1 @ f Z2
V PńEN
R2 + @ R1
V OUT * V PńEN
To check the design of this compensation network, the
following equation must be true:
R1 @ R2 @ R FB1 1 (eq. 19)
u gm
R1 @ R FB1 ) R2 @ R FB1 ) R1 @ R2
If it is not true, then a higher value of RC1 must be selected.

ORDERING INFORMATION
Device Package Shipping†
NCP1581DR2G SOIC−14 2500 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.

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 NCP1581

PACKAGE DIMENSIONS

SOIC−14
CASE 751A−03
NOTES:
ISSUE J 1. DIMENSIONING AND TOLERANCING PER
−A− ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
14 8 3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B− P 7 PL
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
0.25 (0.010) M B M DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
1 7 CONDITION.

G MILLIMETERS INCHES
R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
−T− F 0.40 1.25 0.016 0.049
K M J
SEATING D 14 PL G 1.27 BSC 0.050 BSC
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

SOLDERING FOOTPRINT*
7X
7.04 14X
1.52
1
14X
0.58

1.27
PITCH

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
Email: orderlit@onsemi.com Phone: 81−3−5773−3850 Sales Representative

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