Drain Current and Short Channel Effects Modeling in

Junctionless Nanowire Transistors

Renan D. Trevisoli, Rodrigo T. Doria, Michelly de Souza, and Marcelo A. Pavanello

Department of Electrical Engineering, Centro Universitario da FEI, Sao Bernardo do Campo, Brazil
e-mail: renantd@fei.edu.br

abstraCt1

Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they
provide a great scalability without the need for rigorously controlled doping techniques. In this work, the
modeling of triple-gate JNTs is addressed, focusing on the short-channel effects. Analytical expressions
for the subthreshold slope, threshold voltage roll-off and drain induced barrier lowering are presented.
The model is validated using tridimensional numerical simulations.

Index terms: Junctionless Nanowire Transistors, Analytical Model, Subthreshold Slope, Drain Induced
Barrier Lowering .

I. IntroduCtIon an accumulation layer and bulk conduction. However,

as stated by Kranti et al. [20], the JNT operates mainly
Planar MOS devices miniaturization becomes in the partial depletion regime with a reduced electric
quite challenging for transistors with reduced channel field [21], while the AMSOI works most of time in
length due to the loss of gate control over the channel accumulation regime with a higher electric field. Also,
charges. As an alternative, multi-gate devices have been the bulk current in JNTs is higher than in the AMSOI
developed due to the better electrostatic control of the owing to the heavier doping concentration. A sche-
charges, which leads to a reduction of the short-chan- matic view of a triple-gate JNT is presented in Fig. 1,
nel effects [1-6]. However, for devices with extremely where the silicon nanowire heigth (H) and width (W),
reduced channel length, it is needed the formation of the gate oxide thickness (tox), the channel length (L)
ultra-sharp junctions with a high process complexity at and the buried oxide thickness (tBox) are indicated.
source/channel and drain/channel interfaces. In order
to address this issue, Junctionless Nanowire Transistors
(JNTs) have been proposed [7-11] and have been the
focus of several recent studies [12-18].
The JNT is a heavily-doped silicon nanowire sur-
rounded by the gate stack. The doping distribution is
constant from source to drain with the same doping el-
ement and concentration. Therefore, there are no dop-
ing gradients, eliminating impurity diffusion-related
problems [7]. For an nMOS device an n-type element
is used, whereas a p-type dopant is used in a pMOS Figure 1. Schematic view of a triplel-gate Junctionless Nanowire
Transistor.
device. The Junctionless transistor works similarly to
an accumulation mode SOI device (AMSOI) [19]. For
gate voltages (VG) lower than the threshold voltage The modeling of junctionless devices has been
(VTH), the silicon nanowire is fully depleted such that the focus of several recent studies [14-15,22-23], how-
there is only a small drain current due to the diffusion ever, most of them are based on cylindrical, double-gate
of carriers. For gate voltages slightly higher than VTH, or planar devices. In this work, an analytical model for
the current flows through drift in a neutral channel at triple-gate devices is derived from the solution of the
the center of the device whereas for VG higher than the Poisson equation for long channel devices and a correc-
flatband voltage (VFB), the current flows through both tion for short channel effects is included in the model.
116 Journal of Integrated Circuits and Systems 2013; v.8 / n.2:116-124
 Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

Analytical expressions for the subthreshold slope (S), current that flows through the device. The voltages VA
threshold voltage roll-off (VTH,roll-off) and drain induced and VB represent the voltages at the points A and B,
barrier lowering (DIBL) are also proposed. respectively.

II. long-Channel draIn Current Model

derIVatIon
The charge density per unit of length Q1, which
In Fig. 2, a representation of the longitudinal is related to the conduction in both accumulation layer
section of a n-type JNT is presented, considering that and body, can be described as
the biases VG and VD are applied at the gate and at the
drain (the source is grounded), respectively. In the
region between 0 ≤ y ≤ A, there is the conduction
through both accumulation layer and bulk whereas for where Qt = (q.ND.H.W), ND is the donor dop-
A < y ≤ B there is only bulk conduction. In case of A ing concentration, Cox is the gate capacitance per unit
= L, the whole channel present an accumulation layer of length and q is the electron charge. The second term
whereas if A = 0, there is only the bulk conduction. If of (3) represents the accumulation layer formed at the
B = L, there is no pinch-off, i.e. the device is not in sat- interface silicon/gate oxide whereas the first one is re-
uration. For B lower than L, there is a depletion region lated to the bulk charge.
between the drain and the channel, which is induced by Eq. (3) can be integrated from 0 to VA as shown
the drain potential, similarly to an inversion-mode de- in (2), resulting in the component I1 of the current:
vice. The distance between B and L leads to a reduction

In order to obtain the charge Q2, which is re-

lated only to bulk conduction, the two-dimensional
Poisson equation must be solved:

Figure 2. Longitudinal-section of a Junctionless Nanowire Transistor.

where Φ is the potential, x and z are the axes in
of the effective channel length which is modulated by width and height directions, respectively, and εSi is the sili-
the drain bias. This variation of B degrades (increases) con permittivity. The carrier density has been neglected in
the output conductance of the devices and is especially (5) once the bulk charge is controlled by the depletion.
important for short-channel transistors. The approximation that the potential varies sim-
The drain current can be obtained using the ilarly in both x and z directions (dΦ/dx = dΦ/dz) has
equation: been used in order to solve (5). This approximation
has already been used in [24-26]. The center potential
at the source side of the device has been considered as
zero, since it is connected directly to the ground (no
junctions). The electric field has also been considered
as zero at the center. Eq. (5) can be integrated follow-
where µn is the electron mobility, Q is conduc- ing these boundary conditions such that the depletion
tion charge per unit of length and Vy is the voltage at a charge (QDepl) can be obtained by [24]
point y along the channel.

From Fig. 2, it can be seen that the charge Q can

be considered separately in each region of the device
depending on the conduction regime: Q1 for 0 ≤ y ≤
A and Q2 for A< y ≤ B. Thus, the drain current can
be obtained through the integration of (2), where the where α = εSi q ND (2H + W)2/4.
first term results in the current I1 whereas the second The total bulk conduction charge can be ob-
results in I2. The sum ID = I1 + I2 is the total drain tained by the difference of the charge Qt and the de-

Journal of Integrated Circuits and Systems 2013; v.8 / n.2:116-124 117

Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

pleted charge (Q2 = Qt – QDepl). Therefore, the charge

where K 3 = −4 ì n α /( 3L) , K 2 = ì n (2α / Cox + Qt ) / L , K1 = 2 vsat α and
Q2 can be integrated as shown in (2), resulting in the
component I2 of the drain current
ìn  4 α 2  2α  α L v sat  C 
K0 =  −  + Qt  +  + Qt (VG − VFB ) + ox (VG − VFB ) 2 
. L  3 C ox
3
C
 ox C
 ox
2
ì 
 2 

The saturation voltage is obtained by

It is worth mentioning that the minimum satu-

ration voltage has been limited in the thermal voltage
III. Voltages VA and VB (ft) as in a planar MOSFET [28]. For the subthreshold
regime, it was considered that the current presents an ex-
The voltage at the point VA represents the transi- ponential dependence on the gate voltage, calculated by
tion between the bulk conduction regime and the accu-
mulation layer plus bulk conduction regime. This tran-
sition occurs around Vy = VG – VFB for VG > VFB. For
VG < VFB there is only bulk conduction, which means
where n is the body effect factor, which is close
that VA equals the source voltage (VS) in this condi-
to the unit for JNTs, and VGS is the voltage applied be-
tion. For VG > VFB, an accumulation layer is formed
tween the gate and the source.
at least at the source side of the channel and, depend-
ing on VG and VD, this accumulation layer may extend
In (12), a smooth function is used to the volt-
through the whole channel. The maximum value that
age VG in order to guarantee the continuity of the cur-
the voltage at the point A may assume is VB, which
rent at the transition between subthreshold and above
would mean that the accumulation layer is formed
threshold regions, described by
from source to drain. Therefore, VA­ can vary between
two well-defined points (VS and VB) depending on the
applied biases. In order to have a smooth transition
between bulk and accumulation layer regimes, equa-
tion (8) has been used for VA, where A1 controls the
smoothness and have been set to 6. where A3 controls the transition and has been set
to 12 and VTH is calculated by [24]

The voltage at the point B represents the effec-

tive drain-source voltage (VDSe), which values VD until
the device reaches saturation. Therefore, to limit the
maximum VDSe in the saturation voltage (VDsat), the IV. Model Validation for Long-Channel
smooth function was used: Devices

In order to validate the model for long channel

 ln[1 + exp( A2 (1 − VD / VDsat ))]  . (9)
VDSe = VB = VDsat 1 −  devices, three-dimensional TCAD simulations of n-
 ln(1 + exp( A2 )  type devices have been performed with Synopsys tools
[29-30]. The simulated JNTs present nanowire height
where A2 is a fitting parameter that controls the and width of 10 nm, gate oxide thickness of 2 nm, dop-
transition from triode to saturation and has been set to 4. ing concentration of ND = 1 × 1019 cm-3 and channel
length of 1 µm. P+ polysilicon has been used as gate
To obtain the saturation voltage, the relation material. The low field mobility has been considered
IDsat = Qsat.vsat, where IDsat is the saturation current, constant and equal to 100 cm2/V.s.
Qsat is the charge density per unit of length in the satu- In Fig. 3, the drain current in linear and loga-
ration condition and vsat is the velocity saturation, has rithm scales and the transconductance (gm = dID/dVG)
been used [27]. Combining equations (4), (6) and are presented as a function of the gate voltage for sev-
(7) with the saturation relation, VDsat can be obtained eral drain biases. From this figure, it is clear that the
through the solution of the polynomial equation: drain current and its derivative are correctly predicted
by the model in both subthreshold and above thresh-
K 3 .w 3 + K 2 .w 2 + K1 .w + K 0 = 0 , (10)

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 Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

2.4 Symbols - Simulation 10-5 The model has been also compared to experi-
VD = 0.05, 1 V
Lines - Model
mental data. The devices were fabricated according [7]
2.0 and present H = tox = 10 nm, doping concentration
Drain current [µA]

10-7

Drain current [A]

of 1 × 1019 cm-3 and an effective width of 20 nm. The
1.6
low field mobility has been calculated considering the
VD = 0.05, 0.1, 10-9
1.2 lattice and ionized impurities scattering [31] and carri-
0.2, 0.5, 1 V er-carrier scattering [32]. The series resistance has been
0.8 10-11 taken into account iteratively considering source/drain
0.4 length of 150 nm each. In Fig. 5, the drain current (A)
10-13 and the transconductance (B) are presented as a func-
0.0 tion of the gate voltage for different temperatures rang-
10-15 ing between room temperature up to 470 K. In order
5
H = 10 nm
to take the incomplete carrier ionization into account,
Transconductance [µS]

4 W = 10 nm VD = 0.05, 0.1, which is very important for these devices [18,24,33-

tox = 2 nm 0.2, 0.5, 1 V 34], the model proposed by Altermatt et al. [35] has
3 L = 1 µm 19 -3 been used, such that the doping concentration has been
ND = 1 x 10 cm substituted by the ionized doping concentration. From
2 this Fig. 5, it is clear that the model describes adequate-
ly the dependence on the temperature.
1

0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Gate voltage [V]
Figure 3. Drain current and transconductance as a function of the
gate voltage for the n-type devices.

old regions. In Fig. 4, the drain current and the drain

output conductance (gD = dID/dVD) are presented as a
function of the drain voltage for several gate overdrive
voltages (VGT = VG – VTH). From this figure, it can
be concluded that the model adequately predicts the
characteristics for long channel devices.

2.0 ND = 1 x 1019 cm-3 VGT = 1 V

H = 10 nm
Drain current [µA]

W = 10 nm
1.5 tox = 2 nm
VGT = 0.8 V
L = 1 µm
1.0
VGT = 0.6 V
0.5 VGT = 0.4 V
VGT = 0.2 V
0.0
Output conductance [S]

VGT = 0.2, 0.4,

10-6 0.6, 0.8, 1 V

10-7

10-8

10-9 Lines - Model

Symbols - Simulation
0.0 0.4 0.8 1.2 1.6
Figure 5. Drain current (A) and transconductance (B) as a function
Drain voltage [V] of the gate voltage comparing experimental and modeled data for dif-
Figure 4. Drain current and output conductance as a function of the ferent temperatures.
drain voltage for the n-type devices.

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Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

V. Short-Channel Effects Correction U = − Φ2D, V = VD − Φ2D and Φ2D is the potential

obtained from the solution of the 2D Poisson equation.
In order to obtain an analytical expression which
accounts for short-channel effects, the tridimensional
Poisson equation must be solved: l  U exp( L / l ) − V  (18)
y min = ln 
2 V − U exp(− L / l ) 

The surface potential Φ2D for the depletion re-

gion can be obtained through eq. (6) leading to

In order to find an analytical solution for (15),

the superposition principle can be used, such that the
solution is obtained by the sum of the solution of (5)
with the solution of the 3D Laplace equation given by

In Figs. 6 and 7 the drain current and its de-

rivative are presented as a function of the gate and
drain biases, respectively, comparing simulated and
The solution of (16) for the minimum potential modeled data for short channel-devices. From these
in the channel is given by [1,26,36] curves, it can be seen that the inclusion of eq. (17)
adequately describes the short channel effects in the
drain current.

where l is characteristic length, which for a triple

gate device can be obtained through the average of the
two scaling lengths (l1 related to the width scaling and
l2 related to the height one) [1], ymin is the point of the
minimum potential in the channel given by (18) [36],

Figure 7. Drain current and output conductance as a function of the

drain voltage for a short-channel device (L = 40 nm).

Figure 6. Drain current and transconductance as a function of the

gate voltage for a short-channel device (L = 40 nm).

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 Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

VI. Subthreshold Slope

0.6 VD = 0.05 V ND = 1 x 1019 cm-3
Eq. (17) can be used to obtain an expression W = 10 nm
0.5 H = 10 nm
for the subthreshold slope dependence on the channel
tox = 2nm
length. In order to develop this expression the varia- 0.4
tion of the minimum potential in the channel with the

Φmin [V]
gate voltage needs to be analyzed. In Fig. 8, the point 0.3
of the minimum potential normalized by the channel L = 20, 30,
0.2 40 and 50 nm
length is shown as a function of the gate voltage for
devices with different L at a low drain bias. The thresh-
0.1
0.56 0.0
L = 20, 30,
40 and 50 nm -0.5 0.0 0.5 1.0
0.52
Gate voltage [V]
Figure 9. Minimum potential in the channel as a function of the gate
0.48 voltage for devices of different lengths.
ymin/L

0.44 VD = 0.05 V
where S was calculated by S = (kT/q) ln(10).n, with n ≈ 1.
tox = 2nm
0.40 H = 10 nm Differentiating (20) in relation to the gate volt-
W = 10 nm age it can be obtained
0.36 ND = 1 x 1019 cm-3

-0.5 0.0 0.5 1.0

Gate voltage [V]
Figure 8. Point of the minimum potential in the channel normalized
by the channel length as a function of the gate voltage. In the subthreshold regime, the surface potential
varies linearly with the gate voltage (Φ2D ∝ VG), since
old voltage is about 0.65 V for these devices. From this all the charges in the channel are depleted, so that there
figure, one can note that for VG << VTH, the point of is no charge variation with VG [15,26]. Therefore, the
the minimum potential tends to the half of the channel subthreshold slope considering short-channel effects
length (ymin/L = 0.5). This is related to the small differ- can be calculated by
ence between the potential barriers at source and drain.
Therefore, in order to derive an expression for S, the
point y­min can be considered as L/2. With this approxi-
mation, eq. (17) can be rewritten in the subthreshold
regime for a low drain bias as

120
Symbols - Simulation W H tox
Subthreshold slope [mV/dec]

110 Lines - Model [nm] [nm] [nm]

In Fig. 9, the minimum potential obtained 10 10 2
from (18) is presented as a function of the gate volt- 100 20 10 2
age for the devices with different channel lengths. 10 20 2
90 10 10 1
From this figure it is clear that Φmin,sub varies linearly
with the gate voltage in the subthreshold region. It 80
can be also noted that the minimum potential and
its variation with VG increases when the channel 70
length is reduced. The variation of the subthreshold
slope (DS) with the dimensions of the device is re- 60
lated with the variation of Φmin,sub with VG: ND = 1 x 1019 cm-3
50
20 40 60 80 100
Channel length [nm]
Figure 10. Subthreshold slope as a function of the channel length
comparing modeled and simulated data.

Journal of Integrated Circuits and Systems 2013; v.8 / n.2:116-124 121

Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

The subthreshold slope calculated by (23) has The threshold voltage roll-off is finally obtained
been compared to the data of simulated devices of dif- substituting (28) in (27), which leads to
ferent dimensions in Fig. 10. From this figure, one can
conclude that eq. (23) can predict adequately the sub-
threshold slope on the devices characteristics.

VII. Threshold Voltage Roll-off and In Fig. 11, the VTH,roll-off obtained through eq.
Drain Induced Barrier Lowering (29) is compared to the one extracted from the simu-
lated devices. For the simulated devices, VTH is extract-
Eq. (17) can also be used to develop an analytic ed using the double-derivative method [37] for a drain
model for the threshold voltage roll-off and for the bias of 50 mV. The comparison is performed for de-
drain induced barrier lowering. To obtain an analytical vices of different dimensions, showing that the model
expression for the VTH roll-off, the surface potential in is adequate for predict the VTH,roll-off.
the threshold condition is needed. For a long device, The drain induced barrier lowering can be cal-
this potential can be obtained by [24] culated using the threshold voltage roll-off. Firstly,
the surface potential Φ2D is calculated for VG = VTH
– VTH,roll-off using eq. (19), with VTH obtained by (14).
Then, the point ymin is calculated considering a
higher drain bias, e.g. VD = 1 V, using (18) and the min-
imum potential at this higher VD (Φmin,Vd=1V) is obtained
However, this potential changes with the by (17). The drain induced barrier lower is calculated as
variation of the minimum potential in the channel.
Therefore, the potential at threshold considering short-
channel effects (ΦVth,SCE) can be obtained by the dif-
ference between the surface potential for long-channel where DIBLL is the drain induced barrier lower-
devices and the minimum potential in the surface in the ing extracted for the long device.
threshold condition

Considering that the threshold voltage is extract-

ed with a low drain bias, the point of the minimum po-
tential in the channel occurs in the center of the device
(ymin = L/2, as shown in Fig. 8). The potential Φmin,Vth,
which represents the threshold voltage roll-off (VTH,roll-
off = Φmin,Vth) can be obtained by eq. (20) with U =
Φ2DVth,SCE, V = VD +Φ2DVth,SCE:

If the drain bias is much lower than the surface

potential, eq. (26) can be rewritten as

Substituting (27) in (25), the potential at thresh- Figure 11. Threshold voltage roll-off comparing modeled and simu-
old considering short-channel effects is described by lated data for devices of different dimensions.

122 Journal of Integrated Circuits and Systems 2013; v.8 / n.2:116-124

 Drain Current and Short Channel Effects Modeling in Junctionless Nanowire Transistors
Trevisoli, Doria, Souza & Pavanello

Acknowledgements

The authors acknowledge the Brazilian research

founding agencies FAPESP, CNPq and CAPES for the
financial support.

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