Enhancement of ON-Current in Modified TMG

Vertical TFET with Split Pockets

K. Sivani (  sivanik234@gmail.com )
Kakatiya Institute of Technology and Science
B. Harish
Vignan’s Lara Institute of Technology and Science
Ch. Pavan Kumar
Kakatiya Institute of Technology and Science

Research Article

Keywords: Ambipolarity, Gate stacking, Vertical TFET, Sub-threshold slope, Source pocket overlay

Posted Date: January 31st, 2024

DOI: https://doi.org/10.21203/rs.3.rs-3909124/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
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Additional Declarations: No competing interests reported.

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Abstract
This paper emphasizes the configuration of an N+ Si pocket overlay in a Vertical Tunnel Field Effect
Transistor (VTFET), incorporating a gate-stacking process. In this design, the source pocket is divided into
two segments with differing doping concentrations, specifically low and high concentrations. In Tunnel
Field Effect Transistors (TFETs), the source pocket plays a vital role in augmenting the ON-state (ION)
current. The vertical structure is implemented to alleviate scaling constraints and improve the device's
scalability. To address ambipolarity, the gate electrode is divided into three segments with optimal work-
functions of 4.15 eV, 4.30 eV, and 4.15 eV for the Auxiliary gate, Control gate, and Tunneling gate,
respectively. The sub-threshold slope of short-channel Tunnel Field Effect Transistors (TFETs) will
experience enhancement through a gate-stacking procedure employing high-k gate oxides, such as HfO2,
in combination with SiO2 in the stack. Additionally, the pocket overlay positioned in the center of the
source-channel region, utilizing low band gap group III-V materials, contributes to further improvements in
the current ratio (ION / IOFF) and sub-threshold slope. In the presented device, the measured ION current
and IOFF current are 8.14 x 10-3 A/μm and 5.37 x 10-11 A/μm, respectively. The threshold voltage is
reduced to 0.2V. These achieved parameters establish the N+ Si pocket-doped Triple Metal Gate (TMG)
VTFET as well-suited for applications demanding low power consumption.

1. INTRODUCTION
CMOS (Complementary Metal-Oxide Semiconductor) has found extensive applications over the years,
playing a pivotal role in chip design, flash memory, microprocessor designs, computer memories, and
CPUs. Despite its widespread use, CMOS encounters limitations attributed to short-channel effects (SCE).
These effects arise when the channel length of a MOSFET becomes comparable to the thicknesses of the
depletion layers at the source and drain junctions. Short-channel effects manifest in various ways, such
as reduced barrier caused by the drain, velocity saturation, degradation of hot carrier and quantum
confinement, and a high sub-threshold slope [1–5].

In response to these drawbacks, Tunnel FET (TFET) was introduced in 1992. TFET brings about changes
in several performance characteristics of conventional MOSFETs, including sub-threshold swing
improvement, achievement of ultra-low power and voltage, mitigation of short-channel effects, reduction
in leakage current, and addressing the speed requirements through tunneling effects. Furthermore, TFET
helps overcome the fundamental limit of the sub-threshold slope to 60mV per decade while reducing OFF
current [6–7].

TFETs operate through the control of quantum tunneling across the barrier, in contrast to conventional
MOSFETs that rely on regulating thermionic emission over the barrier. TFETs are generally categorized
into two main types: Lateral TFET and Vertical TFET (VTFET).

It can be argued that the lateral TFET design, despite having a significantly lower tunneling current
density than its vertical counterpart, does not experience parasitic tunneling. In a Lateral TFET, tunneling
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occurs exclusively at the gate's edge, whereas in a VTFET, tunneling takes place across the entire gate.
However, a drawback of the lateral design is the potential for increased leakage current when the gate is
scaled down due to direct tunneling between the source and drain.

Tunnel FETs find optimal application in low-power devices leveraging band-to-band tunneling. The critical
process influencing the dependence of drain current on gate-to-drain voltage, along with the transition to
the high current state, is identified as band-to-band tunneling (BTBT). Despite numerous advantages,
Tunnel FETs come with certain drawbacks, including low ION current, elevated threshold voltage (Vth),
and ambipolar conduction. Ambipolarity refers to the ability to conduct while maintaining a single drain
bias over both extremely positive and extremely negative gate voltages. To mitigate ambipolar
conduction, a solution involves the introduction of a triple metal gate with gate stacking. Gate stacking
involves partitioning the metal gate into three segments, with the middle section maintaining a higher
work function compared to other areas of the metal gate. This approach aims to address and reduce the
challenges associated with ambipolar conduction in Tunnel FETs.

2. EXISTING VERTICAL TFET

Tunnel FETs emerge as a compelling contender for the next generation of low-power devices, offering the
potential to address various technological challenges. This device demonstrates the ability to easily
surpass the fundamental limit of the Sub-threshold Slope (SS), which is 60mV per decade, while
maintaining a modest IOFF current. The quantum band-to-band tunneling (BTBT) process governs the
tunneling probability[8–11].

Traditional silicon-based Tunnel FETs (TFETs) encounter various constraints, such as low ION current, a
high Vth (threshold voltage), and ambipolarity. Overcoming these limitations is imperative to expand the
usability of TFETs across different applications. Specifically, efforts should focus on augmenting the ION
current and suppressing ambipolar behavior.

Numerous techniques and tools are employed to tackle these challenges and enhance the overall
efficiency of the unit. Addressing ambipolarity involves dividing the gate electrode into three sections,
each with optimized work-functions: MG1 at 4.15eV, MG2 at 4.30eV, and MG3 at 4.15eV. The construction
of heterojunction Tunnel FET structures and source regions incorporates materials such as Germanium
(Ge), silicon germanium (SiGe), or low-bandgap Group III-V. These materials play a crucial role in
overcoming technological limits and improving the performance of the device [12–15].

As a consequence, both the ION current and the Sub-threshold Slope experience enhancement. The gate-
stacking technique, demonstrated by incorporating high-k gate oxides like HfO2 in the stack with SiO2,
serves to further improve the Sub-threshold Slope of short-channel Tunnel FETs. Experimental evidence
indicates that scaling limitations in Tunnel FETs are overcome by adopting Vertical Tunnel Field Effect
Transistors (VTFETs). Moreover, introducing a pocket overlay within the source-channel region has been
shown to elevate the ION/IOFF and Sub-threshold Slope, surpassing the previous restrictions of 30 to 50
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mV per decade. While these methods demonstrate efficacy when applied individually, they fall short in
meeting the heightened performance demands of densely packed circuits. A novel approach involves
subjecting Tunnel FET designs to the combined effects of gate stacking and pocket overlay within the
source-channel region in a Triple Metal Gate (TMG) VTFET. The current configuration features a gate-
stacked triple metal gate VTFET with a silicon pocket overlay, effectively reducing ambipolar
characteristics and improving ION current [16–17].

Figure 1: N + Si gate-stacked TMG VTFET.

Illustrated in Fig. 1 is the gate-stacked Triple Metal Gate Vertical Tunnel Field Effect Transistor with a
source pocket overlay (GS-TMG-VTFET). The simulation of the current VTFET employs specific design
parameters and doping concentrations outlined in Table 1. In the current VTFET configuration, the
measured ION current is 6.4 x 10− 4 A/µm, while the IOFF current is measured at 5.64 x 10− 11 A/µm. A
preliminary measurement indicates a Vth of 0.54V. To enhance the device's performance, modifications
are introduced to increase the ION current and reduce the threshold voltage.

Table 1
Design specifications used for simulation of existing Tunnel FET using Silvaco
TCAD
Parameters Specifications

Length of source (Ls ) / doping concentration (cm− 3) 30nm / 5 x 1020 (p-type)

Length of channel (Lg) / doping concentration(cm− 3) 70nm / 1 x 1016 (n-type)

Length of drain (Ld) / doping concentration (cm− 3) 60nm / 5 x 1018 (p-type)

Work-function of Tunneling Gate (MG1) 4.15 eV

Work-function of Control Gate (MG2) 4.30 eV

Work-function of Auxiliary Gate (MG3) 4.15 eV

Thickness of Gate Oxide (SiO2 / HfO2) 3nm / 2nm

N + Si pocket layer (Lp) 2nm / 5nm

3. MODIFIED VERTICAL TFET

The drawback of the existing Vertical Tunnel Field Effect Transistor (VTFET) lies in the fact that steeper
Sub-threshold Slopes are observed only at lower voltages, rendering TFETs incapable of generating
adequate currents even at higher voltages. The presence of parasitic tunneling is responsible for the
inability to achieve the expected low sub-threshold swings when reducing the barrier thickness. To
enhance the ION current in Tunnel FETs, a crucial element is the source pocket. The source pocket
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undergoes vertical separation into low and high-concentration segments without altering its width, aiming
to enhance the properties of the source pocket.

The source pocket width (LP=5nm) is partitioned into two equal segments (LH=LL=2.5nm). The high-
concentration source pocket is doped at N+= 1 x 1020 cm− 3, while the low-concentration source pocket is
doped at N− = 5 x 1019 cm− 3. To decrease the threshold value, the drain concentration is reduced. In the
original Vertical Tunnel Field Effect Transistor (VTFET), the drain concentration is (5 x 1018 cm− 3), and in
the modified structure, it is further reduced to (1 x 1018 cm− 3) through the gate stacking mechanism. The
gate stacking process aims to enhance the ION current and achieve a steeper sub-threshold slope.
Incorporating high-k gate oxides, such as HfO2 stacked with SiO2, in the gate stacking process is a crucial
technique to further improve the Sub-threshold Slopes of short-channel Tunnel FETs. The gate electrode
is divided into three sections: MG1, MG2, and MG3. The work-functions for each section are 4.15 eV for the
Auxiliary gate (MG1), 4.30 eV for the Control gate (MG2), and 4.15 eV for the Tunneling gate (MG3). The
modified VTFET using split pockets is shown in Fig. 2.

The design parameters and doping concentrations used for the simulation of modified VTFET with split
pockets are given in Table 2.

Table 2
Device design specifications used for simulation using Silvaco TCAD
Parameter used Specifications

Length of source (Ls) / doping concentration (cm− 3) 30nm / 5 x 1020 (p-type)

Length of channel (Lg) / doping concentration(cm− 3) 70nm / 1 x 1016 (n-type)

Length of drain (Ld) / doping concentration (cm− 3) 60nm / 1 x 1018 (p-type)

Work-function of Tunneling Gate (MG1) 4.15 eV

Work-function of Control Gate (MG2) 4.30 eV

Work-function of Auxiliary Gate (MG3) 4.15 eV

Thickness of Gate Oxide - SiO2 / HfO2 3nm / 2nm

N + Si pocket layer (Lp) 5nm split

High-concentration source pocket (LH) / doping concentration (cm− 3) 2.5nm / 1 x 1020

Low-concentration source pocket (LL) / doping concentration (cm− 3) 2.5nm / 5 x 1019

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In the modified VTFET, the ION current observed is 8.14 x 10− 3 A/µm, and the IOFF current is observed as
5.37 x 10− 11 A/µm. The Vth measured is 0.2V.

4. RESULTS AND DISCUSSIONS

The drain current characteristics (Ids – Vgs) for both the existing and modified Vertical Tunnel Field
Effect Transistor (VTFET) are depicted in Fig. 3 and Fig. 4, respectively. The design and the result
parameters of the existing and modified Tunnel FET device are given in Table 3.

Table 3
Comparison table for existing and modified VTFET
Parameter used Existing structure Modified structure

Length of source (Ls) / doping concentration(cm− 3) 30nm / 5 x 1020 (p- 30nm / 5 x 1020 (p-
type) type)

Length of channel (Lg) / doping concentration(cm− 3) 70nm / 1 x 1016 (n- 70nm / 1 x 1016 (n-
type) type)

Length of drain (Ld) / doping concentration(cm− 3) 60nm / 5 x 1018 (p- 60nm / 1 x 1018 (p-
type) type)

Thickness of Gate oxide- SiO2 / HfO2 3nm / 2nm 3nm / 2nm

N + Si pocket layer (Lp) 2nm / 5nm 5nm split

High-concentration source pocket (LH) / doping 2.5nm / 1 x 1020

concentration(cm− 3)

Low-concentration source pocket (LL) / doping 2.5nm / 5 x 1019

concentration(cm− 3)

Threshold voltage (Vth) 0.54V 0.2V

ON-current (ION) 6.4 x 10− 4 A/µm 8.14 x 10− 3 A/µm

OFF-current (IOFF) 5.64 x 10− 11 A/µm 5.37 x 10− 11 A/µm

ION / IOFF 1.13 x 107 1.51 x 108

Analyzing Table 3 reveals an increase in the ION current (8.14 x 10− 3 A/µm) and a reduction in the
threshold voltage (Vth) to 0.2V. Notably, it is evident that the enhanced structure exhibits an improved ION
current without a concurrent increase in the IOFF current.

5. CONCLUSION

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This paper explores the characteristics of an N+ Si pocket-doped Gate Stacked Triple Metal Gate Vertical
Tunnel Field Effect Transistor (VTFET). In contrast to modifying the Tunnel FET, the study proposes an
enhanced architecture for the existing VTFET by dividing the pocket into low-concentration and high-
concentration source pockets. This architecture demonstrates promising simulation results, showcasing
a substantial increase in ION current, a minimally sharp sub-threshold slope, and an optimized threshold
voltage.

To mitigate ambipolar conduction, the updated design incorporates a triple metal gate, and the use of a
gate stack with a high-k dielectric maximizes the ION current. Control over the device tunneling current is
enhanced through the gate-stacking combination of SiO2 and HfO2.

Remarkably, the suggested device architecture allows for an increase in tunneling conduction without a
boost in the IOFF current. The ION / IOFF ratio achieved in optimal structure simulation is notably high (1.51
x 108) with a sub-threshold voltage of 0.2V. Reported ION and IOFF currents are 8.14 x 10− 3 A/µm and 5.37
x 10− 11 A/µm, respectively. For applications in low-power consumption digital circuits, the proposed
Vertical Tunnel FET emerges as a promising alternative to traditional Tunnel FET devices.

Declarations
Author Contribution
K. Sivani worked on the concept wrote main manuscript.B. Harish prepared draft and checked thoroughly.
Ch. Pavan Kumar prepared the final draft and checked thoroughly.

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Figures

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Figure 1

N + Si gate-stacked TMG VTFET.

Figure 2

Symbolic diagram of modified VTFET with split pockets

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Figure 3

Ids – Vgs characteristics of existing VTFET

Figure 4

Ids – Vgs characteristics of modified VTFET

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