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still operate upto 11 MHz

from thesc FFs and
(c) Afew combination of inputs and the pre
sents state

(d) All the combinations of input and the (a) Any

present state (b) 8
25. For the circuit shown, the counter state (c) 256
(QQ.)follows the sequence (d) 10 is
walking or creeping Counter
30. Athree-stage
depicted below:

D, Qo D, Q, CK
CK
CK
Clock 4
pass
dows this counter
How many states
through before repeating?
is its modulo?
(a) 00, 01, 10, 11, 00 In other words, what
(b) 00, 01, 10, 00, 01 (a) 3
(c) 00, 01, 11, 00, 01 (b) 8
(d) 00, 10, 11, 00, 10 (c) 6
be determined given
26. A divide by-78 counter can be
realized.by (d) The modulo cannot
this information
using
flip-flops are in rest
(a) 6 nos of mod-13 counters 31. Assuming that all
conditions initially, the count sequence
(b) 13 nos of mod-6 counters shown is
followed by one mod observed at Q, in the circuit
(c) one mod-13 counter
6 counters
Output
(d) 13nos and mod-13 counters
output of the
27. What is the frequency of the frequency is
eight FF when the input clock lo/P
512 kHz
(a) 16 kHz
(b) 8 kHz
Clock
(c) 4 kHz
(d) 2 kHz (a) 0010111 ...
MOD-16 down counter
28. The initial state of a (b) 0001011 ...
is 0110. What state
will it be after 37 clock
(c) 0101111 ...
pulses?
(a) Indeterminate (d) 0110100 ...

(b) 0110 32. The following binary values were applied to

then X and Yinputs of the NAND latch shown
(c) 0101 in the figure in the sequence indicated below:
(d) 0001 X=0, Y=1;
ns. The largest
29. Acertain JKFF has tpd =12 X =0, Y =0;
be constructed
MOD ripple counter that can

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34. In the modulo-2 ripple counter shown in th.
X =1, Y=l. figure, the output of the 2-input gate is
outputs will be to clear the J-K flip-flops used
The corresponding table P, Q

P c J Chy

|2-input
gate
Y
The 2-input gate is
(a) a NAND gate
(a) P= 1, Q = 0; (b) a NOR gate
P= 1, Q -0; (c) a OR gate
P= 1, Q = 0or (d) an AND gate
P=0, Q =1 35. A 4bit ripple counter and a 4 bit synchrnous
(b) P= 1, Q = 0; counter are made using flip flop having a
P= 0, Q=0; or
propagation delay of 10 nseach. If the worst
case delay in the riPple counter and the
P= 0, Q =1; synchronous counter be A and S respectively.
P=0, Q = 1 then
(c) P= 1, Q = 0; (a) R = 10ns, S = 40 ns
P= 1, Q= 1; (b) R = 40 ns, S = 10 ns
P= 1, Q = 0; or (c) R = 10 ns, S= 30 ns
P=0, Q=1 (d) R = 30 ns, S = 10 ns
(d) P = 1, Q = 0; 36. The digital block in the figure is realized using
P= 1, Q= 1;
two positive edge triggered D-flip flops.
Assume that for t<to = , =0. The
P= 1, Q= 1;
Choose the correct one from among the
circuit in the digital block is given by:
33.
alternatives A, B, C, D after matching an item
from Group 1with the most appropriate item X DIGITAL
BLOCK
in Group 2. to tË t, t, t t, t, t,
Group 1
P. Shift register 14D,
Q. Counter (a)
R. Decoder
Group 2 D,
1. Frequency division (b) X
2. Addressing in memory chips
3. Serial to parallel data conversion
1
(a) P-3, Q-2, R-1 D
(b) P-3, Q-1, R-2 (c)
(c) P-2, Q-1, R-3
(d) P-1, Q-2, R-2

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