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The document describes a VHDL implementation of a PS/2 keyboard interface and a four-digit seven-segment display controller. It includes entities for handling PS/2 scancodes, a shift register for data input, and a display driver that manages the output to the seven-segment display. The architecture consists of multiple components working together to process input and display corresponding values based on the received scancodes.
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0% found this document useful (0 votes)
5 views11 pagescodpdf
The document describes a VHDL implementation of a PS/2 keyboard interface and a four-digit seven-segment display controller. It includes entities for handling PS/2 scancodes, a shift register for data input, and a display driver that manages the output to the seven-segment display. The architecture consists of multiple components working together to process input and display corresponding values based on the received scancodes.
Uploaded by
Suciu TudorCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
/ 11
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Four_DIGIT_SSD is
Port ( CLK : in STD_LOGIC;
DIGI1: in std_logic_vector (6 downto 0);
DIGI2: in std_logic_vector (6 downto 0);
DIGI3: in std_logic_vector (6 downto 0);
DIGI4: in std_logic_vector (6 downto 0);
AN: out std_logic_vector (7 downto 0);
SEG: out std_logic_vector (6 downto 0)
);
end Four_DIGIT_SSD;
architecture BEHAVIORAL of Four_DIGIT_SSD is
signal N: std_logic_vector (27 downto 0) := (others => '0');
signal ANA: std_logic_vector (7 downto 0); --anode active
signal digit_sel: std_logic_vector (1 downto 0);
begin
process(CLK)
begin
if rising_edge (CLK) then
N <= N+1;
end if;
end process;
digit_sel <= N(17)&N(16);
-- anode selection (only the first 4 are used)
ANA <= "11111110" when digit_sel = "00" else
"11111101" when digit_sel = "01" else
"11111011" when digit_sel = "10" else
"11110111" when digit_sel = "11" else
"11111111";
AN <= ANA;
-- segment selection
SEG <= DIGI1 when digit_sel = "00" else
DIGI2 when digit_sel = "01" else
DIGI3 when digit_sel = "10" else
DIGI4 when digit_sel = "11" else
"1111111";
end BEHAVIORAL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity ps2_scancode is
Port (
clk : in std_logic; -- 100 MHz clock
PS2_CLK : in std_logic; -- PS/2 clock
PS2_DATA : in std_logic; -- PS/2 data
code : out std_logic_vector(7 downto 0); -- Output scancode
ready : out std_logic ;--high when ready
AN : out std_logic_vector(7 downto 0);
CT : out std_logic_vector(6 downto 0)
);
end ps2_scancode;
architecture Behavioral of ps2_scancode is
signal ps2_clk_sync : std_logic_vector(1 downto 0) :="11";
signal ps2_clk_falling : std_logic :='0';
signal shift_reg : std_logic_vector(10 downto 0) := (others => '0');
signal bit_count : integer range 0 to 10 := 0;
signal data_ready : std_logic := '0';
signal data_byte : std_logic_vector(7 downto 0) := (others => '0');
signal i1: std_logic_vector(6 downto 0);
signal i2: std_logic_vector(6 downto 0);
signal i3: std_logic_vector(6 downto 0);
signal i4: std_logic_vector(6 downto 0);
component shift_register is
Port ( clk : in STD_LOGIC;
sin : in STD_LOGIC_VECTOR (7 downto 0);
q1 : out std_logic_vector (6 downto 0);
q2 : out std_logic_vector (6 downto 0);
q3 : out std_logic_vector (6 downto 0);
q4 : out std_logic_vector (6 downto 0)
);
end component;
component Four_DIGIT_SSD is
Port ( CLK : in STD_LOGIC;
DIGI1: in std_logic_vector (6 downto 0);
DIGI2: in std_logic_vector (6 downto 0);
DIGI3: in std_logic_vector (6 downto 0);
DIGI4: in std_logic_vector (6 downto 0);
AN: out std_logic_vector (7 downto 0);
SEG: out std_logic_vector (6 downto 0)
);
end component;
begin
process(clk)
begin
if rising_edge(clk) then
ps2_clk_sync(1) <= ps2_clk_sync(0);
ps2_clk_sync(0) <= PS2_CLK;
ps2_clk_falling <= ps2_clk_sync(1) and not ps2_clk_sync(0);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
data_ready<='0';
-- Detect falling edge on PS/2 clock
if ps2_clk_falling = '1' then
shift_reg(bit_count)<=PS2_DATA;
if bit_count = 10 then
bit_count<=0;
data_byte<=shift_reg(8 downto 1);
data_ready<='1';
else
bit_count<=bit_count+1;
end if;
end if;
end if;
end process;
code <= data_byte;
ready <= data_ready;
c1 : shift_register port map (
clk => clk,
sin => data_byte,
q1=>i1,
q2=>i2,
q3=>i3,
q4=>i4
);
c2 : Four_DIGIT_SSD port map (
CLK=>clk,
DIGI1=>i1,
DIGI2=>i2,
DIGI3=>i3,
DIGI4=>i4,
AN=>AN,
SEG=>CT
);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity shift_register is
Port ( clk : in STD_LOGIC;
sin : in STD_LOGIC_VECTOR (7 downto 0);
q1 : out std_logic_vector (6 downto 0);
q2 : out std_logic_vector (6 downto 0);
q3 : out std_logic_vector (6 downto 0);
q4 : out std_logic_vector (6 downto 0)
);
end shift_register;
architecture Behavioral of shift_register is
type matrix is array (0 to 3) of std_logic_vector(6 downto 0);
signal state : matrix := (others => "0000000"); -- 7-segment data
signal dot : integer range 0 to 3 := 0; -- current dot position
signal e0_flag : std_logic := '0'; -- track E0 prefix
begin
-- Process for dot navigation and special keys
process(clk)
begin
if rising_edge(clk) then
if sin = x"E0" then
e0_flag <= '1'; -- set E0 prefix flag
elsif e0_flag = '1' then
-- Only handle arrow keys when E0 prefix is set
if sin = x"6B" then -- Right Arrow
if dot = 3 then
dot <= 0;
else
dot <= dot + 1;
end if;
elsif sin = x"74" then -- Left Arrow
if dot = 0 then
dot <= 3;
else
dot <= dot - 1;
end if;
end if;
e0_flag <= '0'; -- clear flag after handling
end if;
end if;
end process;
-- Process for data input and special functions
process(clk)
begin
if rising_edge(clk) then
if sin = "01011010" then -- Enter (5A)
state <= (others => "1111111"); -- clear all
else
case sin is
when "01100110" => state(dot) <= "1111111"; -- Backspace
when "01000101" => state(dot)<= "0000001"; -- 0
when "00010110" => state(dot) <= "1001111"; -- 1
when "00011110" => state(dot) <= "0010010"; -- 2
when "00100110" => state(dot) <= "0000110"; -- 3
when "00100101" => state(dot) <= "1001100"; -- 4
when "00101110" => state(dot) <= "0100100"; -- 5
when "00110110" => state(dot) <= "0100000"; -- 6
when "00111101" => state(dot) <= "0001111"; -- 7
when "00111110" => state(dot) <= "0000000"; -- 8
when "01000110" => state(dot) <= "0000100"; -- 9
-- Letters A-Z mapping
when "00011100" => state(dot) <= "0001000"; -- A
when "00110010" => state(dot) <= "1100000"; -- B
when "00100001" => state(dot) <= "0110001"; -- C
when "00100011" => state(dot) <= "1000010"; -- D
when "00100100" => state(dot) <= "0110000"; -- E
when "00101011" => state(dot) <= "0111000"; -- F
when "00110100" => state(dot) <= "0100001"; -- G
when "00110011" => state(dot) <= "1001000"; -- H
when "01000011" => state(dot) <= "1111001"; -- I
when "00111011" => state(dot) <= "1000011"; -- J
when "01000010" => state(dot) <= "1111110"; -- Not defined
when "01001011" => state(dot) <= "1110001"; -- L
when "00111010" => state(dot) <= "1111110"; -- Not defined
when "00110001" => state(dot) <= "0001001"; -- N
when "01000100" => state(dot) <= "0000001"; -- O
when "01001101" => state(dot) <= "0011000"; -- P
when "00010101" => state(dot) <= "0001100"; -- Q
when "00101101" => state(dot) <= "0111001"; -- R
when "00011011" => state(dot) <= "0100100"; -- S
when "00101100" => state(dot) <= "1110000"; -- T
when "00111100" => state(dot) <= "1000001"; -- U
when "00101010" => state(dot) <= "1000001"; -- V
when "00011101" => state(dot) <= "1111110"; -- Not defined
when "00100010" => state(dot) <= "1111110"; -- Not defined
when "00110101" => state(dot) <= "1000100"; -- Y
when "00011010" => state(dot) <= "0010010"; -- Z
when others => state <= state; -- No change
end case;
end if;
end if;
end process;
-- Assign outputs with dot active on selected segment
q1 <= state(0);
q2 <= state(1);
q3 <= state(2);
q4 <= state(3);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_project is
Port (
clk :in std_logic ;
PS2_CLK : in std_logic; -- PS/2 clock
PS2_DATA : in std_logic; -- PS/2 data
AN : out std_logic_vector(7 downto 0);
CT : out std_logic_vector(6 downto 0)
);
end top_project;
architecture Behavioral of top_project is
component ps2_scancode is
Port (
clk : in std_logic; -- 100 MHz clock
PS2_CLK : in std_logic; -- PS/2 clock
PS2_DATA : in std_logic; -- PS/2 data
code : out std_logic_vector(7 downto 0); -- Output scancode
ready : out std_logic ;--high when ready
AN : out std_logic_vector(7 downto 0);
CT : out std_logic_vector(6 downto 0)
);
end component;
signal code : std_logic_vector(7 downto 0);
signal ready : std_logic;
begin
c1: ps2_scancode port
map(clk=>clk,PS2_CLK=>PS2_CLK,PS2_DATA=>PS2_DATA,ready=>ready,code=>code,AN=>AN,CT=>CT);
end Behavioral;