SDH TRANSMISSION SYSTEM

SDH BASICS

 What is SDH?
 Characteristics of SDH
 ITU-T’s Recommendations
 Bit Rates
 Path and Section
 Review Questions
1
 What is SDH?

• A New Digital Hierarchy

· 155.52 Mb/s, 622.08 Mb/s, 2488.32 Mb/s, 9953.28 Mb/s,
39813.120Mb/s
· Existing PDH and future ATM signals are carried over
the SDH system.
• Very basic functions are same as PDH.
· Multiplex low bit rate digital signals to higher bit rate
and transmit large information efficiently.

2
 What are the differences ?

 Synchronous Network
Basically, all network elements work on a single clock
source.

• Abundant Overhead Bits

To carry large information for Network Management.

• Unified Interface and Multiplexing Specifications

Common to all countries.
Standardized optical interfaces.

3
 What are the benefits? (1)
- Synchronous Network -

Simple multiplexing process

Easy access to tributary signals in a multiplexed high
bit rate signal.
ADD/DROP distribution
RING survivability
CROSS CONNECT capacity management
band width management
protection route diversity
Simple Access to Tributaries

140M 140M
DD F

34 M 34 M

8M 8M

A D D /D R O P M U X
2M
PDH
S T M -1 ST M -1
M IN I X -C O N N
SDH

2M

4
 What are the benefits? (2)
- Overhead Bits –

• Realization of highly advanced Network

Management System for:
Fault management
Configuration management
Performance management
Security management
Accounting management

5
 What are benefits SDH? (3)
- Unified Interface –

• Multi-vendor Environment
• International Connection

6
 What are SDH?
- in conclusion –

• SDH is the infrastructure for the telecommunication

network of the 21st century, providing board band and
intelligent services.

7
 ITU-T’s Recommendations on SDH
G.707 Network Node Interface for the SDH
G.773 Protocol Suits for Q-interface
G.774 SDH Management Information Model for the Network
Element View
G.781 Synchronization layer functions
G.782 Types and General Characteristics of SDH Multiplexing
Equipment
G.783 Characteristics of SDH Multiplexing Equipment Functional Blocks
G.784 SDH Management
G.803 Architecture of Transport Networks Based on the SDH
G.813 Timing characteristics of SDH equipment slave clocks(SEC)
G.842 Interworking of SDH network protection architectures
G.957 Optical Interfaces for Equipments and Systems Relating to SDH
G.958 Digital Line Systems Based on SDH for Use on Optical Fiber
Cables
8
 SDH Bit Rates

CEPT North America Japan

2.048 Mb/s 1.544 Mb/s 1.544 Mb/s
8.448 Mb/s 6.312 Mb/s 6.312 Mb/s PDH
34.368 Mb/s 44.376 Mb/s 32.064 Mb/s G.702
139.264 Mb/s 97.728 Mb/s

STM-0 51.840 Mb/s

STM-1 155.520 Mb/s
STM-4 622.080 Mb/s SDH
STM-16 2,488.320 Mb/s G.707
STM-64 9,953.280 Mb/s
STM-256 39,813.120 Mb/s
STM: Synchronous Transport Module

9
 Path and Section
Path
Multiplex Section
Regenerator Regenerator Regenerator
Section Section Section

MUX LT LT MUX

REG REG

VC Processing STM-N Processing

10
 Review Questions
Fill up the following sentences with correct words: 　　

A) When the SDH and PDH are compared, the ( 1 ) is an asynchronous system and th
e ( 2 ) is a synchronous system. The ( 3 ) conforms to the worldwide unique st
andard. On the other hand, there are three different ( 4 ) standards, for Europe and
others, North America, and Japan.
B) The peculiarities of the SDH are that the entire network basically operates with one (
1 ), it conforms to the ( 2 ) recommendation, and advanced ( 3 ) is easi
ly enabled by using abundant ( 4 ).
C) The bit rate of STM-1 is ( 1 ) Mb/s, bit rate of STM-4 is ( 2 ) Mb/s, and bit rate
of STM-16 is ( 3 ) Mb/s. They are ( 4 ) multiple of STM- ( 5 ).
D) The regenerator section is a section between ( 1 ) ( 2 ) or a section between a
( 3 ) and its neighbor ( 4 ).
E) The multiplex section is a section between nodes where ( 1 ) is generated and (
2 ).
F) The path is a connection between assembling and disassembling points of ( 1 ).

11
12
SDH TRANSMISSION SYSTEM
MULTIPLEXING STRUCTURE,
FRAME STRUCTURE AND
POINTER
 Multiplexing Structure
 Frame Structure
 Pointer
 Review Questions

13
 SDH Multiplexing Structure (1)
X1 x1
STM-256 AUG-256 AU-4-256c VC-4-256c C-4-256c

x4
x1
X1 AUG-64
STM-64 AU-4-64c VC-4-64c C-4-64c

x4

x1
X1 AUG-16 VC-4-16c C-4-16c
STM-16 AU-4-16c

x4

x1
X1 AUG-4 AU-4-4c VC-4-4c C-4-4c
STM-4

x4

x1
X1 AU-4 VC-4 C-4 139264 kb/s
STM-1 AUG-1 x3
x1
TUG-3 TU-3 VC-3
x3

C-3 44736 kb/s

X1 AU-3 VC-3 34368 kb/s
STM-0 x7 x7
x1
TU-2 VC-2 C-2 6312 kb/s
TUG-2
x3
Poi nt er pr oces s i ng TU-12 VC-12 C-12 2048 kb/s
Multiplexing
x4
Aligning TU-11 C-11 1544 kb/s
VC-11
Mapping

14
 SDH Multiplexing Structure (2)
X1 x1
STM-256 AUG-256 AU-4-256c VC-4-256c C-4-256c

x4
x1
X1 AUG-64
STM-64 AU-4-64c VC-4-64c C-4-64c

x4

x1
X1 AUG-16 VC-4-16c C-4-16c
STM-16 AU-4-16c

x4

x1
X1 AUG-4 AU-4-4c VC-4-4c C-4-4c
STM-4

x4

x1
X1 AU-4 VC-4 C-4 139264 kb/s
STM-1 AUG-1 x3
x1
TUG-3 TU-3 VC-3
x3

C-3 44736 kb/s

X1 AU-3 VC-3 34368 kb/s
STM-0 x7 x7
x1
TU-2 VC-2 C-2 6312 kb/s
TUG-2
x3
Poi nt er pr ocessi ng TU-12 VC-12 C-12 2048 kb/s
Multiplexing
x4
Aligning TU-11 C-11 1544 kb/s
VC-11
Mapping

15
 Multiplexing Process of SDH
Example: 2 Mb/s to STM-4
2.048Mb/s PDH
S 2.048Mb/s C-12

LO POH C-12 VC-12

pointer offset value
TU-1 PTR VC-12 TU-12

TU-1 PTR 3 TU-1 PTR 2 TU-1 PTR 1 VC-12 31 VC-12 21 VC-12 11 TUG-2

TUG-2 7 TUG-2 1 TUG-3

HO POH TUG-3 3 TUG-3 2 TUG-3 1 VC-4

pointer offset value
AU-4 PTR VC-4 AU-4

AU-4 PTR VC-4 AUG-1

AUG-1 4 AUG-1 3 AUG-1 2 AUG-1 1 AUG-4

SOH AUG-4 STM-4

16
 STM-1 Frame Structure
1 2 3 4 5 6 7 8 8 bits = 1 byte

125 µs
( 1) ( 2) ( 9)
270 bytes

9 261
( 1)
( 2) 3 R-SOH

9
1 AU PTR
rows Payload Capacity

5 M-SOH

( 9)
270 columns 125 µs
R-SOH: Regenerator Section Overhead
M-SOH: Multiplex Section Overhead

17
Byte Interleaved Multiplex and Frame Structure STM-N
STM-1 (AU-4)  STM-N

AAA
STM-1 AU-4
BBB
STM-1 AU-4
CCC N CBA N CBA
STM-1 AU-4
STM-N
NNN
STM-1 AU-4
byte interleaved multiplexing

9 x N 261 x N

ABC NABC N N
R SOH

AU PTRs
9 rows

M SOH
N 125 µs

18
 Pointer Function

R SOH VC-4(1)
VC-4(2)
VC-4(3)
AU PTR
TU12 PTR
P POH
VC-12
O
M SOH TU-3 PTR area POH
H VC-12
POH
VC-12
(

V
C
STM-4 4
)

2 M signal
Example:
2 Mb/s to STM-4 via AU-4 VC-4 (4) 63

2
VC-12 (63)
1

19
 AU-4 Pointer and Pointer Offset Number

H1 * * H2 * * H3H3H3 0 0 0 1 1 1 86 # #
87 # #

435 # # 521 # #
VC-4 522 # #
696 # # 782 # #

H1 H2
# same number for 3 consecutive bytes
NNNNSS I D I D I D I D I D
10 bits

Pointer Configuration

20
TU-12 Pointer and Pointer Offset Numbering
V1 V1
105 V5

36 bytes
35 bytes

139
125 µs 125 µs
V2 V2 J2
0

20 * V5

34 Z6
V3 V3 V1 V2
35
N N N N S S I D I D I D I D I D

10 bits
K4
69 Pointer Structure
V4 V4
70
*In this case, pointer offset value is set
20(0000010100)
500 µs

104
VC-12
500 µs
TU-12

21
 Pointer Renewal
A

STM-1

STM-N STM-1
AB

input signal

multiplexed signal
STM-1
delay ( )
B

STM-1
delay
( )
frame aligned signal

22
 AU-4 Justification (1)

1
N e g a t iv e ju s t if ic a t io n o p p o r t u n it y
(3 b y te s )
4 0 0 0

P o s it iv e ju s t if ic a t io n o p p o r t u n it y
(3 b y te )
9

Negative justification control

H1 H2 invert five D-bits accept majority vote
I : Increment bit
N N N N S S I D I D I D I D I D D : Decrement bit
N : New data flag bit Positive justification control
pointer value
invert five I-bits accept majority vote

23
 AU-4 Justification (2)
- Positive Justification -
start of VC-4
H1 Y Y H2 1 1 H3 H3 H3

n-1 n n n n+1 n+1

Frame 1
125 µs
pointer value (n)
H1 Y Y H2 1 1 H3 H3 H3

n-1 n n n n+1 n+1

Frame 2
250 µs
pointer value (I bits inverted)
H1 Y Y H2 1 1 H3 H3 H3 positive justification start of VC-4 (new)

n-1 n n n n+1 n+1

Frame 3
375 µs
pointer value (n+1)
H1 Y Y H2 1 1 H3 H3 H3

n-1 n n n n+1 n+1

Frame 4
500 µs

24
 AU-4 Justification (3)
- Negative Justification -
start of VC-4
H1 Y Y H2 1 1 H3 H3 H3

n-2 n-1 n-1 n-1 n n n n+1 n+1

Frame 1
125 µs
pointer value (n)
H1 Y Y H2 1 1 H3 H3 H3

n-2 n-1 n-1 n-1 n n n n+1 n+1

Frame 2
250 µs
pointer value (D bits inverted)
negative justification start of VC-4 (new)
H1 Y Y H2 1 1

n-2 n-1 n-1 n-1 n n n n+1 n+1

Frame 3
375 µs
pointer value (n-1)
H1 Y Y H2 1 1 H3 H3 H3

n-2 n-1 n-1 n-1 n n n n+1 n+1

Frame 4
500 µs

25
 Review Questions
Fill up the spaces enclosed in parentheses in the following sentences with correct words: 　
1. The cycle of the frame structure of STM-1 is ( a ) and composed of ( b ) bytes. (
c ) vertical matrixes and ( d ) horizontal matrixes represent the frame structure.
2. An STM-4 signal has four times the rate of an STM-1 signal. The STM-4 signal has rate of (
a )Mbit/s (=( b )x( c )Mbit/s). There are 36 columns for section overhead plus
( d ) pointer. There are ( e ) columns or byte for an STM-4 signal.
3. Multiplexing process route via AU-( a ) is ( b ) standard and used in most countries.
One AUG is equivalent one ( c ). A three of ( d ) signals is formed an AUG.
4. VC-3 or VC-4 POH starts immediately after ( a ) (if the pointer offset value is 0); but for VC1
2 POH, V5 is placed right after the ( b ) byte not after the ( c ).
5.. The five I bits in the (H1, H2) pointer word are inverted if the system request a ( a ) frequenc
y justification while the five D bits used for ( b ) frequency justification. In either case, the
majority vote rule is applicable to both the I and the D bits. Under a normal operation condition, t
he pointer value can be increased or decreased by ( c ). If the pointer value is 728, and a pos
itive frequency justification is requested, the new pointer value will become ( d ) for the next
three frames. If the pointer value is 0, and a negative frequency justification is requested, the new
pointer value will become ( e ) for the next three frames.
6. The NDF of SDH pointer has a code of ( a ) for a normal operation; on the other hand, for re-
starting (rebooting ) a new pointer while ignoring the existing one, NDF should be set to ( b
).

26
27
28
SDH TRANSMISSION SYSTEM

OVERHEAD AND MAPPING

• Overhead
• Mapping
• Review Questions

29
 STM-1 Frame Structure and SOH
9 bytes 261 b ytes

RSO H

A U P TR
9 row s

STM-1 PAYLOAD

MSOH

}
A1 A1 A1 A 2 A 2 A 2 J0
B1 E1 F1 RSO H
Sec tion O verhead D1 D2 D3
A U P o in te r( s )
B2 B2 B2 K1 K2

}
D4 D5 D6
D7 D8 D9 M SO H
D10 D 11 D 12
S1 Z1 Z1 Z2 Z2 M 1 E2

: bytes reserved for national use

30
 Function of SOH (1)
Framing (A1, A2)
Regenerator section trace (J0) regenerator section connection check
Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/s
Order wire (E1) accessible at regenerators
(E2) accessible at multiplexers
User channel (F1) 64 kb/s clear channel
Error monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24N
APS signaling (K1,2) automatic protection switching
(K2) also used as MS-AIS and MS-RDI
Synchronization status (S1) indication of quality level
Section status reporting (M1) REI (count of BIP-24N)

}
A1 A1 A 1 A2 A2 A 2 J0
B1 E1 F1 R SO H
RDI ; Remote Defect Indication
D 1 D 2 D 3 (formerly FERF, Far End Receive Failure)
A U P o in t e r ( s )
B2 B2 B2 K1 K2 REI ; Remote Error Indication

}
D 4 D 5 D 6
D 7 D 8 D 9 M SO H (formerly FEBE, Far End Block Error)
D 10 D 11 D 12 MS ; Multiplex Section
S1 Z1 Z1 Z2 Z2 M 1 E2
DCC ; Data Communication Channel
: bytes reserved for national use

31
 Function of SOH (2)
Framing (A1, A2)
Regenerator section trace (J0) regenerator section connection check
Data communication channel (D1-3) regenerator section DCC, 192 kb/s
(D4-12) multiplex section DCC, 576 kb/s
Order wire (E1) accessible at regenerators
(E2) accessible at multiplexers
User channel (F1) 64 kb/s clear channel
Error monitoring (B1) regenerator section BIP-8
(B2) multiplexer section BIP-24N
APS signaling (K1,2) automatic protection switching
(K2) also used as MS-RDI
Synchronization status (S1) indication of quality level
Section status reporting (M1) REI (count of BIP-24N)

}
A1 A1 A1 A2 A2 A2 J0
B1 E1 F1 RSOH
D1 D2 D3
RDI ; Remote Defect Indication
AU Pointer(s) (formerly FERF, Far End Receive Failure)
B2 B2 B2 K1 K2

}
D4 D5 D6 REI ; Remote Error Indication
D7 D8 D9 MSOH
(formerly FEBE, Far End Block Error)
D10 D11 D12
S1 Z1 Z1 Z2 Z2 M1 E2 MS ; Multiplex Section
; bytes reserved for national use DCC ; Data Communication Channel

32
 Section and Path Trace Method
Node A Node B

LPT HPT MST RST RST MST HPT LPT

RST
J0: Section trace

VC-4 POH (J1: Path trace)

VC-3 POH(J1: Path trace)
VC-12(J2: Path trace)
RST: Regenerator Section Termination MST: Multiplex Section Termination
HPT: High Order Path Termination LPT: Lower Order Path Termination

Node -A Node -B
Path Trace : Used Path Trace : Used
Transmit path trace : 123-565656 Transmit path trace : ABCDEFG
Path Trace expected value Path Trace expected value
: ABCDEGF : 123-565656
Received value : ABCDEFG Received value : 123-565656
33
 Section Trace(J0)
Node A Node B Node C
a b
R R R R
S S S S
T c d T T T

a’ b’
R R
S S
T c’ d’ T

Terminated Section of Terminated Section of

Section Trace Section Trace

RST: Regenerator Section Termination

34
 Principle of BIP 8

1121 * * * K1 * * * 81 12 22 * * * K2 * * * 82

#n 1i 2i * * * Ki * * * 8i
Block

1n 2n * * * Kn * * * 8n

B1 byte
1 2 * * * ** K * * * * 8
n
even - - - - - K=0
# n+1
Block
Ki = odd - - - - - K=1
1

35
 BIP Computing 　 Area

RSOH RSOH

AU PTR A U PTR
#n
counted counted
MSOH after scrambling M SOH before scram bling

B1
B1 renewed at every regenerator

# n+1 B2 B2 B2
B2 renewed only at m ultiplexer

BIP 8 for Regenerator Section BIP N x 24 for Multiplex Section

36
 Higher-Order POH Functions (VC-3, VC-4)

Path error monitor (B3) BIP-8

Path status report (G1) REI (Remote E rror Indication)
count of error (BIP-8 results)
VC-3 / VC-4
RDI (Remote Defect Indication)
receiving path AIS , signal failure
J1 path trace mismatch
Path trace (J1) verification of VC connection
B3 user programmable, 15 characters
Signal label (C2) indication of VC composition
C2 unequipped, equipped-non-specific,
G1 TUG structure, locked TU, ATM,
async. 34M or 45M, async. 140M,
F2 MAN (DQDB), F DDI
Path user channels (F2, F3) 64 kb/s clear channels
H4 APS signaling (K3) automatic protection switching at the
F3 higher order path level
V C -3 / VC-4 Position indicator (H4) multiframe position for the VC-1, VC-2
K3 pa yload Network operator byte (N1) for tandem connection maintenance
N1

REI; formerly FEBE (Far End Block Error), RD I; formerly FE RF (Far End Receive Failure)

37
VC-3/VC-4
TU-12 multiframe indication byte
POH Portion

(V4)

VC-3/VC-4 Payload 9 rows

H4(00)

PTR(V1)

H4 bits
VC-3/VC-4 Payload
H4(01) 1 2 3 4 5 6 7 8 Frame No Time
X X 1 1 X X 0 1 0 0
X X 1 1 X X 1 0 1
PTR(V2) X X 1 1 X X 1 0 2
X X 1 1 X X 1 1 3 500s TU-n multiframe
VC-3/VC-4 Payload
H4(10)
X: Bit reserved for future international standardization. Its content
shall be set to “1" in the interim.
PTR(V3)

VC-3/VC-4 Payload
H4(11)

(V4)

VC-3/VC-4 Payload
H4(00)

In H4(X Y), X Y represent bits 7 and 8 of H4

38
 Path Trace (J1)
Node A Node B Node C
Cross
connection
a
L
P
T c
b
L
P
d T

Terminated Section of J1 (J2) Path Trace

LPT: Lower Order Path Termination

[It will change to HPT(High Order Path Termination) when VC-4 J1 is used]

39
 Tandem Connection

A Network B Network (Operator Administrative area) C Network

VC VC

RS RS RS
MS MS MS RS : Regenerator Section
Tandem Connection MS: Multiplex Section
Path

B3 monitor B3 monitor

Error count Error detection (for all VCs in a bundle)

Compare
N1 byte in VC Data link (for the first VC in the bundle)
Error in TC

* The Tandem Connection is applicable to a single VC or bundled VCs.

40
 Functions of POH (VC-1x, VC-2)
Path error monitor (V5) BIP-2
V5
Path status report (V5) REI (Remote Error Indication)
count of error (BIP-2 results)
RFI (Remote Failure Indication)
RDI (Remote Defect Indication)
125µs
receiving path AIS, signal failure
J2
Signal label (V5) indication of VC composition
unequipped, equipped-non-specific,
VC-1x / VC-2

asynchronous, bit synchronous,

byte synchronous, equipped-unused
Path access point identifier (J2) verification of VC connection
N2
user programmable, 15 characters

Network operator byte (N2) for tandem connection maintenance

APS signaling (K4) automatic protection switching at the
K4 lower order path level
REI ; former FEBE (Far End Block Error)
BIP-2 REI RFI Signal Label RDI
1 2 3 4 5 6 7 8
RDI ; former FERF (Far End Receive Failure)
RFI ; formerly this bit was assigned to Path Trace
500µs V5 byte

41
 Table for SAPI & API
CRC of previous 16 multiframe for J1

maximum 15 characters (ex. Tokyo-Osaka #21)

1 C1 C2 C3 C4 C5 C6 C7 J1
(Space) 3 F Y l
125s
! 4 G Z m 0 x x x x x x x J1
(T)
“ 5 H [ n
# 6 I \ o 0 x x x x x x x J1
(o)
$ 7 J ] p
0 x x x x x x x J1
& 8 K ^ q (k)
% 9 L _ (Under Bar) r

16 multi-frame
‘ (Apostrophe) : (Colon) M ! s
( ; (Semicolon) N a t
) < O b u
* = P c v
+ > Q d w
, (Comma) ? R e x 0 x x x x x x x J1
(#)
- (Hyphen) @ S f y
0 x x x x x x x J1
. (Period) A T g z (2)
/ B U h {
0 x x x x x x x J1
0 C V i | (1)
1 D W j }
2ms
2 E X k ~
example : VC-4 or VC-3 case
Total 94 characters plus space

42
 End-to-End Maintenance Signal
Low Order Path Section
High Order Path Section
Multiplex Section
Regenerator Regenerator
Section Section
LOVC HOVC LT REG LT HOVC LOVC

LOS LOS LOP LOP

LOF LOF
AIS AIS AIS AIS
AIS AIS
RDI (FERF)

RDI (FERF)

BIP-8 BIP-8 RDI (FERF)

BIP-24N

BIP-8 REI (FEBE)

BIP-2 REI (FEBE)

REI (FEBE)

MUX
Terminal Equipment generation detection

43
 Mapping 2M Signal into VC-12
V5 V5 V5
R R R
TS0
TS1 to 15
32 bytes 32 bytes TS16
TS17 to 31
R R R
J2 J2 J2
C 1C2O O O O R R 10OOOORR R
TS0
35 bytes TS1 to 15
32 bytes 125 µs 32 bytes
TS16
140 TS17 to 31
bytes
R R R
500 µs N2 N2 N2
C1 C2 O O O O R R 10OOOORR TS 0 R
TS0 I ; information
TS1 to 15 O; overhead
32 bytes 32 bytes TS16 C; justification control
TS17 to 31
S; justification opportunity
R; fixed stuff
R R R
K4 K4 K4
C1 C2 R R R R R S1 10RRRRRR R
S2 I I I I I I I TS0
TS1 to 15
31 bytes + 7 bits 32 bytes
TS16 * The latest recommendation deleted
TS17 to 31 bit synchronous mapping.
R R R
Asynchronous Bit Synchronous Byte Synchronous

44
 Mapping 34M Signal into VC-3
J1
B3 T1 3 rows
C2
G1
F2 T2 3 rows
H4
Z3 R : Fixed stu ffing bit
K3 T3 3 rows C 1 , C2 : Justification control bit
Z5 S 1, S 2 : Justification opportunity bit
125µs I : Information bit
1 84 bytes

VC-3 POH

3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I C 3x8 I 3x8 I 3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I C 3x8 I

3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I C 3x8 I 3x8 I 3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I C 3x8 I

3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I C 3x8 I 3x8 I 3x 8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I 3x8 I A B8
I

=R RR RR RR R C = R R R R R R C1 C2 AB = R R R R R R R S1 S2 I I I I I I

45
 Mapping 140M Signal into VC-4
STM-1
1 byte 13 bytes I ; in fo r m a tio n
SOH VC-4 O ; o v e rh e a d
J1
PTR B3 C ; ju s t ifi c a tio n c o n tr o l
C2 S ; ju s t ifi c a tio n o p p o r tu n it y
G1
SOH
F2
R ; f ix e d s t u f f
H4
F3 W = I I I I I I I I
K3 X = C R R R R R OO
N1
20 blocks of 3 bytes
Y = R R R R R RRR
POH
Z = I I I I I I SR
1 1 12 bytes

POH W 96 I X 96 I Y 96 I Y 96 I Y 96 I

X 96 I Y 96 I Y 96 I Y 96 I X 96 I

Y 96 I Y 96 I Y 96 I X 96 I Y 96 I

Y 96 I Y 96 I X 96 I Y 96 I Z 96 I

46
 Mapping ATM Cell Into VC-4

V C -4
J1
B3
C2
G1
F2
H4
F3
K3
N1
VC-4 POH
header
A T M c e ll
53 bytes

47
VC-12 (2 Mb/s) to VC-4 (STM-1)
27 0 = 2 61 + 9
SOH

9 AU PTR
STM-1 SOH
125 µs
9

AU PTR
AU-4 9

125 µs
26 1 = 86 x 3 + 3
PTR
(NPI)
P
VC-4 9 O S S
H
1 2 3 1 2 3 1 2 3 1 1 2 3 125 µs

x3
86 = 12 x 7 + 2
N PTR
P
I

TUG-3 S (1) (2) (3) (4) ~ (11) (12)

S
1 2 7 1 2 7 1 2 7 7 1 2 7
125 µs
x7
12 = 4 x 3
P TR
V1
TUG-2 9 36

V2 125 µs
1 2 3 1 2 3 1 2 3 1 2 3 125 µs
36
x3
4 V3
PTR
36
9 VC 12
TU-12 R
36
125 µs
500 µs

48
Mapping of VC-12 into VC-4

49
VC-3 (34 Mb/s) to VC-4 (STM-1)

50
 Scrambler
data
+
D Q D Q D Q D Q D Q D Q D Q +
C S C S C S C S C S C S C S
clock
scrambled
set = frame pulse data
scrambler output
+
not scrambled scrambled
modulo 2 addition
1 1 1 1 1 1 1
0 1 1 1 1 1 1 1111111000000100 - - - -
A + B = C 0 0 1 1 1 1 1 1
0 0 0 1 1 1 1 2
1 + 1 = 0 0 0 0 0 1 1 1
0 0 0 0 0 1 1 3
1 + 0 = 1 0 0 0 0 0 0 1 .
1 0 0 0 0 0 0 . SOH Pay l oad
Payload
0 + 1 = 1 0 1 0 0 0 0 0 .
0 0 1 0 0 0 0
0 + 0 = 0 0 0 0 1 0 0 0 .
0 0 0 0 1 0 0 .
0 0 0 0 0 1 0
1 0 0 0 0 0 1 9
1 1 0 0 0 0 0
1111111000000100 - - - -
0 1 1 0 0 0 0
. .
. .
. .

51
 2M PDH Signal Extraction from STM-1
9 bytes 261 bytes
261= 86x3 +3
4 bytes
AU PTR (N P I) PTR
V1 V1
9 H1* * H2 * * H3 * * J1 P
1 V C -4 O S S 9
Rows 1 V5
H Row
123 123 123 1 23 36
V2
35
34
86=1 2x7+ 2 9
Row V5 2 V2
9 H1* * H2 * * H3 * *
N
PTR J2
J1 P

Rows 2 I
C-12
TUG-3 S (1 ) (2 ) (3 ) (4 ) ~ (11 ) (1 2 ) V3
V5
S 9 36 35
1 2 71 2 712 71 71 2 7 Row 3

144 140
12=4x3 V4 V3 TS
N2 2.048Mbit/s
9 H1* * H2 * * H3 * * J1 PTR TS Information
3 9
Rows 4 35
TUG-2 Row
36
1 2 3 1 2 3 1 2 3 1 2 3
TU-12（4 Multi- K4
frames）
9 H1* * H2 * * H3 * * J1
4 (4x9 Frame) V4
35
4 PTR
Rows
TU-12 VC-12 36
VC-12
STM-1 Frame （4 Multi-
TU-12 frames）
(4x9 frame) TU-12
frame in a row

52
 Contiguous & Virtual Concatenation
NE-A NE-B NE-C NE-D
STM-16 STM-1 STM-16
AU-4#1 AU-4#1
STM-1 STM-1
STM-4 AU-4#2 AU-4#2
AU-4#3 AU-4#3
AU-4#4 AU-4#4

AU-4#1

VC-4-4c AU-4#2
STM-4c AU-4-4c AU-4-4c
AU-4#3
AU-4#4

Contiguous Virtual Contiguous

Concatenation Concatenation Concatenation

53
 Virtual Concatenation

• For the transport of payloads that do not fit

efficiently into the standard set of virtual containers
(VC-3/4/12)
• VC concatenation can be used. VC concatenation is
defined for:
VC-3/4- to provide transport for payloads requiring
greater capacity than one Container-3/4;
VC-12- to provide transport for payloads that require
capacity greater than one Container-12.

54
 Contiguous Concatenation of X VC-4s
(VC-4-Xc, X=4, 16, 64, 256)

9X 261X 9N 261N

RSOH 261X RSOH 261N

3 1 3 1 N
J1 J1 J1
1 AU-4-4c PTRs B3 1 AU-4-4 PTRs B3 B3
C2 C2 C2
G1 G1 G1
Fixed
5 MSOH F2 C-4-Xc 5 MSOH F2 F2
Stuff C-4-N
H4 H4 H4
F3 F3 F3
K3 K3 K3
STM-N N1 STM-N N1 N1

X-1 VC-4-Xc VC-4-N

VC-4 POH VC-4 POH
VC-4 POH
Concatenated VC-4-Xc
VC-4-N

55
AU-4 Pointer and Concatenation Indication

a) Nine AU-4 pointer bytes H1 Y 1* 1* H2 H3 H3 H3

H1 H2

b) Normal AU-4 pointer N N N N S S I D I D I D I D I D

c) Concatenation indication 1 0 0 1 U U 1 1 1 1 1 1 1 1 1 1

(H1, H2) = AU-4 pointer, H3= pointer action byte , Y=(100UU11)

U=Unspecified, 1*=(11111111)
N = New data flag bit, S= size bit, I= increment bit, D= decrement
bit, U=Unspecified

56
 Virtual concatenation of X VC-3/4s
(VC-3/4-Xv, X=1….256)

a) VC-3-Xv Structure b) VC-4-Xv Structure

1 X X x 84 1 X X x 260
1 1

C-3-#X C-4-#X

9 9
125s 125s

1 85 1 261
1 J1 1 J1

1 B3 1 B3
85 261
1 J1 C2 1 J1 C2
G1 G1
B3 B3
F2 F2
C2 C2
H4 VC-3-Xc H4 VC-4-Xc
G1 G1
F3 F3
F2 F2
K3 K3
H4 H4
F3
9 N1 125s F3
9 N1 125s
K3 VC-3#X K3 VC-4#X
9 N1 125s 9 N1 125s
VC-3#1 VC-4#1

57
 Virtual Concatenation Multiframe Structure

a) Mulltiframe indicator MFI1 Configuration b) Mulltiframe indicator MFI2

(from Frame 0 to 15) ( from Frame 0 to 255)

No used MFI X MFI2(MSB) MFI2(LSB)

Bit No in H4 1 2 3 4 5 6 7 8 Bit No in H4 1 2 3 4 5 6 7 8
Frame 0 0 0 0 0 Frame 0 0 0 0 0 0 0 0 1
Frame 1 0 0 0 1 Frame 1 0 0 0 0 0 0 1 0 Sequencce
Frame 2 0 0 1 0 Frame 2 0 0 0 0 0 0 1 1 indiccator
SQ LSB
(bit 5-8)
Frame 14 1 1 1 0 Frame 126 0 1 1 1 1 1 1 0
Frame 15 1 1 1 1 Frame 127 0 1 1 1 1 1 1 1
Frame 128 1 0 0 0 0 0 0 0
Frame 129 1 0 0 0 0 0 0 0 Sequencce
Frame 130 1 0 0 0 0 0 0 0 indiccator
SQ MSB
(bit 1-4)
Frame 254 1 1 1 1 1 1 1 0
Frame 255 1 1 1 1 1 1 1 1

58
VC-3/VC-4-Xv multiframe and sequence
indicator
C-4/3-Xc C-4/3-Xc
1 X

POH
MFI1:0
MF12_MSB:0

POH
MFI1:0
MF12_MSB:0

POH
MFI1:1
MF12_LSB:0

POH
MFI1:1

Multiframe (MF)
MF12_LSB:0

POH
MFI1:15
POH

MFI1:15

POH
MFI1:0
MF12_MSB:0
POH

MFI1:0
MF12_MSB:0
POH

MFI1:1
MF12_LSB:1
POH

MFI1:1
MF12_LSB:1

SQ:X-1

SQ:0

59
 VC-12-Xv Structure
1 X X34
1
2
C-12#Xc
3
4
500s

1 35
1 V5
1 2 J2 35
1 V5 3 N2
VC-12#Xv
2 J2 4 K4
500s
3 N2 VC-12#X
4 K4
500s
VC-12#1

60
Capacity of virtually concatenated VC-12-Xv

If carried in X Capacity In steps of

VC-12-Xv VC-3 1 to 21 2176 kbit/s to 45 696 kbit/s 2176 kbit/s
VC-12-Xv VC-4 1 to 63 2176 kbit/s to 137 088 kbit/s 2176 kbit/s
VC-12-Xv Unspecified 1 to 64 2176 kbit/s to 139 264 kbit/s 2176 kbit/s

61
VC12 Extended Signal label byte coding
-in K4 bit 1-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 1 1 1 1 1 1 1 1 1 0 0 R R R R R R R R R R R R
MFAS Extended Signal Label

MSB LSB MFAS: Multiframe Alignment Signal

0: Zero
R: Reserved bit

MSB LSB Hex

b12 b13 b14 b15 b16 b17 b18 b19 code Interpretation
0000 0000 00 Reserved

0000 0111 07
0000 1000 08 Mapping under development
0000 1001 09 ATM mapping
0000 1010 0A Mapping of HDLC/PPP framed signal
0000 1011 0B Mapping of HDLC/LAPS framed signals
0000 1100 0C Virtually concatenated test signal, O.181
specific mapping
0000 1101 0D Flexible Topology Data Link mapping

1111 1111 FF Reserved

62
 K4 bit 2 multiframe:K4 (b2)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Frame count Sequence indicator

RRRRRRRRRRRRRRRRRRRRR

R: Reserved bit

63
64
65
 Review Questions
Fill up the spaces enclosed in parentheses in the following sentences with correct words. 　
1. B1 is to monitor a ( a ) error and B2 is for monitor a ( b ) error. For STM-4, th
e monitoring method of B1 is ( c ) and the monitoring method of B2 is ( d ).
2. K1 and K2 are called ( a ) signaling and used to exchange of transfer control informat
ion among nodes in an ( b ) Ring and a ( c ) – protection ( d ) system.
3. M1 is used to report a result of error detection by ( a ) , by number of ( b ) violatio
n.
4. G1 is used to report the receiving status of ( a ) back to the ( b ) side.
5. H4 is used to display a ( a ) number in a multiframe required to process the TU point
er.
6. ( a ) 2,048 kb/s signal is required in frequency justification between ( b ) and SDH
is necessary. ( c ) synchronous 2,048 kb/s signal is always ( d ) bit is used and (
e ) bit is not used. To indicate this status ( f ) and ( g ) are always set to 1 and
0 automatically. ( h ) synchronous 2,048 kb/s signal location of 64 kb/s channels of 2
M in VC-12 is allocated
7. SDH pointers require 10 bits (5 Is and 5 Ds) of pointer value because of the maximum possi
ble pointer offset value of AU-4 pointer is ( a )

66