COA Lecture 6

COMPUTER ORGANIZATION &
ASSEMBLY LANGUAGE
Processor Basics
OUTLINE
 Basic Operational Concepts
 Instruction Representation
 Instruction Cycle
 Processor Clock
2
REFERENCES
 Chapter 1, Ytha Yu and Charles Marut, “Assembly Language Programming
and Organization of IBM PC”
 Chapter 3, William Stallings, “Computer Organization & Architecture”
 Chapter 2, Subrata Ghoshal, “Computer Organization & Architecture”
3
BASIC OPERATIONAL
CONCEPTS
MACHINE INSTRUCTION ELEMENTS
 Each instruction must have elements that contain the
information required by the CPU for execution.
 These elements can be:
 Operation code: Specifies the operation to be performed
(e.g.. ADD, I/O). The operation is specified by a binary code,
known as the operation code, or opcode.
 Source operand reference: The operation may involve one
or more source operands, that is, operands that are inputs for
the operation.
 Result operand reference: The operation may produce a
result. Also called destination operand.
 Next instruction reference: This tells the CPU where to
fetch the next instruction.
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INSTRUCTION REPRESENTATION
 Within the computer, each instruction is represented by a
sequence of bits.
 16 bits instruction
 4 bit opcode, 6 bit operand 1, 6 bit operand 2
 4 bit opcode, 12 bit operand
Figure: A Simple Instruction Format

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CONTD..
 Binary representations of machine instructions is difficult to
remember.
 Use a symbolic representation of machine instructions.
 Opcodes are represented by abbreviations, called mnemonics,

that indicate the operation. Common examples include:
MUL
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INSTRUCTION TYPES
 Data processing: Arithmetic and logic instructions
 Data storage: Memory instructions
 Data movement: I/O instructions
 Transfer of Control: Test and branch instructions
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NO. OF ADDRESSES IN AN INSTRUCTION
 Three addresses
 Operand 1, operand 2, result
 Two addresses
 Source
 Destination
 One addresses
 Source or Destination
 Zero address
 Zero-address instructions are applicable to a special memory
organization, called a Stack. A stack is a last-in-first-out set of
locations.
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TYPES OF OPERANDS
 Machine instructions operate on data.
 The most important general categories of data are:
 Addresses
 Numbers
 Characters
 Logical data
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BASIC OPERATIONS – PROCESSOR
 Execute the software by fetching instruction from memory
 Look for any external signal and react accordingly
 Input signals from keyboard or mouse etc.
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PROCESSOR CLOCK
 Heart of any processor
 Simple digital signals at equal time intervals
 Alternate On Off states
 All activity within the CPU is synchronized with the edges
(rising or falling) of this clock signal.
Rising Edge Falling Edge
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PROGRAM COUNTER (A.K.A. BINARY
COUNTER)
 With every falling edge or rising edge (depending upon processor) of clock
signal, the counter is incremented by one.
 Width varies from processor to processor
 The contents of PC are used as target address for the memory area
Control Unit Memory

Read
(CU)
Read
PC Address
Memory address
Data Buffer Data
Data from Memory Memory

Microprocessor
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Figure: Reading from memory
BASIC INSTRUCTION CYCLE
 Fetch  Decode  Execute
 Fetch
1. Fetch an instruction from memory

2. Decode the instruction to determine the operation
3. Fetch data from memory if necessary
 Execute
4. Perform the operation on the data
5. Store the result in memory if needed
14
CONTD..
 Internal CPU Registers used in instruction cycle:
 Program Counter (PC) = Address of instruction
 Instruction Register (IR) = Instruction being executed
 Accumulator (AC) = Temporary Storage
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COMPUTER COMPONENTS: TOP LEVEL VIEW CONTD..
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DETAILED STEPS
 Address in the Program Counter register
 Program Counter (PC) holds address of next instruction to fetch
 Fetch the instruction from the memory
 Increment the Program Counter
 Unless told otherwise
 Instruction loaded into Instruction Register (IR)
 Decode the type of instruction
 Fetch the operands
 Execute the instruction
 Store the results
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EXAMPLE PROGRAM EXECUTION
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INSTRUCTION EXECUTION CYCLE
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INSTRUCTION CYCLE STATE
DIAGRAM
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INTERRUPTS
 Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
 Program
 e.g. overflow, division by zero
 Timer
 Generated by internal processor timer
 Used in pre-emptive multi-tasking
 I/O
 from I/O controller
 Hardware failure
 e.g. memory parity error
INTERRUPT CYCLE
 Added to instruction cycle
 Processor checks for interrupt
 Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
 Suspend execution of current program
 Save context
 Set PC to start address of interrupt handler routine
 Process interrupt
 Restore context and continue interrupted program
INSTRUCTION CYCLE (WITH
INTERRUPTS) - STATE DIAGRAM
MEMORY MANAGEMENT
 Memory manage through basic modes of operations
 Real Mode
 Protected mode
 Virtual mode
REAL MODE
 Only 1 MB of memory can be addresses
 Processor runs only one program at a time
 Interrupts handle momentarily
 Application program permit to read and modify any area

of RAM
 Not modify any area of ROM
 MS-DOS runs in real address mode

PROTECTED MODE
 Protected mode is native state of processor in which all
instructions and features are available.
 Programs are given separate memory area
 Protected mode allows multitasking
 Protected mode can access up to 4GB of memory

VIRTUAL MODE
 Runs in protected mode
 Creates virtual 8086 machine with its own 1 MB address
space

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COMPUTER ORGANIZATION &

Figure: A Simple Instruction Format

 Opcodes are represented by abbreviations, called mnemonics,

Rising Edge Falling Edge

Control Unit Memory

Data from Memory Memory

1. Fetch an instruction from memory

 Interrupts handle momentarily

 Application program permit to read and modify any area

 MS-DOS runs in real address mode

 Protected mode allows multitasking

 Protected mode can access up to 4GB of memory

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